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| author | Manuel Lauss <manuel.lauss@googlemail.com> | 2011-05-08 10:42:17 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-05-19 09:55:45 +0100 |
| commit | 80130204b43ce9c3b50924e4c2d44e9f2881f8c3 (patch) | |
| tree | b136768ee20f226dbe0c55e1957f19e882784a5b /arch/mips/alchemy/gpr | |
| parent | adcb86279f1e4d7a1a9f267b49441aecf4a5110a (diff) | |
| download | kernel_samsung_smdk4412-80130204b43ce9c3b50924e4c2d44e9f2881f8c3.zip kernel_samsung_smdk4412-80130204b43ce9c3b50924e4c2d44e9f2881f8c3.tar.gz kernel_samsung_smdk4412-80130204b43ce9c3b50924e4c2d44e9f2881f8c3.tar.bz2 | |
MIPS: Alchemy: Rewrite UART setup and constants.
Detect CPU type at runtime and setup uarts accordingly; also clean up the
uart base address mess in the process as far as possible.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Wolfgang Grandegger <wg@grandegger.com>
Patchwork: https://patchwork.linux-mips.org/patch/2352/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org
Diffstat (limited to 'arch/mips/alchemy/gpr')
| -rw-r--r-- | arch/mips/alchemy/gpr/board_setup.c | 14 | ||||
| -rw-r--r-- | arch/mips/alchemy/gpr/init.c | 2 |
2 files changed, 5 insertions, 11 deletions
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c index ad2e3f1..5f8f069 100644 --- a/arch/mips/alchemy/gpr/board_setup.c +++ b/arch/mips/alchemy/gpr/board_setup.c @@ -36,9 +36,6 @@ #include <prom.h> -#define UART1_ADDR KSEG1ADDR(UART1_PHYS_ADDR) -#define UART3_ADDR KSEG1ADDR(UART3_PHYS_ADDR) - char irq_tab_alchemy[][5] __initdata = { [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, }; @@ -67,18 +64,15 @@ static void gpr_power_off(void) void __init board_setup(void) { - printk(KERN_INFO "Tarpeze ITS GPR board\n"); + printk(KERN_INFO "Trapeze ITS GPR board\n"); pm_power_off = gpr_power_off; _machine_halt = gpr_power_off; _machine_restart = gpr_reset; - /* Enable UART3 */ - au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */ - au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ - /* Enable UART1 */ - au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */ - au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ + /* Enable UART1/3 */ + alchemy_uart_enable(AU1000_UART3_PHYS_ADDR); + alchemy_uart_enable(AU1000_UART1_PHYS_ADDR); /* Take away Reset of UMTS-card */ alchemy_gpio_direction_output(215, 1); diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c index f044f4c..229aafa 100644 --- a/arch/mips/alchemy/gpr/init.c +++ b/arch/mips/alchemy/gpr/init.c @@ -59,5 +59,5 @@ void __init prom_init(void) void prom_putchar(unsigned char c) { - alchemy_uart_putchar(UART0_PHYS_ADDR, c); + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); } |