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| author | Wu Zhangjin <wuzhangjin@gmail.com> | 2010-07-24 09:22:13 +0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-08-05 13:26:23 +0100 |
| commit | b8c7428af023c4cc37b8651e309713c1f4d9a18e (patch) | |
| tree | b3ed6ba799a19e545696759722b0722072202506 /arch/mips/loongson/lemote-2f | |
| parent | 4c076fb41ac93bc0cbd55f2a731cc31337804acb (diff) | |
| download | kernel_samsung_smdk4412-b8c7428af023c4cc37b8651e309713c1f4d9a18e.zip kernel_samsung_smdk4412-b8c7428af023c4cc37b8651e309713c1f4d9a18e.tar.gz kernel_samsung_smdk4412-b8c7428af023c4cc37b8651e309713c1f4d9a18e.tar.bz2 | |
MIPS: Loongson: Remove set_irq_trigger_mode()
set_irq_trigger_mode() is not needed on all platforms so remove it
and move the related source code to mach_init_irq().
This will allow gdium to share the common irq.c without adding an empty
set_irq_trigger_mode().
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1493/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/loongson/lemote-2f')
| -rw-r--r-- | arch/mips/loongson/lemote-2f/irq.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c index 1d8b4d2..c6db7e7 100644 --- a/arch/mips/loongson/lemote-2f/irq.c +++ b/arch/mips/loongson/lemote-2f/irq.c @@ -91,13 +91,6 @@ void mach_irq_dispatch(unsigned int pending) spurious_interrupt(); } -void __init set_irq_trigger_mode(void) -{ - /* setup cs5536 as high level trigger */ - LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1; - LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1); -} - static irqreturn_t ip6_action(int cpl, void *dev_id) { return IRQ_HANDLED; @@ -122,6 +115,10 @@ void __init mach_init_irq(void) * 32-63 ------> bonito irq */ + /* setup cs5536 as high level trigger */ + LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1; + LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1); + /* Sets the first-level interrupt dispatcher. */ mips_cpu_irq_init(); init_i8259_irqs(); |