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author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-19 08:22:38 +0100 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-19 18:15:58 +0100 |
commit | d527eef5b7f151320921f0ff7a88297cefc5be72 (patch) | |
tree | 8376bc3dd03818f8274a16753605cba84eee0653 /arch/mips/sibyte/sb1250 | |
parent | 93c846f9047f392fc2335668a5234edfbddb7cdc (diff) | |
download | kernel_samsung_smdk4412-d527eef5b7f151320921f0ff7a88297cefc5be72.zip kernel_samsung_smdk4412-d527eef5b7f151320921f0ff7a88297cefc5be72.tar.gz kernel_samsung_smdk4412-d527eef5b7f151320921f0ff7a88297cefc5be72.tar.bz2 |
[MIPS] Sibyte: Finish conversion to modern time APIs.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sibyte/sb1250')
-rw-r--r-- | arch/mips/sibyte/sb1250/irq.c | 36 | ||||
-rw-r--r-- | arch/mips/sibyte/sb1250/smp.c | 5 | ||||
-rw-r--r-- | arch/mips/sibyte/sb1250/time.c | 104 |
3 files changed, 30 insertions, 115 deletions
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 7659174..500d17e 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -400,43 +400,11 @@ static void sb1250_kgdb_interrupt(void) #endif /* CONFIG_KGDB */ -static inline void sb1250_timer_interrupt(void) -{ - int cpu = smp_processor_id(); - int irq = K_INT_TIMER_0 + cpu; - - irq_enter(); - kstat_this_cpu.irqs[irq]++; - - write_seqlock(&xtime_lock); - - /* ACK interrupt */ - ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); - - /* - * call the generic timer interrupt handling - */ - do_timer(1); - - write_sequnlock(&xtime_lock); - - /* - * In UP mode, we call local_timer_interrupt() to do profiling - * and process accouting. - * - * In SMP mode, local_timer_interrupt() is invoked by appropriate - * low-level local timer interrupt handler. - */ - local_timer_interrupt(irq); - - irq_exit(); -} - extern void sb1250_mailbox_interrupt(void); asmlinkage void plat_irq_dispatch(void) { + unsigned int cpu = smp_processor_id(); unsigned int pending; /* @@ -454,7 +422,7 @@ asmlinkage void plat_irq_dispatch(void) if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */ do_IRQ(MIPS_CPU_IRQ_BASE + 7); else if (pending & CAUSEF_IP4) - sb1250_timer_interrupt(); + do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */ #ifdef CONFIG_SMP else if (pending & CAUSEF_IP3) diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c index c38e1f3..aaa4f30 100644 --- a/arch/mips/sibyte/sb1250/smp.c +++ b/arch/mips/sibyte/sb1250/smp.c @@ -57,8 +57,9 @@ void sb1250_smp_init(void) void sb1250_smp_finish(void) { - extern void sb1250_time_init(void); - sb1250_time_init(); + extern void sb1250_clockevent_init(void); + + sb1250_clockevent_init(); local_irq_enable(); } diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index fe11fed..9ef5462 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c @@ -100,6 +100,7 @@ static void sibyte_set_mode(enum clock_event_mode mode, break; case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ + case CLOCK_EVT_MODE_RESUME: ; } } @@ -144,79 +145,7 @@ static struct irqaction sibyte_irqaction = { .name = "timer", }; -/* - * The general purpose timer ticks at 1 Mhz independent if - * the rest of the system - */ -static void sibyte_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - unsigned int cpu = smp_processor_id(); - void __iomem *timer_cfg, *timer_init; - - timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); - timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - __raw_writeq(0, timer_cfg); - __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init); - __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, - timer_cfg); - break; - - case CLOCK_EVT_MODE_ONESHOT: - /* Stop the timer until we actually program a shot */ - case CLOCK_EVT_MODE_SHUTDOWN: - __raw_writeq(0, timer_cfg); - break; - - case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ - ; - } -} - -static int -sibyte_next_event(unsigned long delta, struct clock_event_device *evt) -{ - unsigned int cpu = smp_processor_id(); - void __iomem *timer_cfg, *timer_init; - - timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); - timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); - - __raw_writeq(0, timer_cfg); - __raw_writeq(delta, timer_init); - __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg); - - return 0; -} - -struct clock_event_device sibyte_hpt_clockevent = { - .name = "sb1250-counter", - .features = CLOCK_EVT_FEAT_PERIODIC, - .set_mode = sibyte_set_mode, - .set_next_event = sibyte_next_event, - .shift = 32, - .irq = 0, -}; - -static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) -{ - struct clock_event_device *cd = &sibyte_hpt_clockevent; - - cd->event_handler(cd); - - return IRQ_HANDLED; -} - -static struct irqaction sibyte_irqaction = { - .handler = sibyte_counter_handler, - .flags = IRQF_DISABLED | IRQF_PERCPU, - .name = "timer", -}; - -static void __init sb1250_clockevent_init(void) +void __cpuinit sb1250_clockevent_init(void) { struct clock_event_device *cd = &sibyte_hpt_clockevent; unsigned int cpu = smp_processor_id(); @@ -249,12 +178,6 @@ static void __init sb1250_clockevent_init(void) clockevents_register_device(cd); } -void __init plat_time_init(void) -{ - sb1250_clocksource_init(); - sb1250_clockevent_init(); -} - /* * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over * again. @@ -267,3 +190,26 @@ static cycle_t sb1250_hpt_read(void) return SB1250_HPT_VALUE - count; } + +struct clocksource bcm1250_clocksource = { + .name = "MIPS", + .rating = 200, + .read = sb1250_hpt_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 32, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +void __init sb1250_clocksource_init(void) +{ + struct clocksource *cs = &bcm1250_clocksource; + + clocksource_set_clock(cs, V_SCD_TIMER_FREQ); + clocksource_register(cs); +} + +void __init plat_time_init(void) +{ + sb1250_clocksource_init(); + sb1250_clockevent_init(); +} |