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| author | Scott Wood <scottwood@freescale.com> | 2011-06-14 18:34:29 -0500 |
|---|---|---|
| committer | Avi Kivity <avi@redhat.com> | 2011-07-12 13:16:32 +0300 |
| commit | ecee273fc48f7f48f0c2f074335c43aaa790c308 (patch) | |
| tree | ba12981dbad927816a9cc51042aa2febd85fc74e /arch/powerpc/kvm/booke_interrupts.S | |
| parent | c51584d52e3878aa9b2bb98cdfb87173e7acf560 (diff) | |
| download | kernel_samsung_smdk4412-ecee273fc48f7f48f0c2f074335c43aaa790c308.zip kernel_samsung_smdk4412-ecee273fc48f7f48f0c2f074335c43aaa790c308.tar.gz kernel_samsung_smdk4412-ecee273fc48f7f48f0c2f074335c43aaa790c308.tar.bz2 | |
KVM: PPC: booke: use shadow_msr
Keep the guest MSR and the guest-mode true MSR separate, rather than
modifying the guest MSR on each guest entry to produce a true MSR.
Any bits which should be modified based on guest MSR must be explicitly
propagated from vcpu->arch.shared->msr to vcpu->arch.shadow_msr in
kvmppc_set_msr().
While we're modifying the guest entry code, reorder a few instructions
to bury some load latencies.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/kvm/booke_interrupts.S')
| -rw-r--r-- | arch/powerpc/kvm/booke_interrupts.S | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/arch/powerpc/kvm/booke_interrupts.S b/arch/powerpc/kvm/booke_interrupts.S index b58ccae..55410cc 100644 --- a/arch/powerpc/kvm/booke_interrupts.S +++ b/arch/powerpc/kvm/booke_interrupts.S @@ -24,8 +24,6 @@ #include <asm/page.h> #include <asm/asm-offsets.h> -#define KVMPPC_MSR_MASK (MSR_CE|MSR_EE|MSR_PR|MSR_DE|MSR_ME|MSR_IS|MSR_DS) - #define VCPU_GPR(n) (VCPU_GPRS + (n * 4)) /* The host stack layout: */ @@ -405,20 +403,17 @@ lightweight_exit: /* Finish loading guest volatiles and jump to guest. */ lwz r3, VCPU_CTR(r4) + lwz r5, VCPU_CR(r4) + lwz r6, VCPU_PC(r4) + lwz r7, VCPU_SHADOW_MSR(r4) mtctr r3 - lwz r3, VCPU_CR(r4) - mtcr r3 + mtcr r5 + mtsrr0 r6 + mtsrr1 r7 lwz r5, VCPU_GPR(r5)(r4) lwz r6, VCPU_GPR(r6)(r4) lwz r7, VCPU_GPR(r7)(r4) lwz r8, VCPU_GPR(r8)(r4) - lwz r3, VCPU_PC(r4) - mtsrr0 r3 - lwz r3, VCPU_SHARED(r4) - lwz r3, (VCPU_SHARED_MSR + 4)(r3) - oris r3, r3, KVMPPC_MSR_MASK@h - ori r3, r3, KVMPPC_MSR_MASK@l - mtsrr1 r3 /* Clear any debug events which occurred since we disabled MSR[DE]. * XXX This gives us a 3-instruction window in which a breakpoint |