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| author | Nathan Lynch <ntl@pobox.com> | 2007-08-09 10:50:44 +1000 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2007-08-17 11:01:53 +1000 |
| commit | 1bdb2867e5f0bca7c94f7df92f23fdd20524a488 (patch) | |
| tree | eecb27269188c1cb846400b45a309afb6723df43 /arch/powerpc/platforms/maple | |
| parent | 96b952dd4b8aaa752b6086ad8bcaf2af23729b5f (diff) | |
| download | kernel_samsung_smdk4412-1bdb2867e5f0bca7c94f7df92f23fdd20524a488.zip kernel_samsung_smdk4412-1bdb2867e5f0bca7c94f7df92f23fdd20524a488.tar.gz kernel_samsung_smdk4412-1bdb2867e5f0bca7c94f7df92f23fdd20524a488.tar.bz2 | |
[POWERPC] Remove gratuitous reads from maple PCI config space methods
The maple PCI configuration space write methods read the written
location immediately after the write is performed, presumably in order
to flush the write. However, configuration space writes are not
allowed to be posted, making these reads gratuitous. Furthermore,
this behavior potentially causes us to violate the PCI PM spec when
changing between e.g. D0 and D3 states, because a delay of up to 10ms
may be required before the OS accesses configuration space after the
write which initiates the transition. It definitely causes a system
hang for me with a Broadcom 5721 PCIE network adapter, which is fixed
by this change.
Therefore this removes the gratuitous reads from u3_agp_write_config,
u3_ht_write_config, and u4_pcie_write_config.
Signed-off-by: Nathan Lynch <ntl@pobox.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/maple')
| -rw-r--r-- | arch/powerpc/platforms/maple/pci.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c index 2542403..b095eaa 100644 --- a/arch/powerpc/platforms/maple/pci.c +++ b/arch/powerpc/platforms/maple/pci.c @@ -169,15 +169,12 @@ static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn, switch (len) { case 1: out_8(addr, val); - (void) in_8(addr); break; case 2: out_le16(addr, val); - (void) in_le16(addr); break; default: out_le32(addr, val); - (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; @@ -268,15 +265,12 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, switch (len) { case 1: out_8(addr, val); - (void) in_8(addr); break; case 2: out_le16(addr, val); - (void) in_le16(addr); break; default: out_le32(addr, val); - (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; @@ -376,15 +370,12 @@ static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, switch (len) { case 1: out_8(addr, val); - (void) in_8(addr); break; case 2: out_le16(addr, val); - (void) in_le16(addr); break; default: out_le32(addr, val); - (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; |