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author | Magnus Damm <damm@igel.co.jp> | 2008-10-31 20:15:07 +0900 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2008-12-22 18:42:50 +0900 |
commit | 7c7e02a28b4e7212dcdcc24bbd2b137790504a84 (patch) | |
tree | 09a749672364c52f8b9e850de4de8382027fb4ba /arch/sh/kernel/cpu/sh4a/clock-sh7722.c | |
parent | 1dc7b776d91ac9f016982e418e74cb14f63c5b02 (diff) | |
download | kernel_samsung_smdk4412-7c7e02a28b4e7212dcdcc24bbd2b137790504a84.zip kernel_samsung_smdk4412-7c7e02a28b4e7212dcdcc24bbd2b137790504a84.tar.gz kernel_samsung_smdk4412-7c7e02a28b4e7212dcdcc24bbd2b137790504a84.tar.bz2 |
sh: new sh_mobile mstpcr clocks base code
Add base code to handle new mstpcr clocks. Make sure clock rates propagate.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/clock-sh7722.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7722.c | 45 |
1 files changed, 41 insertions, 4 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c index 69ab62d..c7155f9 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c @@ -516,16 +516,19 @@ static struct clk_ops sh7722_video_clk_ops = { static struct clk sh7722_umem_clock = { .name = "umem_clk", .ops = &sh7722_frqcr_clk_ops, + .flags = CLK_RATE_PROPAGATES, }; static struct clk sh7722_sh_clock = { .name = "sh_clk", .ops = &sh7722_frqcr_clk_ops, + .flags = CLK_RATE_PROPAGATES, }; static struct clk sh7722_peripheral_clock = { .name = "peripheral_clk", .ops = &sh7722_frqcr_clk_ops, + .flags = CLK_RATE_PROPAGATES, }; static struct clk sh7722_sdram_clock = { @@ -533,6 +536,11 @@ static struct clk sh7722_sdram_clock = { .ops = &sh7722_frqcr_clk_ops, }; +static struct clk sh7722_r_clock = { + .name = "r_clk", + .rate = 32768, + .flags = CLK_RATE_PROPAGATES, +}; #ifndef CONFIG_CPU_SUBTYPE_SH7343 @@ -612,9 +620,16 @@ static void sh7722_mstpcr_disable(struct clk *clk) sh7722_mstpcr_start_stop(clk, 0); } +static void sh7722_mstpcr_recalc(struct clk *clk) +{ + if (clk->parent) + clk->rate = clk->parent->rate; +} + static struct clk_ops sh7722_mstpcr_clk_ops = { .enable = sh7722_mstpcr_enable, .disable = sh7722_mstpcr_disable, + .recalc = sh7722_mstpcr_recalc, }; #define DECLARE_MSTPCRN(regnr, bitnr, bitstr) \ @@ -664,6 +679,16 @@ static struct clk sh7722_mstpcr[] = { DECLARE_MSTPCR(2), }; +#define MSTPCR(_name, _parent, regnr, bitnr) \ +{ \ + .name = _name, \ + .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \ + .ops = (void *)_parent, \ +} + +static struct clk sh7722_mstpcr_clocks[] = { +}; + static struct clk *sh7722_clocks[] = { &sh7722_umem_clock, &sh7722_sh_clock, @@ -698,16 +723,28 @@ arch_init_clk_ops(struct clk_ops **ops, int type) int __init arch_clk_init(void) { - struct clk *master; + struct clk *clk; int i; - master = clk_get(NULL, "master_clk"); + clk = clk_get(NULL, "master_clk"); for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) { pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name); - sh7722_clocks[i]->parent = master; + sh7722_clocks[i]->parent = clk; clk_register(sh7722_clocks[i]); } - clk_put(master); + clk_put(clk); + + clk_register(&sh7722_r_clock); + + for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr_clocks); i++) { + pr_debug( "Registering mstpcr clock '%s'\n", + sh7722_mstpcr_clocks[i].name); + clk = clk_get(NULL, (void *) sh7722_mstpcr_clocks[i].ops); + sh7722_mstpcr_clocks[i].parent = clk; + sh7722_mstpcr_clocks[i].ops = &sh7722_mstpcr_clk_ops; + clk_register(&sh7722_mstpcr_clocks[i]); + clk_put(clk); + } for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr); i++) { pr_debug( "Registering mstpcr '%s'\n", sh7722_mstpcr[i].name); |