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authorDavid S. Miller <davem@sunset.davemloft.net>2006-02-04 00:10:01 -0800
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 01:11:36 -0800
commit314ef6859750b6539eac48d78059bb7986f29cb1 (patch)
tree26c7da386349c1cf377225356e1012ae62da6f07 /arch/sparc64/kernel/ttable.S
parentffe483d55229fadbaf4cc7316d47024a24ecd1a2 (diff)
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[SPARC64]: Refine register window trap handling.
When saving and restoing trap state, do the window spill/fill handling inline so that we never trap deeper than 2 trap levels. This is important for chips like Niagara. The window fixup code is massively simplified, and many more improvements are now possible. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/ttable.S')
-rw-r--r--arch/sparc64/kernel/ttable.S16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/sparc64/kernel/ttable.S b/arch/sparc64/kernel/ttable.S
index 9953142..2679b6e 100644
--- a/arch/sparc64/kernel/ttable.S
+++ b/arch/sparc64/kernel/ttable.S
@@ -92,11 +92,11 @@ tl0_resv07c: BTRAP(0x7c) BTRAP(0x7d) BTRAP(0x7e) BTRAP(0x7f)
tl0_s0n: SPILL_0_NORMAL
tl0_s1n: SPILL_1_NORMAL
tl0_s2n: SPILL_2_NORMAL
-tl0_s3n: SPILL_3_NORMAL
-tl0_s4n: SPILL_4_NORMAL
-tl0_s5n: SPILL_5_NORMAL
-tl0_s6n: SPILL_6_NORMAL
-tl0_s7n: SPILL_7_NORMAL
+tl0_s3n: SPILL_0_NORMAL_ETRAP
+tl0_s4n: SPILL_1_GENERIC_ETRAP
+tl0_s5n: SPILL_1_GENERIC_ETRAP_FIXUP
+tl0_s6n: SPILL_2_GENERIC_ETRAP
+tl0_s7n: SPILL_2_GENERIC_ETRAP_FIXUP
tl0_s0o: SPILL_0_OTHER
tl0_s1o: SPILL_1_OTHER
tl0_s2o: SPILL_2_OTHER
@@ -110,9 +110,9 @@ tl0_f1n: FILL_1_NORMAL
tl0_f2n: FILL_2_NORMAL
tl0_f3n: FILL_3_NORMAL
tl0_f4n: FILL_4_NORMAL
-tl0_f5n: FILL_5_NORMAL
-tl0_f6n: FILL_6_NORMAL
-tl0_f7n: FILL_7_NORMAL
+tl0_f5n: FILL_0_NORMAL_RTRAP
+tl0_f6n: FILL_1_GENERIC_RTRAP
+tl0_f7n: FILL_2_GENERIC_RTRAP
tl0_f0o: FILL_0_OTHER
tl0_f1o: FILL_1_OTHER
tl0_f2o: FILL_2_OTHER