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authorSuresh Siddha <suresh.b.siddha@intel.com>2008-08-23 17:47:10 +0200
committerIngo Molnar <mingo@elte.hu>2008-08-23 17:47:10 +0200
commitbbb65d2d365efe9951290e61678dcf81ec60add4 (patch)
treef3eacf1b1313d729e084064ed6dda5db64522bf4 /arch/x86/kernel/cpu/intel.c
parent87ce786ae5f24e336195805a9fc7428a6f922478 (diff)
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x86: use cpuid vector 0xb when available for detecting cpu topology
cpuid leaf 0xb provides extended topology enumeration. This interface provides the 32-bit x2APIC id of the logical processor and it also provides a new mechanism to detect SMT and core siblings (which provides increased addressability). Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
-rw-r--r--arch/x86/kernel/cpu/intel.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 77618c7..58a6f1a 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -176,9 +176,16 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
if (p)
strcpy(c->x86_model_id, p);
- c->x86_max_cores = num_cpu_cores(c);
-
- detect_ht(c);
+ detect_extended_topology(c);
+
+ if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
+ /*
+ * let's use the legacy cpuid vector 0x1 and 0x4 for topology
+ * detection.
+ */
+ c->x86_max_cores = num_cpu_cores(c);
+ detect_ht(c);
+ }
/* Work around errata */
Intel_errata_workarounds(c);