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| author | Ralf Baechle <ralf@linux-mips.org> | 2015-03-25 13:14:16 +0100 |
|---|---|---|
| committer | Ben Hutchings <ben@decadent.org.uk> | 2015-08-07 00:32:19 +0100 |
| commit | 8feb2a714b3478b2cde5c576fd9f47ef44b60e8d (patch) | |
| tree | 9141741b662a3be03226e70db98440c4b029cb2f /arch | |
| parent | 53493d44a771a3155ee12b6ac668fb2543d21a7a (diff) | |
| download | kernel_samsung_smdk4412-8feb2a714b3478b2cde5c576fd9f47ef44b60e8d.zip kernel_samsung_smdk4412-8feb2a714b3478b2cde5c576fd9f47ef44b60e8d.tar.gz kernel_samsung_smdk4412-8feb2a714b3478b2cde5c576fd9f47ef44b60e8d.tar.bz2 | |
MIPS: Fix cpu_has_mips_r2_exec_hazard.
commit 9cdf30bd3bac697fc533988f44a117434a858f69 upstream.
Returns a non-zero value if the current processor implementation requires
an IHB instruction to deal with an instruction hazard as per MIPS R2
architecture specification, zero otherwise.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[bwh: Backported to 3.2: trim the CPU type list]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index ca400f7..0f4991b 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -153,8 +153,32 @@ #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ cpu_has_mips64r1 | cpu_has_mips64r2) +/* + * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor + * + * Returns non-zero value if the current processor implementation requires + * an IHB instruction to deal with an instruction hazard as per MIPS R2 + * architecture specification, zero otherwise. + */ #ifndef cpu_has_mips_r2_exec_hazard -#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2 +#define cpu_has_mips_r2_exec_hazard \ +({ \ + int __res; \ + \ + switch (current_cpu_type()) { \ + case CPU_74K: \ + case CPU_CAVIUM_OCTEON: \ + case CPU_CAVIUM_OCTEON_PLUS: \ + case CPU_CAVIUM_OCTEON2: \ + __res = 0; \ + break; \ + \ + default: \ + __res = 1; \ + } \ + \ + __res; \ +}) #endif /* |