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authorAndrew Isaacson <adi@broadcom.com>2005-10-19 23:54:43 -0700
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 19:32:45 +0100
commitd121ced21d79eab7726bfe6b1e33da4ae86072c0 (patch)
treea673fe4d3e3c49179b68c3185ef331712df9e716 /arch
parent485a4a928a059a361c7363e7ce0eab330a09dbd3 (diff)
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Sibyte fixes
Fix typo in cpu_probe_sibyte. Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/kernel/cpu-probe.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 72c580d..f7a8415 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -612,7 +612,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
* cache code which eventually will be folded into c-r4k.c. Until
* then we pretend it's got it's own cache architecture.
*/
- c->options &= MIPS_CPU_4K_CACHE;
+ c->options &= ~MIPS_CPU_4K_CACHE;
c->options |= MIPS_CPU_SB1_CACHE;
switch (c->processor_id & 0xff00) {