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| author | Alex Deucher <alexdeucher@gmail.com> | 2011-05-20 12:36:12 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@gmail.com> | 2011-05-22 20:20:05 +1000 |
| commit | 6f15c506e0cec601fad9fabb7ded0d1811b8002f (patch) | |
| tree | 014495d41f3db1388f08412a4d690267b95bf99e /drivers/char | |
| parent | d291767b6056540277497d91baa9120428d7cd1a (diff) | |
| download | kernel_samsung_smdk4412-6f15c506e0cec601fad9fabb7ded0d1811b8002f.zip kernel_samsung_smdk4412-6f15c506e0cec601fad9fabb7ded0d1811b8002f.tar.gz kernel_samsung_smdk4412-6f15c506e0cec601fad9fabb7ded0d1811b8002f.tar.bz2 | |
drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices
If the ss clock is external, the CLK_REF bit needs to be set
in the SetPixelClock parameters. This should fix DP failures
in the channel equalization loop.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>
Diffstat (limited to 'drivers/char')
0 files changed, 0 insertions, 0 deletions