samsung update 1

5 files changed, 1076 insertions, 92 deletions

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 2967002..c16e914 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -88,7 +88,11 @@ config GPIO_IT8761E
 
 config GPIO_EXYNOS4
 	def_bool y
-	depends on CPU_EXYNOS4210
+	depends on ARCH_EXYNOS4
+
+config GPIO_EXYNOS5
+	def_bool y
+	depends on ARCH_EXYNOS5
 
 config GPIO_PLAT_SAMSUNG
 	def_bool y
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index b605f8e..f141bb5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_GPIO_ADP5588)	+= adp5588-gpio.o
 obj-$(CONFIG_GPIO_BASIC_MMIO_CORE)	+= basic_mmio_gpio.o
 obj-$(CONFIG_GPIO_BASIC_MMIO)	+= basic_mmio_gpio.o
 obj-$(CONFIG_GPIO_EXYNOS4)	+= gpio-exynos4.o
+obj-$(CONFIG_GPIO_EXYNOS5)	+= gpio-exynos5.o
 obj-$(CONFIG_GPIO_PLAT_SAMSUNG)	+= gpio-plat-samsung.o
 obj-$(CONFIG_GPIO_S5PC100)	+= gpio-s5pc100.o
 obj-$(CONFIG_GPIO_S5PV210)	+= gpio-s5pv210.o
diff --git a/drivers/gpio/gpio-exynos4.c b/drivers/gpio/gpio-exynos4.c
index 9029835..01b827b 100644
--- a/drivers/gpio/gpio-exynos4.c
+++ b/drivers/gpio/gpio-exynos4.c
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-exynos4/gpiolib.c
+/* linux/drivers/gpio/gpio-exynos4.c
  *
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
@@ -20,6 +20,7 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
+#include <plat/cpu.h>
 
 int s3c_gpio_setpull_exynos4(struct s3c_gpio_chip *chip,
 				unsigned int off, s3c_gpio_pull_t pull)
@@ -55,7 +56,7 @@ static struct s3c_gpio_cfg gpio_cfg_noint = {
 };
 
 /*
- * Following are the gpio banks in v310.
+ * Following are the gpio banks in exynos4.
  *
  * The 'config' member when left to NULL, is initialized to the default
  * structure gpio_cfg in the init function below.
@@ -64,162 +65,176 @@ static struct s3c_gpio_cfg gpio_cfg_noint = {
  * Note: The initialization of 'base' member of s3c_gpio_chip structure
  * uses the above macro and depends on the banks being listed in order here.
  */
-static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
+static struct s3c_gpio_pm s3c_gpio_pm_nop = { NULL, NULL };
+
+static struct s3c_gpio_chip exynos4_gpio_common_4bit[] = {
 	{
+		.base	= S5P_VA_GPIO1,
+		.eint_offset = 0x0,
+		.group	= 0,
 		.chip	= {
 			.base	= EXYNOS4_GPA0(0),
 			.ngpio	= EXYNOS4_GPIO_A0_NR,
 			.label	= "GPA0",
 		},
 	}, {
+		.base	= (S5P_VA_GPIO1 + 0x20),
+		.eint_offset = 0x4,
+		.group	= 1,
 		.chip	= {
 			.base	= EXYNOS4_GPA1(0),
 			.ngpio	= EXYNOS4_GPIO_A1_NR,
 			.label	= "GPA1",
 		},
 	}, {
+		.base	= (S5P_VA_GPIO1 + 0x40),
+		.eint_offset = 0x8,
+		.group	= 2,
 		.chip	= {
 			.base	= EXYNOS4_GPB(0),
 			.ngpio	= EXYNOS4_GPIO_B_NR,
 			.label	= "GPB",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO1 + 0x60),
+		.eint_offset = 0xC,
+		.group	= 3,
 		.chip	= {
 			.base	= EXYNOS4_GPC0(0),
 			.ngpio	= EXYNOS4_GPIO_C0_NR,
 			.label	= "GPC0",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO1 + 0x80),
+		.eint_offset = 0x10,
+		.group	= 4,
 		.chip	= {
 			.base	= EXYNOS4_GPC1(0),
 			.ngpio	= EXYNOS4_GPIO_C1_NR,
 			.label	= "GPC1",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO1 + 0xA0),
+		.eint_offset = 0x14,
+		.group	= 5,
 		.chip	= {
 			.base	= EXYNOS4_GPD0(0),
 			.ngpio	= EXYNOS4_GPIO_D0_NR,
 			.label	= "GPD0",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO1 + 0xC0),
+		.eint_offset = 0x18,
+		.group	= 6,
 		.chip	= {
 			.base	= EXYNOS4_GPD1(0),
 			.ngpio	= EXYNOS4_GPIO_D1_NR,
 			.label	= "GPD1",
 		},
 	}, {
-		.chip	= {
-			.base	= EXYNOS4_GPE0(0),
-			.ngpio	= EXYNOS4_GPIO_E0_NR,
-			.label	= "GPE0",
-		},
-	}, {
-		.chip	= {
-			.base	= EXYNOS4_GPE1(0),
-			.ngpio	= EXYNOS4_GPIO_E1_NR,
-			.label	= "GPE1",
-		},
-	}, {
-		.chip	= {
-			.base	= EXYNOS4_GPE2(0),
-			.ngpio	= EXYNOS4_GPIO_E2_NR,
-			.label	= "GPE2",
-		},
-	}, {
-		.chip	= {
-			.base	= EXYNOS4_GPE3(0),
-			.ngpio	= EXYNOS4_GPIO_E3_NR,
-			.label	= "GPE3",
-		},
-	}, {
-		.chip	= {
-			.base	= EXYNOS4_GPE4(0),
-			.ngpio	= EXYNOS4_GPIO_E4_NR,
-			.label	= "GPE4",
-		},
-	}, {
+		.base   = (S5P_VA_GPIO1 + 0x180),
+		.eint_offset = 0x30,
+		.group	= 7,
 		.chip	= {
 			.base	= EXYNOS4_GPF0(0),
 			.ngpio	= EXYNOS4_GPIO_F0_NR,
 			.label	= "GPF0",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO1 + 0x1A0),
+		.eint_offset = 0x34,
+		.group	= 8,
 		.chip	= {
 			.base	= EXYNOS4_GPF1(0),
 			.ngpio	= EXYNOS4_GPIO_F1_NR,
 			.label	= "GPF1",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO1 + 0x1C0),
+		.eint_offset = 0x38,
+		.group	= 9,
 		.chip	= {
 			.base	= EXYNOS4_GPF2(0),
 			.ngpio	= EXYNOS4_GPIO_F2_NR,
 			.label	= "GPF2",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO1 + 0x1E0),
+		.eint_offset = 0x3C,
+		.group	= 10,
 		.chip	= {
 			.base	= EXYNOS4_GPF3(0),
 			.ngpio	= EXYNOS4_GPIO_F3_NR,
 			.label	= "GPF3",
 		},
-	},
-};
-
-static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
-	{
-		.chip	= {
-			.base	= EXYNOS4_GPJ0(0),
-			.ngpio	= EXYNOS4_GPIO_J0_NR,
-			.label	= "GPJ0",
-		},
-	}, {
-		.chip	= {
-			.base	= EXYNOS4_GPJ1(0),
-			.ngpio	= EXYNOS4_GPIO_J1_NR,
-			.label	= "GPJ1",
-		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0x40),
+		.eint_offset = 0x8,
+		.group	= 16,
 		.chip	= {
 			.base	= EXYNOS4_GPK0(0),
 			.ngpio	= EXYNOS4_GPIO_K0_NR,
 			.label	= "GPK0",
 		},
+#ifdef CONFIG_MACH_MIDAS
+		.pm	= &s3c_gpio_pm_nop,
+#endif
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0x60),
+		.eint_offset = 0xC,
+		.group	= 17,
 		.chip	= {
 			.base	= EXYNOS4_GPK1(0),
 			.ngpio	= EXYNOS4_GPIO_K1_NR,
 			.label	= "GPK1",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0x80),
+		.eint_offset = 0x10,
+		.group	= 18,
 		.chip	= {
 			.base	= EXYNOS4_GPK2(0),
 			.ngpio	= EXYNOS4_GPIO_K2_NR,
 			.label	= "GPK2",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0xA0),
+		.eint_offset = 0x14,
+		.group	= 19,
 		.chip	= {
 			.base	= EXYNOS4_GPK3(0),
 			.ngpio	= EXYNOS4_GPIO_K3_NR,
 			.label	= "GPK3",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0xC0),
+		.eint_offset = 0x18,
+		.group	= 20,
 		.chip	= {
 			.base	= EXYNOS4_GPL0(0),
 			.ngpio	= EXYNOS4_GPIO_L0_NR,
 			.label	= "GPL0",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0xE0),
+		.eint_offset = 0x1C,
+		.group	= 21,
 		.chip	= {
 			.base	= EXYNOS4_GPL1(0),
 			.ngpio	= EXYNOS4_GPIO_L1_NR,
 			.label	= "GPL1",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0x100),
+		.eint_offset = 0x20,
+		.group	= 22,
 		.chip	= {
 			.base	= EXYNOS4_GPL2(0),
 			.ngpio	= EXYNOS4_GPIO_L2_NR,
 			.label	= "GPL2",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0x120),
 		.config	= &gpio_cfg_noint,
 		.chip	= {
 			.base	= EXYNOS4_GPY0(0),
@@ -227,6 +242,7 @@ static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
 			.label	= "GPY0",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0x140),
 		.config	= &gpio_cfg_noint,
 		.chip	= {
 			.base	= EXYNOS4_GPY1(0),
@@ -234,6 +250,7 @@ static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
 			.label	= "GPY1",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0x160),
 		.config	= &gpio_cfg_noint,
 		.chip	= {
 			.base	= EXYNOS4_GPY2(0),
@@ -241,6 +258,7 @@ static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
 			.label	= "GPY2",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0x180),
 		.config	= &gpio_cfg_noint,
 		.chip	= {
 			.base	= EXYNOS4_GPY3(0),
@@ -248,6 +266,7 @@ static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
 			.label	= "GPY3",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0x1A0),
 		.config	= &gpio_cfg_noint,
 		.chip	= {
 			.base	= EXYNOS4_GPY4(0),
@@ -255,6 +274,7 @@ static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
 			.label	= "GPY4",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0x1C0),
 		.config	= &gpio_cfg_noint,
 		.chip	= {
 			.base	= EXYNOS4_GPY5(0),
@@ -262,6 +282,7 @@ static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
 			.label	= "GPY5",
 		},
 	}, {
+		.base   = (S5P_VA_GPIO2 + 0x1E0),
 		.config	= &gpio_cfg_noint,
 		.chip	= {
 			.base	= EXYNOS4_GPY6(0),
@@ -308,76 +329,344 @@ static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
 			.label	= "GPX3",
 			.to_irq	= samsung_gpiolib_to_irq,
 		},
+	}, {
+		.base   = S5P_VA_GPIO3,
+		.chip	= {
+			.base	= EXYNOS4_GPZ(0),
+			.ngpio	= EXYNOS4_GPIO_Z_NR,
+			.label	= "GPZ",
+		},
 	},
 };
 
-static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
+static struct s3c_gpio_chip exynos4210_gpio_4bit[] = {
 	{
+		.base   = (S5P_VA_GPIO1 + 0xE0),
+		.eint_offset = 0x1C,
+		.group	= 11,
 		.chip	= {
-			.base	= EXYNOS4_GPZ(0),
-			.ngpio	= EXYNOS4_GPIO_Z_NR,
-			.label	= "GPZ",
+			.base	= EXYNOS4210_GPE0(0),
+			.ngpio	= EXYNOS4210_GPIO_E0_NR,
+			.label	= "GPE0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x100),
+		.eint_offset = 0x20,
+		.group	= 12,
+		.chip	= {
+			.base	= EXYNOS4210_GPE1(0),
+			.ngpio	= EXYNOS4210_GPIO_E1_NR,
+			.label	= "GPE1",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x120),
+		.eint_offset = 0x24,
+		.group	= 13,
+		.chip	= {
+			.base	= EXYNOS4210_GPE2(0),
+			.ngpio	= EXYNOS4210_GPIO_E2_NR,
+			.label	= "GPE2",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x140),
+		.eint_offset = 0x28,
+		.group	= 14,
+		.chip	= {
+			.base	= EXYNOS4210_GPE3(0),
+			.ngpio	= EXYNOS4210_GPIO_E3_NR,
+			.label	= "GPE3",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x160),
+		.eint_offset = 0x2C,
+		.group	= 15,
+		.chip	= {
+			.base	= EXYNOS4210_GPE4(0),
+			.ngpio	= EXYNOS4210_GPIO_E4_NR,
+			.label	= "GPE4",
+		},
+	}, {
+		.base   = S5P_VA_GPIO2,
+		.group	= 23,
+		.eint_offset = 0x0,
+		.chip	= {
+			.base	= EXYNOS4210_GPJ0(0),
+			.ngpio	= EXYNOS4210_GPIO_J0_NR,
+			.label	= "GPJ0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x20),
+		.eint_offset = 0x4,
+		.group	= 24,
+		.chip	= {
+			.base	= EXYNOS4210_GPJ1(0),
+			.ngpio	= EXYNOS4210_GPIO_J1_NR,
+			.label	= "GPJ1",
 		},
 	},
 };
 
+static struct s3c_gpio_chip exynos4212_gpio_4bit[] = {
+	{
+		.base   = (S5P_VA_GPIO1 + 0x240),
+		.eint_offset = 0x40,
+		.group	= 11,
+		.chip	= {
+			.base	= EXYNOS4212_GPJ0(0),
+			.ngpio	= EXYNOS4212_GPIO_J0_NR,
+			.label	= "GPJ0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x260),
+		.eint_offset = 0x44,
+		.group	= 12,
+		.chip	= {
+			.base	= EXYNOS4212_GPJ1(0),
+			.ngpio	= EXYNOS4212_GPIO_J1_NR,
+			.label	= "GPJ1",
+		}
+	}, {
+		.base	= (S5P_VA_GPIO2 + 0x260),
+		.eint_offset = 0x24,
+		.group	= 23,
+		.chip	= {
+			.base	= EXYNOS4212_GPM0(0),
+			.ngpio	= EXYNOS4212_GPIO_M0_NR,
+			.label	= "GPM0",
+		},
+	}, {
+		.base	= (S5P_VA_GPIO2 + 0x280),
+		.eint_offset = 0x28,
+		.group	= 24,
+		.chip	= {
+			.base	= EXYNOS4212_GPM1(0),
+			.ngpio	= EXYNOS4212_GPIO_M1_NR,
+			.label	= "GPM1",
+		},
+	}, {
+		.base	= (S5P_VA_GPIO2 + 0x2A0),
+		.eint_offset = 0x2C,
+		.group	= 25,
+		.chip	= {
+			.base	= EXYNOS4212_GPM2(0),
+			.ngpio	= EXYNOS4212_GPIO_M2_NR,
+			.label	= "GPM2",
+		},
+	}, {
+		.base	= (S5P_VA_GPIO2 + 0x2C0),
+		.eint_offset = 0x30,
+		.group	= 26,
+		.chip	= {
+			.base	= EXYNOS4212_GPM3(0),
+			.ngpio	= EXYNOS4212_GPIO_M3_NR,
+			.label	= "GPM3",
+		},
+	}, {
+		.base	= (S5P_VA_GPIO2 + 0x2E0),
+		.eint_offset = 0x34,
+		.group	= 27,
+		.chip	= {
+			.base	= EXYNOS4212_GPM4(0),
+			.ngpio	= EXYNOS4212_GPIO_M4_NR,
+			.label	= "GPM4",
+		},
+	}, {
+		.base   = S5P_VA_GPIO4,
+		.eint_offset = 0x00,
+		.group	= 28,
+		.chip	= {
+			.base	= EXYNOS4212_GPV0(0),
+			.ngpio	= EXYNOS4212_GPIO_V0_NR,
+			.label	= "GPV0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO4 + 0x20),
+		.eint_offset = 0x04,
+		.group	= 29,
+		.chip	= {
+			.base	= EXYNOS4212_GPV1(0),
+			.ngpio	= EXYNOS4212_GPIO_V1_NR,
+			.label	= "GPV1",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO4 + 0x60),
+		.eint_offset = 0x08,
+		.group	= 30,
+		.chip	= {
+			.base	= EXYNOS4212_GPV2(0),
+			.ngpio	= EXYNOS4212_GPIO_V2_NR,
+			.label	= "GPV2",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO4 + 0x80),
+		.eint_offset = 0x0C,
+		.group	= 31,
+		.chip	= {
+			.base	= EXYNOS4212_GPV3(0),
+			.ngpio	= EXYNOS4212_GPIO_V3_NR,
+			.label	= "GPV3",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO4 + 0xC0),
+		.eint_offset = 0x10,
+		.group	= 32,
+		.chip	= {
+			.base	= EXYNOS4212_GPV4(0),
+			.ngpio	= EXYNOS4212_GPIO_V4_NR,
+			.label	= "GPV4",
+		},
+	},
+};
+
+/* EXYNOS4 machine dependent GPIO help function */
+int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config)
+{
+	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+	void __iomem *reg;
+	unsigned long flags;
+	int offset;
+	u32 con;
+	int shift;
+
+	if (!chip)
+		return -EINVAL;
+
+	if ((pin >= EXYNOS4_GPX0(0)) && (pin <= EXYNOS4_GPX3(7)))
+		return -EINVAL;
+
+	if (config > S3C_GPIO_SLP_PREV)
+		return -EINVAL;
+
+	reg = chip->base + 0x10;
+
+	offset = pin - chip->chip.base;
+	shift = offset * 2;
+
+	local_irq_save(flags);
+
+	con = __raw_readl(reg);
+	con &= ~(3 << shift);
+	con |= config << shift;
+	__raw_writel(con, reg);
+
+	local_irq_restore(flags);
+	return 0;
+}
+
+s3c_gpio_pull_t s3c_gpio_get_slp_cfgpin(unsigned int pin)
+{
+	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+	void __iomem *reg;
+	unsigned long flags;
+	int offset;
+	u32 con;
+	int shift;
+
+	if (!chip)
+		return -EINVAL;
+
+	if ((pin >= EXYNOS4_GPX0(0)) && (pin <= EXYNOS4_GPX3(7)))
+		return -EINVAL;
+
+	reg = chip->base + 0x10;
+
+	offset = pin - chip->chip.base;
+	shift = offset * 2;
+
+	local_irq_save(flags);
+
+	con = __raw_readl(reg);
+	con >>= shift;
+	con &= 0x3;
+
+	local_irq_restore(flags);
+
+	return (__force s3c_gpio_pull_t)con;
+}
+
+int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config)
+{
+	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+	void __iomem *reg;
+	unsigned long flags;
+	int offset;
+	u32 con;
+	int shift;
+
+	if (!chip)
+		return -EINVAL;
+
+	if ((pin >= EXYNOS4_GPX0(0)) && (pin <= EXYNOS4_GPX3(7)))
+		return -EINVAL;
+
+	if (config > S3C_GPIO_PULL_UP)
+		return -EINVAL;
+
+	reg = chip->base + 0x14;
+
+	offset = pin - chip->chip.base;
+	shift = offset * 2;
+
+	local_irq_save(flags);
+
+	con = __raw_readl(reg);
+	con &= ~(3 << shift);
+	con |= config << shift;
+	__raw_writel(con, reg);
+
+	local_irq_restore(flags);
+
+	return 0;
+}
+
 static __init int exynos4_gpiolib_init(void)
 {
 	struct s3c_gpio_chip *chip;
 	int i;
-	int group = 0;
 	int nr_chips;
 
-	/* GPIO part 1 */
+	/* GPIO common part  */
 
-	chip = exynos4_gpio_part1_4bit;
-	nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
+	chip = exynos4_gpio_common_4bit;
+	nr_chips = ARRAY_SIZE(exynos4_gpio_common_4bit);
 
 	for (i = 0; i < nr_chips; i++, chip++) {
-		if (chip->config == NULL) {
+		if (chip->config == NULL)
 			chip->config = &gpio_cfg;
-			/* Assign the GPIO interrupt group */
-			chip->group = group++;
-		}
 		if (chip->base == NULL)
-			chip->base = S5P_VA_GPIO1 + (i) * 0x20;
+			pr_err("No allocation of base address for [common gpio]");
 	}
 
-	samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
+	samsung_gpiolib_add_4bit_chips(exynos4_gpio_common_4bit, nr_chips);
 
-	/* GPIO part 2 */
+	/* Only 4210 GPIO  part */
+	if (soc_is_exynos4210()) {
+		chip = exynos4210_gpio_4bit;
+		nr_chips = ARRAY_SIZE(exynos4210_gpio_4bit);
 
-	chip = exynos4_gpio_part2_4bit;
-	nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
-
-	for (i = 0; i < nr_chips; i++, chip++) {
-		if (chip->config == NULL) {
-			chip->config = &gpio_cfg;
-			/* Assign the GPIO interrupt group */
-			chip->group = group++;
+		for (i = 0; i < nr_chips; i++, chip++) {
+			if (chip->config == NULL)
+				chip->config = &gpio_cfg;
+			if (chip->base == NULL)
+				pr_err("No allocation of base address [4210 gpio]");
 		}
-		if (chip->base == NULL)
-			chip->base = S5P_VA_GPIO2 + (i) * 0x20;
-	}
-
-	samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
-
-	/* GPIO part 3 */
 
-	chip = exynos4_gpio_part3_4bit;
-	nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
+		samsung_gpiolib_add_4bit_chips(exynos4210_gpio_4bit, nr_chips);
+	} else {
+	/* Only 4212/4412 GPIO part */
+		chip = exynos4212_gpio_4bit;
+		nr_chips = ARRAY_SIZE(exynos4212_gpio_4bit);
 
-	for (i = 0; i < nr_chips; i++, chip++) {
-		if (chip->config == NULL) {
-			chip->config = &gpio_cfg;
-			/* Assign the GPIO interrupt group */
-			chip->group = group++;
+		for (i = 0; i < nr_chips; i++, chip++) {
+			if (chip->config == NULL)
+				chip->config = &gpio_cfg;
+			if (chip->base == NULL)
+				pr_err("No allocation of base address [4212 gpio]");
 		}
-		if (chip->base == NULL)
-			chip->base = S5P_VA_GPIO3 + (i) * 0x20;
+
+		samsung_gpiolib_add_4bit_chips(exynos4212_gpio_4bit, nr_chips);
 	}
 
-	samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
 	s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
 	s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
 
diff --git a/drivers/gpio/gpio-exynos5.c b/drivers/gpio/gpio-exynos5.c
new file mode 100644
index 0000000..1817920
--- /dev/null
+++ b/drivers/gpio/gpio-exynos5.c
@@ -0,0 +1,655 @@
+/* driver/gpio/gpio-exynos5.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5 - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+#include <plat/cpu.h>
+
+int s3c_gpio_setpull_exynos5(struct s3c_gpio_chip *chip,
+				unsigned int off, s3c_gpio_pull_t pull)
+{
+	if (pull == S3C_GPIO_PULL_UP)
+		pull = 3;
+
+	return s3c_gpio_setpull_updown(chip, off, pull);
+}
+
+s3c_gpio_pull_t s3c_gpio_getpull_exynos5(struct s3c_gpio_chip *chip,
+						unsigned int off)
+{
+	s3c_gpio_pull_t pull;
+
+	pull = s3c_gpio_getpull_updown(chip, off);
+	if (pull == 3)
+		pull = S3C_GPIO_PULL_UP;
+
+	return pull;
+}
+
+static struct s3c_gpio_cfg gpio_cfg = {
+	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
+	.set_pull	= s3c_gpio_setpull_exynos5,
+	.get_pull	= s3c_gpio_getpull_exynos5,
+};
+
+static struct s3c_gpio_cfg gpio_cfg_noint = {
+	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
+	.set_pull	= s3c_gpio_setpull_exynos5,
+	.get_pull	= s3c_gpio_getpull_exynos5,
+};
+
+/*
+ * Following are the gpio banks in exynos5.
+ *
+ * The 'config' member when left to NULL, is initialized to the default
+ * structure gpio_cfg in the init function below.
+ *
+ * The 'base' member is also initialized in the init function below.
+ * Note: The initialization of 'base' member of s3c_gpio_chip structure
+ * uses the above macro and depends on the banks being listed in order here.
+ */
+static struct s3c_gpio_chip exynos5_gpio_common_4bit[] = {
+	{
+		.base	= S5P_VA_GPIO1,
+		.eint_offset = 0x0,
+		.group	= 0,
+		.chip	= {
+			.base	= EXYNOS5_GPA0(0),
+			.ngpio	= EXYNOS5_GPIO_A0_NR,
+			.label	= "GPA0",
+		},
+	}, {
+		.base	= (S5P_VA_GPIO1 + 0x20),
+		.eint_offset = 0x4,
+		.group	= 1,
+		.chip	= {
+			.base	= EXYNOS5_GPA1(0),
+			.ngpio	= EXYNOS5_GPIO_A1_NR,
+			.label	= "GPA1",
+		},
+	}, {
+		.base	= (S5P_VA_GPIO1 + 0x40),
+		.eint_offset = 0x8,
+		.group	= 2,
+		.chip	= {
+			.base	= EXYNOS5_GPA2(0),
+			.ngpio	= EXYNOS5_GPIO_A2_NR,
+			.label	= "GPA2",
+		},
+	}, {
+		.base	= (S5P_VA_GPIO1 + 0x60),
+		.eint_offset = 0xC,
+		.group	= 3,
+		.chip	= {
+			.base	= EXYNOS5_GPB0(0),
+			.ngpio	= EXYNOS5_GPIO_B0_NR,
+			.label	= "GPB0",
+		},
+	}, {
+		.base	= (S5P_VA_GPIO1 + 0x80),
+		.eint_offset = 0x10,
+		.group	= 4,
+		.chip	= {
+			.base	= EXYNOS5_GPB1(0),
+			.ngpio	= EXYNOS5_GPIO_B1_NR,
+			.label	= "GPB1",
+		},
+	}, {
+		.base	= (S5P_VA_GPIO1 + 0xA0),
+		.eint_offset = 0x14,
+		.group	= 5,
+		.chip	= {
+			.base	= EXYNOS5_GPB2(0),
+			.ngpio	= EXYNOS5_GPIO_B2_NR,
+			.label	= "GPB2",
+		},
+	}, {
+		.base	= (S5P_VA_GPIO1 + 0xC0),
+		.eint_offset = 0x18,
+		.group	= 6,
+		.chip	= {
+			.base	= EXYNOS5_GPB3(0),
+			.ngpio	= EXYNOS5_GPIO_B3_NR,
+			.label	= "GPB3",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0xE0),
+		.eint_offset = 0x1C,
+		.group	= 7,
+		.chip	= {
+			.base	= EXYNOS5_GPC0(0),
+			.ngpio	= EXYNOS5_GPIO_C0_NR,
+			.label	= "GPC0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x100),
+		.eint_offset = 0x20,
+		.group	= 8,
+		.chip	= {
+			.base	= EXYNOS5_GPC1(0),
+			.ngpio	= EXYNOS5_GPIO_C1_NR,
+			.label	= "GPC1",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x120),
+		.eint_offset = 0x24,
+		.group	= 9,
+		.chip	= {
+			.base	= EXYNOS5_GPC2(0),
+			.ngpio	= EXYNOS5_GPIO_C2_NR,
+			.label	= "GPC2",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x140),
+		.eint_offset = 0x28,
+		.group	= 10,
+		.chip	= {
+			.base	= EXYNOS5_GPC3(0),
+			.ngpio	= EXYNOS5_GPIO_C3_NR,
+			.label	= "GPC3",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x2E0),
+		.eint_offset = 0x34,
+		.group	= 22,
+		.chip	= {
+			.base	= EXYNOS5_GPC4(0),
+			.ngpio	= EXYNOS5_GPIO_C4_NR,
+			.label	= "GPC4",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x160),
+		.eint_offset = 0x2C,
+		.group	= 11,
+		.chip	= {
+			.base	= EXYNOS5_GPD0(0),
+			.ngpio	= EXYNOS5_GPIO_D0_NR,
+			.label	= "GPD0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x180),
+		.eint_offset = 0x30,
+		.group	= 12,
+		.chip	= {
+			.base	= EXYNOS5_GPD1(0),
+			.ngpio	= EXYNOS5_GPIO_D1_NR,
+			.label	= "GPD1",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x1A0),
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= EXYNOS5_GPY0(0),
+			.ngpio	= EXYNOS5_GPIO_Y0_NR,
+			.label	= "GPY0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x1C0),
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= EXYNOS5_GPY1(0),
+			.ngpio	= EXYNOS5_GPIO_Y1_NR,
+			.label	= "GPY1",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x1E0),
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= EXYNOS5_GPY2(0),
+			.ngpio	= EXYNOS5_GPIO_Y2_NR,
+			.label	= "GPY2",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x200),
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= EXYNOS5_GPY3(0),
+			.ngpio	= EXYNOS5_GPIO_Y3_NR,
+			.label	= "GPY3",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x220),
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= EXYNOS5_GPY4(0),
+			.ngpio	= EXYNOS5_GPIO_Y4_NR,
+			.label	= "GPY4",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x240),
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= EXYNOS5_GPY5(0),
+			.ngpio	= EXYNOS5_GPIO_Y5_NR,
+			.label	= "GPY5",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO1 + 0x260),
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= EXYNOS5_GPY6(0),
+			.ngpio	= EXYNOS5_GPIO_Y6_NR,
+			.label	= "GPY6",
+		},
+	}, {
+		.base	= (S5P_VA_GPIO1 + 0xC00),
+		.config	= &gpio_cfg_noint,
+		.irq_base = IRQ_EINT(0),
+		.chip	= {
+			.base	= EXYNOS5_GPX0(0),
+			.ngpio	= EXYNOS5_GPIO_X0_NR,
+			.label	= "GPX0",
+			.to_irq	= samsung_gpiolib_to_irq,
+		},
+	}, {
+		.base	= (S5P_VA_GPIO1 + 0xC20),
+		.config	= &gpio_cfg_noint,
+		.irq_base = IRQ_EINT(8),
+		.chip	= {
+			.base	= EXYNOS5_GPX1(0),
+			.ngpio	= EXYNOS5_GPIO_X1_NR,
+			.label	= "GPX1",
+			.to_irq	= samsung_gpiolib_to_irq,
+		},
+	}, {
+		.base	= (S5P_VA_GPIO1 + 0xC40),
+		.config	= &gpio_cfg_noint,
+		.irq_base = IRQ_EINT(16),
+		.chip	= {
+			.base	= EXYNOS5_GPX2(0),
+			.ngpio	= EXYNOS5_GPIO_X2_NR,
+			.label	= "GPX2",
+			.to_irq	= samsung_gpiolib_to_irq,
+		},
+	}, {
+		.base	= (S5P_VA_GPIO1 + 0xC60),
+		.config	= &gpio_cfg_noint,
+		.irq_base = IRQ_EINT(24),
+		.chip	= {
+			.base	= EXYNOS5_GPX3(0),
+			.ngpio	= EXYNOS5_GPIO_X3_NR,
+			.label	= "GPX3",
+			.to_irq	= samsung_gpiolib_to_irq,
+		},
+	}, {
+		.base   = S5P_VA_GPIO2,
+		.eint_offset = 0x0,
+		.group	= 13,
+		.chip	= {
+			.base	= EXYNOS5_GPE0(0),
+			.ngpio	= EXYNOS5_GPIO_E0_NR,
+			.label	= "GPE0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x20),
+		.eint_offset = 0x4,
+		.group	= 14,
+		.chip	= {
+			.base	= EXYNOS5_GPE1(0),
+			.ngpio	= EXYNOS5_GPIO_E1_NR,
+			.label	= "GPE1",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x40),
+		.eint_offset = 0x8,
+		.group	= 15,
+		.chip	= {
+			.base	= EXYNOS5_GPF0(0),
+			.ngpio	= EXYNOS5_GPIO_F0_NR,
+			.label	= "GPF0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x60),
+		.eint_offset = 0xC,
+		.group	= 16,
+		.chip	= {
+			.base	= EXYNOS5_GPF1(0),
+			.ngpio	= EXYNOS5_GPIO_F1_NR,
+			.label	= "GPF1",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x80),
+		.eint_offset = 0x10,
+		.group	= 17,
+		.chip	= {
+			.base	= EXYNOS5_GPG0(0),
+			.ngpio	= EXYNOS5_GPIO_G0_NR,
+			.label	= "GPG0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0xA0),
+		.eint_offset = 0x14,
+		.group	= 18,
+		.chip	= {
+			.base	= EXYNOS5_GPG1(0),
+			.ngpio	= EXYNOS5_GPIO_G1_NR,
+			.label	= "GPG1",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0xC0),
+		.eint_offset = 0x18,
+		.group	= 19,
+		.chip	= {
+			.base	= EXYNOS5_GPG2(0),
+			.ngpio	= EXYNOS5_GPIO_G2_NR,
+			.label	= "GPG2",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0xE0),
+		.eint_offset = 0x1C,
+		.group	= 20,
+		.chip	= {
+			.base	= EXYNOS5_GPH0(0),
+			.ngpio	= EXYNOS5_GPIO_H0_NR,
+			.label	= "GPH0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x100),
+		.eint_offset = 0x20,
+		.group	= 21,
+		.chip	= {
+			.base	= EXYNOS5_GPH1(0),
+			.ngpio	= EXYNOS5_GPIO_H1_NR,
+			.label	= "GPH1",
+		},
+	}, {
+		.base   = S5P_VA_GPIO3,
+		.chip	= {
+			.base	= EXYNOS5_GPV0(0),
+			.ngpio	= EXYNOS5_GPIO_V0_NR,
+			.label	= "GPV0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO3 + 0x20),
+		.chip	= {
+			.base	= EXYNOS5_GPV1(0),
+			.ngpio	= EXYNOS5_GPIO_V1_NR,
+			.label	= "GPV1",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO3 + 0x60),
+		.chip	= {
+			.base	= EXYNOS5_GPV2(0),
+			.ngpio	= EXYNOS5_GPIO_V2_NR,
+			.label	= "GPV2",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO3 + 0x80),
+		.chip	= {
+			.base	= EXYNOS5_GPV3(0),
+			.ngpio	= EXYNOS5_GPIO_V3_NR,
+			.label	= "GPV3",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO3 + 0xC0),
+		.chip	= {
+			.base	= EXYNOS5_GPV4(0),
+			.ngpio	= EXYNOS5_GPIO_V4_NR,
+			.label	= "GPV4",
+		},
+	},
+};
+
+static struct s3c_gpio_chip exynos5_gpio_no_pm_4bit[] = {
+{
+		.base   = S5P_VA_GPIO4,
+		.chip	= {
+			.base	= EXYNOS5_GPZ(0),
+			.ngpio	= EXYNOS5_GPIO_Z_NR,
+			.label	= "GPZ",
+		},
+	},
+};
+
+static struct s3c_gpio_chip exynos5210_gpio_4bit[] = {
+	{
+		.base   = (S5P_VA_GPIO2 + 0x120),
+		.eint_offset = 0x24,
+		.group	= 22,
+		.chip	= {
+			.base	= EXYNOS5210_GPJ0(0),
+			.ngpio	= EXYNOS5210_GPIO_J0_NR,
+			.label	= "GPJ0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x140),
+		.eint_offset = 0x28,
+		.group	= 23,
+		.chip	= {
+			.base	= EXYNOS5210_GPJ1(0),
+			.ngpio	= EXYNOS5210_GPIO_J1_NR,
+			.label	= "GPJ1",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x160),
+		.eint_offset = 0x2C,
+		.group	= 24,
+		.chip	= {
+			.base	= EXYNOS5210_GPJ2(0),
+			.ngpio	= EXYNOS5210_GPIO_J2_NR,
+			.label	= "GPJ2",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x180),
+		.eint_offset = 0x30,
+		.group	= 25,
+		.chip	= {
+			.base	= EXYNOS5210_GPJ3(0),
+			.ngpio	= EXYNOS5210_GPIO_J3_NR,
+			.label	= "GPJ3",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x1A0),
+		.eint_offset = 0x34,
+		.group	= 26,
+		.chip	= {
+			.base	= EXYNOS5210_GPJ4(0),
+			.ngpio	= EXYNOS5210_GPIO_J4_NR,
+			.label	= "GPJ4",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x1C0),
+		.eint_offset = 0x38,
+		.group	= 27,
+		.chip	= {
+			.base	= EXYNOS5210_GPK0(0),
+			.ngpio	= EXYNOS5210_GPIO_K0_NR,
+			.label	= "GPK0",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x1E0),
+		.eint_offset = 0x3C,
+		.group	= 28,
+		.chip	= {
+			.base	= EXYNOS5210_GPK1(0),
+			.ngpio	= EXYNOS5210_GPIO_K1_NR,
+			.label	= "GPK1",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x200),
+		.eint_offset = 0x40,
+		.group	= 29,
+		.chip	= {
+			.base	= EXYNOS5210_GPK2(0),
+			.ngpio	= EXYNOS5210_GPIO_K2_NR,
+			.label	= "GPK2",
+		},
+	}, {
+		.base   = (S5P_VA_GPIO2 + 0x220),
+		.eint_offset = 0x44,
+		.group	= 30,
+		.chip	= {
+			.base	= EXYNOS5210_GPK3(0),
+			.ngpio	= EXYNOS5210_GPIO_K3_NR,
+			.label	= "GPK3",
+		},
+	},
+};
+
+/* EXYNOS5 machine dependent GPIO help function */
+int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config)
+{
+	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+	void __iomem *reg;
+	unsigned long flags;
+	int offset;
+	u32 con;
+	int shift;
+
+	if (!chip)
+		return -EINVAL;
+
+	if ((pin >= EXYNOS5_GPX0(0)) && (pin <= EXYNOS5_GPX3(7)))
+		return -EINVAL;
+
+	if (config > S3C_GPIO_SLP_PREV)
+		return -EINVAL;
+
+	reg = chip->base + 0x10;
+
+	offset = pin - chip->chip.base;
+	shift = offset * 2;
+
+	local_irq_save(flags);
+
+	con = __raw_readl(reg);
+	con &= ~(3 << shift);
+	con |= config << shift;
+	__raw_writel(con, reg);
+
+	local_irq_restore(flags);
+	return 0;
+}
+
+s3c_gpio_pull_t s3c_gpio_get_slp_cfgpin(unsigned int pin)
+{
+	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+	void __iomem *reg;
+	unsigned long flags;
+	int offset;
+	u32 con;
+	int shift;
+
+	if (!chip)
+		return -EINVAL;
+
+	if ((pin >= EXYNOS5_GPX0(0)) && (pin <= EXYNOS5_GPX3(7)))
+		return -EINVAL;
+
+	reg = chip->base + 0x10;
+
+	offset = pin - chip->chip.base;
+	shift = offset * 2;
+
+	local_irq_save(flags);
+
+	con = __raw_readl(reg);
+	con >>= shift;
+	con &= 0x3;
+
+	local_irq_restore(flags);
+
+	return (__force s3c_gpio_pull_t)con;
+}
+
+int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config)
+{
+	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+	void __iomem *reg;
+	unsigned long flags;
+	int offset;
+	u32 con;
+	int shift;
+
+	if (!chip)
+		return -EINVAL;
+
+	if ((pin >= EXYNOS5_GPX0(0)) && (pin <= EXYNOS5_GPX3(7)))
+		return -EINVAL;
+
+	if (config > S3C_GPIO_PULL_UP)
+		return -EINVAL;
+
+	reg = chip->base + 0x14;
+
+	offset = pin - chip->chip.base;
+	shift = offset * 2;
+
+	local_irq_save(flags);
+
+	con = __raw_readl(reg);
+	con &= ~(3 << shift);
+	con |= config << shift;
+	__raw_writel(con, reg);
+
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+static __init int exynos5_gpiolib_init(void)
+{
+	struct s3c_gpio_chip *chip;
+	int i;
+	int nr_chips;
+
+	/* GPIO common part */
+	chip = exynos5_gpio_common_4bit;
+	nr_chips = ARRAY_SIZE(exynos5_gpio_common_4bit);
+
+	for (i = 0; i < nr_chips; i++, chip++) {
+		if (chip->config == NULL)
+			chip->config = &gpio_cfg;
+		if (chip->base == NULL)
+			pr_err("No allocation of base address for [common gpio]");
+	}
+
+	samsung_gpiolib_add_4bit_chips(exynos5_gpio_common_4bit, nr_chips);
+
+	/* GPIO no PM part */
+	chip = exynos5_gpio_no_pm_4bit;
+	nr_chips = ARRAY_SIZE(exynos5_gpio_no_pm_4bit);
+
+	for (i = 0; i < nr_chips; i++, chip++) {
+		if (chip->config == NULL)
+			chip->config = &gpio_cfg;
+		if (chip->base == NULL)
+			pr_err("No allocation of base address for [common gpio]");
+	}
+
+	samsung_gpiolib_add_4bit_chips_no_pm(exynos5_gpio_no_pm_4bit, nr_chips);
+
+#if defined(CONFIG_CPU_EXYNOS5250) && defined(CONFIG_S5P_GPIO_INT)
+	s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
+	s5p_register_gpioint_bank(IRQ_GPIO_XB,
+				  IRQ_GPIO1_NR_GROUPS,
+				  IRQ_GPIO2_NR_GROUPS);
+	s5p_register_gpioint_bank(IRQ_GPIO_C2C,
+				  IRQ_GPIO1_NR_GROUPS + IRQ_GPIO2_NR_GROUPS,
+				  IRQ_GPIO3_NR_GROUPS);
+	s5p_register_gpioint_bank(IRQ_GPIO,
+				  IRQ_GPIO1_NR_GROUPS + IRQ_GPIO2_NR_GROUPS +
+				  IRQ_GPIO3_NR_GROUPS,
+				  IRQ_GPIO4_NR_GROUPS);
+#endif
+
+	return 0;
+}
+core_initcall(exynos5_gpiolib_init);
diff --git a/drivers/gpio/gpio-plat-samsung.c b/drivers/gpio/gpio-plat-samsung.c
index ea37c04..29a6e4f 100644
--- a/drivers/gpio/gpio-plat-samsung.c
+++ b/drivers/gpio/gpio-plat-samsung.c
@@ -49,12 +49,17 @@ static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
 {
 	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
 	void __iomem *base = ourchip->base;
+	unsigned long flags;
 	unsigned long con;
 
+	s3c_gpio_lock(ourchip, flags);
+
 	con = __raw_readl(base + GPIOCON_OFF);
 	con &= ~(0xf << con_4bit_shift(offset));
 	__raw_writel(con, base + GPIOCON_OFF);
 
+	s3c_gpio_unlock(ourchip, flags);
+
 	gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
 
 	return 0;
@@ -65,9 +70,12 @@ static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
 {
 	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
 	void __iomem *base = ourchip->base;
+	unsigned long flags;
 	unsigned long con;
 	unsigned long dat;
 
+	s3c_gpio_lock(ourchip, flags);
+
 	con = __raw_readl(base + GPIOCON_OFF);
 	con &= ~(0xf << con_4bit_shift(offset));
 	con |= 0x1 << con_4bit_shift(offset);
@@ -83,6 +91,8 @@ static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
 	__raw_writel(con, base + GPIOCON_OFF);
 	__raw_writel(dat, base + GPIODAT_OFF);
 
+	s3c_gpio_unlock(ourchip, flags);
+
 	gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
 
 	return 0;
@@ -115,6 +125,7 @@ static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
 	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
 	void __iomem *base = ourchip->base;
 	void __iomem *regcon = base;
+	unsigned long flags;
 	unsigned long con;
 
 	if (offset > 7)
@@ -122,10 +133,14 @@ static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
 	else
 		regcon -= 4;
 
+	s3c_gpio_lock(ourchip, flags);
+
 	con = __raw_readl(regcon);
 	con &= ~(0xf << con_4bit_shift(offset));
 	__raw_writel(con, regcon);
 
+	s3c_gpio_unlock(ourchip, flags);
+
 	gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
 
 	return 0;
@@ -137,6 +152,7 @@ static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
 	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
 	void __iomem *base = ourchip->base;
 	void __iomem *regcon = base;
+	unsigned long flags;
 	unsigned long con;
 	unsigned long dat;
 	unsigned con_offset = offset;
@@ -146,6 +162,8 @@ static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
 	else
 		regcon -= 4;
 
+	s3c_gpio_lock(ourchip, flags);
+
 	con = __raw_readl(regcon);
 	con &= ~(0xf << con_4bit_shift(con_offset));
 	con |= 0x1 << con_4bit_shift(con_offset);
@@ -161,6 +179,8 @@ static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
 	__raw_writel(con, regcon);
 	__raw_writel(dat, base + GPIODAT_OFF);
 
+	s3c_gpio_unlock(ourchip, flags);
+
 	gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
 
 	return 0;
@@ -170,14 +190,20 @@ void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
 {
 	chip->chip.direction_input = samsung_gpiolib_4bit_input;
 	chip->chip.direction_output = samsung_gpiolib_4bit_output;
-	chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
+	chip->pm = chip->pm ?: __gpio_pm(&s3c_gpio_pm_4bit);
 }
 
 void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
 {
 	chip->chip.direction_input = samsung_gpiolib_4bit2_input;
 	chip->chip.direction_output = samsung_gpiolib_4bit2_output;
-	chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
+	chip->pm = chip->pm ?: __gpio_pm(&s3c_gpio_pm_4bit);
+}
+
+void __init samsung_gpiolib_add_4bit_no_pm(struct s3c_gpio_chip *chip)
+{
+	chip->chip.direction_input = samsung_gpiolib_4bit_input;
+	chip->chip.direction_output = samsung_gpiolib_4bit_output;
 }
 
 void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
@@ -189,6 +215,15 @@ void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
 	}
 }
 
+void __init samsung_gpiolib_add_4bit_chips_no_pm(struct s3c_gpio_chip *chip,
+					   int nr_chips)
+{
+	for (; nr_chips > 0; nr_chips--, chip++) {
+		samsung_gpiolib_add_4bit_no_pm(chip);
+		s3c_gpiolib_add(chip);
+	}
+}
+
 void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
 					    int nr_chips)
 {