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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2009-10-08 10:16:48 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-11-05 14:47:06 -0800 |
| commit | 97f5ab6651a996ecefed73e41684422f3b29d9a8 (patch) | |
| tree | 3a78cd25b38419df94fa5b2f91793f47b5d99b68 /drivers/gpu/drm/i915/i915_suspend.c | |
| parent | d8a2d0e00c0d5a0d55e14b884bff034205015e51 (diff) | |
| download | kernel_samsung_smdk4412-97f5ab6651a996ecefed73e41684422f3b29d9a8.zip kernel_samsung_smdk4412-97f5ab6651a996ecefed73e41684422f3b29d9a8.tar.gz kernel_samsung_smdk4412-97f5ab6651a996ecefed73e41684422f3b29d9a8.tar.bz2 | |
drm/i915: add render standby support
Render standy allows the GPU to power down the render unit when idle.
In order for this to work, it needs a page of graphics memory to save
state. This patch allocates that page and enables the feature on
supported chipsets.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_suspend.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_suspend.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 992d561..cd10d9b 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -699,8 +699,10 @@ int i915_save_state(struct drm_device *dev) pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); /* Render Standby */ - if (IS_I965G(dev) && IS_MOBILE(dev)) + if (I915_HAS_RC6(dev)) { dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY); + dev_priv->savePWRCTXA = I915_READ(PWRCTXA); + } /* Hardware status page */ dev_priv->saveHWS = I915_READ(HWS_PGA); @@ -762,8 +764,10 @@ int i915_restore_state(struct drm_device *dev) pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); /* Render Standby */ - if (IS_I965G(dev) && IS_MOBILE(dev)) + if (I915_HAS_RC6(dev)) { I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY); + I915_WRITE(PWRCTXA, dev_priv->savePWRCTXA); + } /* Hardware status page */ I915_WRITE(HWS_PGA, dev_priv->saveHWS); |