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| author | Dave Airlie <airlied@redhat.com> | 2011-04-11 15:26:01 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2011-04-11 15:26:01 +1000 |
| commit | d85023a3cdb48ae127e431ec216c277ed7a3cb0f (patch) | |
| tree | e957a70646c1770ffe78ae793ca50a91254aeee0 /drivers/gpu/drm/nouveau/nouveau_state.c | |
| parent | d4864d604a8d29a0d6a13a8d882be6e21c498c22 (diff) | |
| parent | a719726f4ceaf14842c80fd7e58dec40cb7022a2 (diff) | |
| download | kernel_samsung_smdk4412-d85023a3cdb48ae127e431ec216c277ed7a3cb0f.zip kernel_samsung_smdk4412-d85023a3cdb48ae127e431ec216c277ed7a3cb0f.tar.gz kernel_samsung_smdk4412-d85023a3cdb48ae127e431ec216c277ed7a3cb0f.tar.bz2 | |
Merge remote branch 'nouveau/drm-nouveau-fixes' of /ssd/git/drm-nouveau-next into drm-fixes
* 'nouveau/drm-nouveau-fixes' of /ssd/git/drm-nouveau-next:
drm/nvc0: improve vm flush function
drm/nv50-nvc0: remove some code that doesn't belong here
drm/nv50: use "nv86" tlb flush method on everything except 0x50/0xac
drm/nouveau: quirk for XFX GT-240X-YA
drm/nv50-nvc0: work around an evo channel hang that some people see
drm/nouveau: implement init table opcode 0x5c
drm/nouveau: fix oops on unload with disabled LVDS panel
nv30: Fix parsing of perf table
drm/nouveau: correct memtiming table parsing for nv4x
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_state.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_state.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index 5bb2859..6e2b1a6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c @@ -376,15 +376,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->graph.destroy_context = nv50_graph_destroy_context; engine->graph.load_context = nv50_graph_load_context; engine->graph.unload_context = nv50_graph_unload_context; - if (dev_priv->chipset != 0x86) + if (dev_priv->chipset == 0x50 || + dev_priv->chipset == 0xac) engine->graph.tlb_flush = nv50_graph_tlb_flush; - else { - /* from what i can see nvidia do this on every - * pre-NVA3 board except NVAC, but, we've only - * ever seen problems on NV86 - */ - engine->graph.tlb_flush = nv86_graph_tlb_flush; - } + else + engine->graph.tlb_flush = nv84_graph_tlb_flush; engine->fifo.channels = 128; engine->fifo.init = nv50_fifo_init; engine->fifo.takedown = nv50_fifo_takedown; |