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| author | Michel Dänzer <michel.daenzer@amd.com> | 2011-09-13 11:27:35 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-10-03 11:40:29 -0700 |
| commit | a4f5172f4f84d22889d97c527cd8fe7430f075ae (patch) | |
| tree | e4408c8dd0f03cf19dd2096875d1331c9e7b0a47 /drivers/gpu/drm/radeon/evergreen.c | |
| parent | 90199f79ba3111426070b3e04d774c25024ea1a6 (diff) | |
| download | kernel_samsung_smdk4412-a4f5172f4f84d22889d97c527cd8fe7430f075ae.zip kernel_samsung_smdk4412-a4f5172f4f84d22889d97c527cd8fe7430f075ae.tar.gz kernel_samsung_smdk4412-a4f5172f4f84d22889d97c527cd8fe7430f075ae.tar.bz2 | |
drm/radeon: Don't read from CP ring write pointer registers.
commit 87463ff83bcda210d8f0ae440bd64d1548f852e7 upstream.
Apparently this doesn't always work reliably, e.g. at resume time.
Just initialize to 0, so the ring is considered empty.
Tested with hibernation on Sumo and Cayman cards.
Should fix https://bugs.launchpad.net/ubuntu/+source/linux/+bug/820746/ .
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 2b2f06c..ac7f700 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -1404,7 +1404,8 @@ int evergreen_cp_resume(struct radeon_device *rdev) /* Initialize the ring buffer's read and write pointers */ WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); WREG32(CP_RB_RPTR_WR, 0); - WREG32(CP_RB_WPTR, 0); + rdev->cp.wptr = 0; + WREG32(CP_RB_WPTR, rdev->cp.wptr); /* set the wb address wether it's enabled or not */ WREG32(CP_RB_RPTR_ADDR, @@ -1429,7 +1430,6 @@ int evergreen_cp_resume(struct radeon_device *rdev) WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); rdev->cp.rptr = RREG32(CP_RB_RPTR); - rdev->cp.wptr = RREG32(CP_RB_WPTR); evergreen_cp_start(rdev); rdev->cp.ready = true; |