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| author | Alex Deucher <alexdeucher@gmail.com> | 2011-04-02 09:15:50 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2011-04-04 10:08:35 +1000 |
| commit | fb9674bd2cd3c18f6c756ee123967e43be501263 (patch) | |
| tree | 6f72538672862de7b8bee00616c4449e6b0ccbcb /drivers/gpu/drm/radeon/evergreen.c | |
| parent | beb47274116b36e17cf52869a2004e7d12a4ef1d (diff) | |
| download | kernel_samsung_smdk4412-fb9674bd2cd3c18f6c756ee123967e43be501263.zip kernel_samsung_smdk4412-fb9674bd2cd3c18f6c756ee123967e43be501263.tar.gz kernel_samsung_smdk4412-fb9674bd2cd3c18f6c756ee123967e43be501263.tar.bz2 | |
drm/radeon/kms: pageflipping cleanup for avivo+
Avoid touching the flip setup regs while
acceleration is running. Set them at modeset
rather than during pageflip. Touching these
regs while acceleration is active caused hangs
on pre-avivo chips. These chips do not seem
to be affected, but better safe than sorry,
plus it avoids repeatedly reprogramming the
regs every flip.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 941080a..0b0cc74 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -43,17 +43,6 @@ static void evergreen_pcie_gen2_enable(struct radeon_device *rdev); void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc) { - struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc]; - u32 tmp; - - /* make sure flip is at vb rather than hb */ - tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); - tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; - WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); - - /* set pageflip to happen anywhere in vblank interval */ - WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); - /* enable the pflip int */ radeon_irq_kms_pflip_irq_get(rdev, crtc); } |