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authorDave Airlie <airlied@redhat.com>2009-12-01 16:04:56 +1000
committerDave Airlie <airlied@redhat.com>2009-12-02 14:00:13 +1000
commit1614f8b17b8cc3ad143541d41569623d30dbc9ec (patch)
tree7b0284e942cb68ea47cdc832bbd43864b23dcd2d /drivers/gpu/drm/radeon/r520.c
parentd8f60cfc93452d0554f6a701aa8e3236cbee4636 (diff)
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drm/radeon/kms: add irq mitigation code for sw interrupt.
We really don't need to process every irq that comes in, we only really want to do SW irq processing when we are actually waiting for a fence to pass. I'm not 100% sure this is race free esp on non-MSI systems so it needs some testing. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r520.c')
-rw-r--r--drivers/gpu/drm/radeon/r520.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 26c3779..92fbc98 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -185,7 +185,6 @@ static int r520_startup(struct radeon_device *rdev)
return r;
}
/* Enable IRQ */
- rdev->irq.sw_int = true;
rs600_irq_set(rdev);
/* 1M ring buffer */
r = r100_cp_init(rdev, 1024 * 1024);