diff options
| author | Manjunatha GK <manjugk@ti.com> | 2009-12-11 11:09:08 +0530 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2009-12-24 01:30:54 +0000 |
| commit | 57eb81b14e35a14df64ac3597bc90c26ce04a9b4 (patch) | |
| tree | dcc3893c4a65872428b38f773c3de0ad2d215474 /drivers/i2c/busses/i2c-omap.c | |
| parent | 07ac31f6f4cd558e53f6705dbe3033a7f0237eb8 (diff) | |
| download | kernel_samsung_smdk4412-57eb81b14e35a14df64ac3597bc90c26ce04a9b4.zip kernel_samsung_smdk4412-57eb81b14e35a14df64ac3597bc90c26ce04a9b4.tar.gz kernel_samsung_smdk4412-57eb81b14e35a14df64ac3597bc90c26ce04a9b4.tar.bz2 | |
i2c-omap: OMAP3: Fix I2C lockup during timeout/error cases
Current OMAP3 I2C driver code does not follow the correct sequence for soft
reset. Due to this, lock up issues are reported during timeout/error cases.
This patch fixes above issue by disabling I2C controller as per OMAP3430 TRM
for soft reset. As per TRM, I2C controller needs to be disabled as a first
step during soft reset.
Here is correct soft reset sequence:
a. Ensure that the module is disabled
(clear the I2Ci.I2C_CON[15] I2C_EN bit to 0).
b. Set the I2Ci.I2C_SYSC[1] SRST bit to 1.
c. Enable the module by setting I2Ci.I2C_CON[15] I2C_EN bit to 1.
d. Check the I2Ci.I2C_SYSS[0] RDONE bit until it is set to 1 to
indicate the software reset is complete.
Tested on Zoom2, Zoom3, 3430SDP and 3630SDP
Signed-off-by: Manjunatha GK <manjugk@ti.com>
Signed-off-by: George, Harith<harith@ti.com>
Acked-by: Varadarajan, Charu Latha<charu@ti.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'drivers/i2c/busses/i2c-omap.c')
| -rw-r--r-- | drivers/i2c/busses/i2c-omap.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index a64a192..0037e31 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -286,6 +286,11 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) unsigned long internal_clk = 0; if (dev->rev >= OMAP_I2C_REV_2) { + /* Disable I2C controller before soft reset */ + omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, + omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & + ~(OMAP_I2C_CON_EN)); + omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); /* For some reason we need to set the EN bit before the * reset done bit gets set. */ |