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| author | codeworkx <daniel.hillenbrand@codeworkx.de> | 2012-06-02 13:09:29 +0200 |
|---|---|---|
| committer | codeworkx <daniel.hillenbrand@codeworkx.de> | 2012-06-02 13:09:29 +0200 |
| commit | c6da2cfeb05178a11c6d062a06f8078150ee492f (patch) | |
| tree | f3b4021d252c52d6463a9b3c1bb7245e399b009c /drivers/media/video/s5p-fimc/regs-fimc.h | |
| parent | c6d7c4dbff353eac7919342ae6b3299a378160a6 (diff) | |
| download | kernel_samsung_smdk4412-c6da2cfeb05178a11c6d062a06f8078150ee492f.zip kernel_samsung_smdk4412-c6da2cfeb05178a11c6d062a06f8078150ee492f.tar.gz kernel_samsung_smdk4412-c6da2cfeb05178a11c6d062a06f8078150ee492f.tar.bz2 | |
samsung update 1
Diffstat (limited to 'drivers/media/video/s5p-fimc/regs-fimc.h')
| -rw-r--r-- | drivers/media/video/s5p-fimc/regs-fimc.h | 36 |
1 files changed, 32 insertions, 4 deletions
diff --git a/drivers/media/video/s5p-fimc/regs-fimc.h b/drivers/media/video/s5p-fimc/regs-fimc.h index 0fea3e6..e069a90 100644 --- a/drivers/media/video/s5p-fimc/regs-fimc.h +++ b/drivers/media/video/s5p-fimc/regs-fimc.h @@ -52,8 +52,13 @@ #define S5P_CIGCTRL_HREF_MASK (1 << 21) #define S5P_CIGCTRL_IRQ_LEVEL (1 << 20) #define S5P_CIGCTRL_IRQ_CLR (1 << 19) +#define S5P_CIGCTRL_IRQ_END_DISABLE (1 << 18) +#define S5P_CIGCTRL_IRQ_START_ENABLE (1 << 17) #define S5P_CIGCTRL_IRQ_ENABLE (1 << 16) #define S5P_CIGCTRL_SHDW_DISABLE (1 << 12) +#define S5P_CIGCTRL_SELWRITEBACK_A (1 << 10) +#define S5P_CIGCTRL_SELWRITEBACK_B (0 << 10) +#define S5P_CIGCTRL_CAM_JPEG (1 << 8) #define S5P_CIGCTRL_SELCAM_MIPI_A (1 << 7) #define S5P_CIGCTRL_CAMIF_SELWB (1 << 6) /* 0 - ITU601; 1 - ITU709 */ @@ -105,9 +110,16 @@ #define S5P_CIOCTRL_YCBCR_3PLANE (0 << 3) #define S5P_CIOCTRL_YCBCR_2PLANE (1 << 3) #define S5P_CIOCTRL_YCBCR_PLANE_MASK (1 << 3) +#define S5P_CIOCTRL_ALPHA_OUT_MASK (0xff << 4) +#define S5P_CIOCTRL_RGB16FMT_MASK (3 << 16) +#define S5P_CIOCTRL_RGB565 (0 << 16) +#define S5P_CIOCTRL_ARGB1555 (1 << 16) +#define S5P_CIOCTRL_ARGB4444 (2 << 16) #define S5P_CIOCTRL_ORDER2P_SHIFT (24) #define S5P_CIOCTRL_ORDER2P_MASK (3 << 24) #define S5P_CIOCTRL_ORDER422_2P_LSB_CRCB (0 << 24) +#define S5P_CIOCTRL_ORDER422_2P_LSB_CBCR (1 << 24) +#define S5P_CIOCTRL_LASTENDEN (1 << 30) /* Pre-scaler control 1 */ #define S5P_CISCPRERATIO 0x50 @@ -158,6 +170,7 @@ #define S5P_CISTATUS_VSYNC (1 << 28) #define S5P_CISTATUS_FRAMECNT_MASK (3 << 26) #define S5P_CISTATUS_FRAMECNT_SHIFT 26 +#define S5P_CISTATUS_SCALER_START (1 << 26) #define S5P_CISTATUS_WINOFF_EN (1 << 25) #define S5P_CISTATUS_IMGCPT_EN (1 << 22) #define S5P_CISTATUS_IMGCPT_SCEN (1 << 21) @@ -216,6 +229,7 @@ #define S5P_MSCTRL 0xfc #define S5P_MSCTRL_IN_BURST_COUNT_MASK (0xF << 24) #define S5P_MSCTRL_2P_IN_ORDER_MASK (3 << 16) +#define S5P_MSCTRL_2P_IN_YCRCB (1 << 16) #define S5P_MSCTRL_2P_IN_ORDER_SHIFT 16 #define S5P_MSCTRL_C_INT_IN_3PLANE (0 << 15) #define S5P_MSCTRL_C_INT_IN_2PLANE (1 << 15) @@ -268,6 +282,10 @@ /* Real output DMA image size (extension register) */ #define S5P_CIEXTEN 0x188 +#define S5P_CIEXTEN_TRGHSIZE_EXT(x) ((((x) >> 13) & 0x1) << 26) +#define S5P_CIEXTEN_TRGVSIZE_EXT(x) ((((x) >> 13) & 0x1) << 24) +#define S5P_CIEXTEN_TRGHSIZE_EXT_MASK (1 << 26) +#define S5P_CIEXTEN_TRGVSIZE_EXT_MASK (1 << 24) #define S5P_CIEXTEN_MHRATIO_EXT(x) (((x) & 0x3f) << 10) #define S5P_CIEXTEN_MVRATIO_EXT(x) ((x) & 0x3f) #define S5P_CIEXTEN_MHRATIO_EXT_MASK (0x3f << 10) @@ -286,12 +304,22 @@ #define S5P_CSIIMGFMT_RAW8 0x2a #define S5P_CSIIMGFMT_RAW10 0x2b #define S5P_CSIIMGFMT_RAW12 0x2c -#define S5P_CSIIMGFMT_USER1 0x30 -#define S5P_CSIIMGFMT_USER2 0x31 -#define S5P_CSIIMGFMT_USER3 0x32 -#define S5P_CSIIMGFMT_USER4 0x33 +/* User defined formats. x = 0...16. */ +#define S5P_CSIIMGFMT_USER(x) (0x30 + x - 1) /* Output frame buffer sequence mask */ #define S5P_CIFCNTSEQ 0x1FC +/* SYSREG for writeback */ +#define SYSREG_CAMERA_BLK (S3C_VA_SYS + 0x0218) +#define SYSREG_ISP_BLK (S3C_VA_SYS + 0x020c) +#define FIMD0_WB_DEST_FIMC0 (0x0 << 14) +#define FIMD0_WB_DEST_FIMC1 (0x1 << 14) +#define FIMD0_WB_DEST_FIMC2 (0x2 << 14) +#define FIMD0_WB_DEST_FIMC3 (0x3 << 14) +#define FIMD1_WB_DEST_FIMC0 (0x0 << 10) +#define FIMD1_WB_DEST_FIMC1 (0x1 << 10) +#define FIMD1_WB_DEST_FIMC2 (0x2 << 10) +#define FIMD1_WB_DEST_FIMC3 (0x3 << 10) + #endif /* REGS_FIMC_H_ */ |