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| author | Thomas Gleixner <tglx@cruncher.tec.linutronix.de> | 2006-05-23 23:25:53 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@cruncher.tec.linutronix.de> | 2006-05-23 23:25:53 +0200 |
| commit | 7abd3ef9875eb2afcdcd4f450680298a2983a55e (patch) | |
| tree | 64c19d2e5ecca182938acfcb8a172efb7d907d85 /drivers/mtd/nand/sharpsl.c | |
| parent | 3821720d51b5f304d2c33021a82c8da70f6d6ac9 (diff) | |
| download | kernel_samsung_smdk4412-7abd3ef9875eb2afcdcd4f450680298a2983a55e.zip kernel_samsung_smdk4412-7abd3ef9875eb2afcdcd4f450680298a2983a55e.tar.gz kernel_samsung_smdk4412-7abd3ef9875eb2afcdcd4f450680298a2983a55e.tar.bz2 | |
[MTD] Refactor NAND hwcontrol to cmd_ctrl
The hwcontrol function enforced a step by step state machine
for any kind of hardware chip access. Let the hardware driver
know which control bits are set and inform it about a change
of the control lines. Let the hardware driver write out the
command and address bytes directly. This gives a peformance
advantage for address bus controlled chips and simplifies the
quirks in the hardware drivers.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/mtd/nand/sharpsl.c')
| -rw-r--r-- | drivers/mtd/nand/sharpsl.c | 41 |
1 files changed, 18 insertions, 23 deletions
diff --git a/drivers/mtd/nand/sharpsl.c b/drivers/mtd/nand/sharpsl.c index 5554d0b..45a1da7 100644 --- a/drivers/mtd/nand/sharpsl.c +++ b/drivers/mtd/nand/sharpsl.c @@ -77,31 +77,26 @@ static struct mtd_partition sharpsl_nand_default_partition_info[] = { /* * hardware specific access to control-lines + * ctrl: + * NAND_CNE: bit 0 -> bit 0 & 4 + * NAND_CLE: bit 1 -> bit 1 + * NAND_ALE: bit 2 -> bit 2 + * */ -static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd) +static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd, + unsigned int ctrl) { - switch (cmd) { - case NAND_CTL_SETCLE: - writeb(readb(FLASHCTL) | FLCLE, FLASHCTL); - break; - case NAND_CTL_CLRCLE: - writeb(readb(FLASHCTL) & ~FLCLE, FLASHCTL); - break; - - case NAND_CTL_SETALE: - writeb(readb(FLASHCTL) | FLALE, FLASHCTL); - break; - case NAND_CTL_CLRALE: - writeb(readb(FLASHCTL) & ~FLALE, FLASHCTL); - break; - - case NAND_CTL_SETNCE: - writeb(readb(FLASHCTL) & ~(FLCE0 | FLCE1), FLASHCTL); - break; - case NAND_CTL_CLRNCE: - writeb(readb(FLASHCTL) | (FLCE0 | FLCE1), FLASHCTL); - break; + struct nand_chip *chip = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + unsigned char bits = ctrl & 0x07; + + bits |= (ctrl & 0x01) << 4; + writeb((readb(FLASHCTL) & 0x17) | bits, FLASHCTL); } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, chip->IO_ADDR_W); } static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; @@ -196,7 +191,7 @@ static int __init sharpsl_nand_init(void) this->IO_ADDR_R = FLASHIO; this->IO_ADDR_W = FLASHIO; /* Set address of hardware control function */ - this->hwcontrol = sharpsl_nand_hwcontrol; + this->cmd_ctrl = sharpsl_nand_hwcontrol; this->dev_ready = sharpsl_nand_dev_ready; /* 15 us command delay time */ this->chip_delay = 15; |