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author | Bruce Allan <bruce.w.allan@intel.com> | 2008-11-21 17:02:41 -0800 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-11-21 17:02:41 -0800 |
commit | e243455d345ef62751723671bc2605a2f6032ceb (patch) | |
tree | 7246784e849ca0471a4bf2bc69a960d6194a6af9 /drivers/net/e1000e/defines.h | |
parent | a20e4cf9e6a37e40532593e00df153d01e317baf (diff) | |
download | kernel_samsung_smdk4412-e243455d345ef62751723671bc2605a2f6032ceb.zip kernel_samsung_smdk4412-e243455d345ef62751723671bc2605a2f6032ceb.tar.gz kernel_samsung_smdk4412-e243455d345ef62751723671bc2605a2f6032ceb.tar.bz2 |
e1000e: check return code from NVM accesses and fix bank detection
Check return code for all NVM accesses[1] and error out accordingly; log
a debug message for failed accesses.
For ICH8/9, the valid NVM bank detect function was not checking whether the
SEC1VAL (sector 1 valid) bit in the EECD register was itself valid (bits 8
and 9 also have to be set). If invalid, it would have defaulted to the
possibly invalid bank 0. Instead, try to use the valid bank detection
method used by ICH10 which has been cleaned up a bit.
[1] - reads and updates only; not writes because those are only writing to
the Shadow RAM, the update following the write is the only thing actually
writing the modified Shadow RAM contents to the NVM.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/e1000e/defines.h')
-rw-r--r-- | drivers/net/e1000e/defines.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index 34a68fc..e6caf29 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h @@ -572,6 +572,7 @@ #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ +#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */ #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ |