diff options
| author | Christian Lamparter <chunkeey@googlemail.com> | 2010-09-28 23:00:59 +0200 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2010-10-05 13:35:21 -0400 |
| commit | 5c895691944862e782c285a871f5d3466797b4ef (patch) | |
| tree | 7d49f76b23d23253b2c54a1794beb0676c66c615 /drivers/net/wireless/ath/carl9170/phy.h | |
| parent | 85416a4fa193754ef36e12b20bb02fe661cb7f17 (diff) | |
| download | kernel_samsung_smdk4412-5c895691944862e782c285a871f5d3466797b4ef.zip kernel_samsung_smdk4412-5c895691944862e782c285a871f5d3466797b4ef.tar.gz kernel_samsung_smdk4412-5c895691944862e782c285a871f5d3466797b4ef.tar.bz2 | |
carl9170: support firmware-based rx filter
The hardware rx-filter was essentially disabled, because
of a serve, yet unidentifiable problem with iwlagn.
Due to these circumstances the driver and mac80211 were
left with the job of filtering.
This is very unfortunate and has proven to be expensive
in terms of latency, memory and load.
Therefore the new 1.8.8.3 firmware introduces a flexible
filtering infrastructure which allows the driver to
offload some of the checks (FCS & PLCP crc check,
RA match, control frame filter, etc...) whenever possible.
Note:
This patch also includes all changes to the
shared headers files since the inclusion.
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/carl9170/phy.h')
| -rw-r--r-- | drivers/net/wireless/ath/carl9170/phy.h | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/drivers/net/wireless/ath/carl9170/phy.h b/drivers/net/wireless/ath/carl9170/phy.h index 53c18d3..02c34eb 100644 --- a/drivers/net/wireless/ath/carl9170/phy.h +++ b/drivers/net/wireless/ath/carl9170/phy.h @@ -423,8 +423,8 @@ #define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 #define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 -#define AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2a0c) #define AR9170_PHY_REG_GAIN_2GHZ (AR9170_PHY_REG_BASE + 0x0a0c) +#define AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2a0c) #define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00fc0000 #define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 #define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003c00 @@ -561,7 +561,4 @@ #define AR9170_PHY_CH2_EXT_MINCCA_PWR 0xff800000 #define AR9170_PHY_CH2_EXT_MINCCA_PWR_S 23 -#define REDUCE_CHAIN_0 0x00000050 -#define REDUCE_CHAIN_1 0x00000051 - #endif /* __CARL9170_SHARED_PHY_H */ |