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author | Tomas Winkler <tomas.winkler@intel.com> | 2008-03-04 18:09:29 -0800 |
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committer | John W. Linville <linville@tuxdriver.com> | 2008-03-07 16:03:00 -0500 |
commit | 750fe6396614e267aeec0e2ff636740e2688d4d9 (patch) | |
tree | 9002a6fa10175e94df7550c9073af32935018dad /drivers/net/wireless/iwlwifi/iwl-csr.h | |
parent | 6f83eaa170c05324fb33668eace007ea24c277d2 (diff) | |
download | kernel_samsung_smdk4412-750fe6396614e267aeec0e2ff636740e2688d4d9.zip kernel_samsung_smdk4412-750fe6396614e267aeec0e2ff636740e2688d4d9.tar.gz kernel_samsung_smdk4412-750fe6396614e267aeec0e2ff636740e2688d4d9.tar.bz2 |
iwlwifi: Move HBUS address to iwl-csr.h
HBUS is accessed through CSR registers
moved to iwl-csr.h
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-csr.h')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-csr.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h index 276ba28..7016e5b 100644 --- a/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/iwlwifi/iwl-csr.h @@ -214,4 +214,46 @@ #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) +/*=== HBUS (Host-side Bus) ===*/ +#define HBUS_BASE (0x400) +/* + * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM + * structures, error log, event log, verifying uCode load). + * First write to address register, then read from or write to data register + * to complete the job. Once the address register is set up, accesses to + * data registers auto-increment the address by one dword. + * Bit usage for address registers (read or write): + * 0-31: memory address within device + */ +#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) +#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) +#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) +#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) + +/* + * Registers for accessing device's internal peripheral registers + * (e.g. SCD, BSM, etc.). First write to address register, + * then read from or write to data register to complete the job. + * Bit usage for address registers (read or write): + * 0-15: register address (offset) within device + * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) + */ +#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) +#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) +#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) +#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) + +/* + * Per-Tx-queue write pointer (index, really!) (3945 and 4965). + * Indicates index to next TFD that driver will fill (1 past latest filled). + * Bit usage: + * 0-7: queue write index + * 11-8: queue selector + */ +#define HBUS_TARG_WRPTR (HBUS_BASE+0x060) +#define HBUS_TARG_MBX_C (HBUS_BASE+0x030) + +#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) + + |