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| author | Vladimir Zapolskiy <vz@mleia.com> | 2011-10-19 22:39:12 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-10-19 13:42:49 -0700 |
| commit | fcde2bf0b9a0581db9fe5382e0c90f526c011114 (patch) | |
| tree | 58569442130b97413eb27b98f35e6d374a3c4800 /drivers/staging/tidspbridge | |
| parent | 6b7200fe0a59d7bda59e9e028b235b25a137dff9 (diff) | |
| download | kernel_samsung_smdk4412-fcde2bf0b9a0581db9fe5382e0c90f526c011114.zip kernel_samsung_smdk4412-fcde2bf0b9a0581db9fe5382e0c90f526c011114.tar.gz kernel_samsung_smdk4412-fcde2bf0b9a0581db9fe5382e0c90f526c011114.tar.bz2 | |
staging: tidspbridge: MMU2 registers are limited to 32-bit data access
According to OMAP3 TRM access to MMU registers shall be strictly 32-bit
aligned.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Omar Ramirez Luna <omar.ramirez@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/tidspbridge')
| -rw-r--r-- | drivers/staging/tidspbridge/hw/hw_mmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.c b/drivers/staging/tidspbridge/hw/hw_mmu.c index c214df9..8a93d55 100644 --- a/drivers/staging/tidspbridge/hw/hw_mmu.c +++ b/drivers/staging/tidspbridge/hw/hw_mmu.c @@ -558,5 +558,5 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address, void hw_mmu_tlb_flush_all(const void __iomem *base) { - __raw_writeb(1, base + MMU_GFLUSH); + __raw_writel(1, base + MMU_GFLUSH); } |