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| author | Anatolij Gustschin <agust@denx.de> | 2011-04-18 22:01:58 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-05-02 16:59:37 -0700 |
| commit | 2ea6698d7b9266da53044dddc5f6743adf097fb5 (patch) | |
| tree | 73dc8d286faf7c6cc25a18843825d796c0138f5b /drivers/usb/gadget/fsl_usb2_udc.h | |
| parent | 09ba0def9aefc16c1c8a6d166f024c9d704f0ab0 (diff) | |
| download | kernel_samsung_smdk4412-2ea6698d7b9266da53044dddc5f6743adf097fb5.zip kernel_samsung_smdk4412-2ea6698d7b9266da53044dddc5f6743adf097fb5.tar.gz kernel_samsung_smdk4412-2ea6698d7b9266da53044dddc5f6743adf097fb5.tar.bz2 | |
USB: fsl_udc_core: support device mode of MPC5121E DR USB Controller
Extend the FSL UDC driver to support MPC5121E DR USB Controller
operation in device mode. Add MPC5121E specific init/uninit
at probe and remove and isolate system interface register accesses
when running on MPC5121E SoC, as these registers are not available
on this platform. This patch relies on previous patch for supporting
big endian registers and descriptors access in the FSL UDC driver.
Additionally support endpoint FIFO status operation by providing
appropriate callback in endpoint ops structure.
Also flush cache for the req buffer used for GetStatus reply.
Without this, the correct reply to an endpoint GetStatus
is written to 'req', but doesn't make it out to the USB bus
since the buffer hasn't been flushed. This would cause the
USBCV Halt Endpoint test to fail (according to changelog in
Freescale LTIB driver code).
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Li Yang <leoli@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/gadget/fsl_usb2_udc.h')
| -rw-r--r-- | drivers/usb/gadget/fsl_usb2_udc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/usb/gadget/fsl_usb2_udc.h b/drivers/usb/gadget/fsl_usb2_udc.h index 24efba9..5647cc21 100644 --- a/drivers/usb/gadget/fsl_usb2_udc.h +++ b/drivers/usb/gadget/fsl_usb2_udc.h @@ -275,7 +275,9 @@ struct usb_sys_interface { #define USB_MODE_CTRL_MODE_IDLE 0x00000000 #define USB_MODE_CTRL_MODE_DEVICE 0x00000002 #define USB_MODE_CTRL_MODE_HOST 0x00000003 +#define USB_MODE_CTRL_MODE_MASK 0x00000003 #define USB_MODE_CTRL_MODE_RSV 0x00000001 +#define USB_MODE_ES 0x00000004 /* Endian Select */ #define USB_MODE_SETUP_LOCK_OFF 0x00000008 #define USB_MODE_STREAM_DISABLE 0x00000010 /* Endpoint Flush Register */ |