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| author | Eric Bénard <eric@eukrea.com> | 2010-10-15 14:30:58 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-10-22 10:22:17 -0700 |
| commit | 69cb1ec4ce4da4bc4c07bb09c4c98b3e25d99fb1 (patch) | |
| tree | 802b47a9b8d485fda7e0083485a0668c090b0ead /drivers/usb | |
| parent | 0f266abd70cd83571eca019f764b5f1992da7361 (diff) | |
| download | kernel_samsung_smdk4412-69cb1ec4ce4da4bc4c07bb09c4c98b3e25d99fb1.zip kernel_samsung_smdk4412-69cb1ec4ce4da4bc4c07bb09c4c98b3e25d99fb1.tar.gz kernel_samsung_smdk4412-69cb1ec4ce4da4bc4c07bb09c4c98b3e25d99fb1.tar.bz2 | |
mxc_udc: add workaround for ENGcm09152 for i.MX35
this patch gives the possibility to workaround bug ENGcm09152
on i.MX35 when the hardware workaround is also implemented on
the board.
It covers the workaround described on page 25 of the following Errata :
http://cache.freescale.com/files/dsp/doc/errata/IMX35CE.pdf
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb')
| -rw-r--r-- | drivers/usb/gadget/fsl_mxc_udc.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c index eafa6d2..5bdbfe6 100644 --- a/drivers/usb/gadget/fsl_mxc_udc.c +++ b/drivers/usb/gadget/fsl_mxc_udc.c @@ -22,6 +22,10 @@ static struct clk *mxc_ahb_clk; static struct clk *mxc_usb_clk; +/* workaround ENGcm09152 for i.MX35 */ +#define USBPHYCTRL_OTGBASE_OFFSET 0x608 +#define USBPHYCTRL_EVDO (1 << 23) + int fsl_udc_clk_init(struct platform_device *pdev) { struct fsl_usb2_platform_data *pdata; @@ -84,6 +88,17 @@ eenahb: void fsl_udc_clk_finalize(struct platform_device *pdev) { struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; +#if defined(CONFIG_ARCH_MX35) + unsigned int v; + + /* workaround ENGcm09152 for i.MX35 */ + if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) { + v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + USBPHYCTRL_OTGBASE_OFFSET)); + writel(v | USBPHYCTRL_EVDO, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + USBPHYCTRL_OTGBASE_OFFSET)); + } +#endif /* ULPI transceivers don't need usbpll */ if (pdata->phy_mode == FSL_USB2_PHY_ULPI) { |