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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2009-10-20 07:37:32 +0900 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-10-23 11:31:18 -0700 |
| commit | 629598da932cfa5ff398fe10bc123282a6f3049e (patch) | |
| tree | 76c088fea8b45aa63291f8eb5c1d3519d528170d /drivers | |
| parent | 0e442c60dd39ac6924b11a20497734bd2303744c (diff) | |
| download | kernel_samsung_smdk4412-629598da932cfa5ff398fe10bc123282a6f3049e.zip kernel_samsung_smdk4412-629598da932cfa5ff398fe10bc123282a6f3049e.tar.gz kernel_samsung_smdk4412-629598da932cfa5ff398fe10bc123282a6f3049e.tar.bz2 | |
drm/i915: update watermarks before enabling PLLs
When coming back from DPMS or turning on a display, make sure we have
the watermarks set up before turning on the display plane, otherwise we
may get underruns.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Dirk Hohndel <hohndel@infradead.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 47d6ff0..7eed3db 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1803,6 +1803,8 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) case DRM_MODE_DPMS_ON: case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: + intel_update_watermarks(dev); + /* Enable the DPLL */ temp = I915_READ(dpll_reg); if ((temp & DPLL_VCO_ENABLE) == 0) { @@ -1840,7 +1842,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) /* Give the overlay scaler a chance to enable if it's on this pipe */ //intel_crtc_dpms_video(crtc, true); TODO - intel_update_watermarks(dev); break; case DRM_MODE_DPMS_OFF: intel_update_watermarks(dev); |