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| author | Zhang, Yanmin <yanmin.zhang@intel.com> | 2006-07-12 09:41:47 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2006-07-12 16:05:48 -0700 |
| commit | 6f0312fd7e0e6f96fd847b0b2e1e0d2d2e8ef89d (patch) | |
| tree | 0acb72443d142459c76d0bd57c54f8e98291de8f /include/linux/pci_regs.h | |
| parent | 709cf5ea7a8bea1b956d361ee7cef1945423200c (diff) | |
| download | kernel_samsung_smdk4412-6f0312fd7e0e6f96fd847b0b2e1e0d2d2e8ef89d.zip kernel_samsung_smdk4412-6f0312fd7e0e6f96fd847b0b2e1e0d2d2e8ef89d.tar.gz kernel_samsung_smdk4412-6f0312fd7e0e6f96fd847b0b2e1e0d2d2e8ef89d.tar.bz2 | |
[PATCH] PCI: add PCI Express AER register definitions to pci_regs.h
Add new defines of PCI-Express AER registers and their bits into file
include/linux/pci_regs.h.
Signed-off-by: Zhang Yanmin <yanmin.zhang@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/linux/pci_regs.h')
| -rw-r--r-- | include/linux/pci_regs.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 6bce4a2..96930cb 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -422,7 +422,23 @@ #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ +/* Correctable Err Reporting Enable */ +#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 +/* Non-fatal Err Reporting Enable */ +#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 +/* Fatal Err Reporting Enable */ +#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 #define PCI_ERR_ROOT_STATUS 48 +#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ +/* Multi ERR_COR Received */ +#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 +/* ERR_FATAL/NONFATAL Recevied */ +#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 +/* Multi ERR_FATAL/NONFATAL Recevied */ +#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 +#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */ +#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ +#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ #define PCI_ERR_ROOT_COR_SRC 52 #define PCI_ERR_ROOT_SRC 54 |