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author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-11-02 17:30:46 +0800 |
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committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-11-02 10:05:46 +0000 |
commit | d110852513148a7ec44fad4e036455aeb816d713 (patch) | |
tree | 5c72fa12fa653804a4d13658a641a713d6849acd /include/xen | |
parent | 328fc1325f144027f4a8269b11e9f8dcf1edcb97 (diff) | |
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agp/intel: fix cache control for sandybridge
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'include/xen')
0 files changed, 0 insertions, 0 deletions