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authorJason Gunthorpe <jgunthorpe@obsidianresearch.com>2010-03-09 09:17:42 +0000
committerDavid S. Miller <davem@davemloft.net>2010-03-16 21:23:42 -0700
commitabf35df21513c51d7761c41fa6d3b819cdf4103e (patch)
tree3152b04190035149aba67936ef0cff81cc6af3a0 /include
parent23606cf5d1192c2b17912cb2ef6e62f9b11de133 (diff)
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NET: Support clause 45 MDIO commands at the MDIO bus level
IEEE 802.3ae clause 45 specifies a somewhat modified MDIO protocol for use by 10GIGE phys. The main change is a 21 bit address split into a 5 bit device ID and a 16 bit register offset. The definition is designed so that normal and extended devices can run on the same MDIO bus. Extend mdio-bitbang to do the new protocol. At the MDIO bus level the protocol is requested by or'ing MII_ADDR_C45 into the register offset. Make phy_read/phy_write/etc pass a full 32 bit register offset. This does not attempt to make the phy layer support C45 style PHYs, just to provide the MDIO bus support. Tested against a Broadcom 10GE phy with ID 0x206034, and several Broadcom 10/100/1000 Phys in normal mode. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
-rw-r--r--include/linux/phy.h12
1 files changed, 8 insertions, 4 deletions
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 14d7fdf..d9bce4b 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -81,6 +81,10 @@ typedef enum {
*/
#define MII_BUS_ID_SIZE (20 - 3)
+/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
+ IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. */
+#define MII_ADDR_C45 (1<<30)
+
/*
* The Bus class for PHYs. Devices which provide access to
* PHYs should register using this structure
@@ -127,8 +131,8 @@ int mdiobus_register(struct mii_bus *bus);
void mdiobus_unregister(struct mii_bus *bus);
void mdiobus_free(struct mii_bus *bus);
struct phy_device *mdiobus_scan(struct mii_bus *bus, int addr);
-int mdiobus_read(struct mii_bus *bus, int addr, u16 regnum);
-int mdiobus_write(struct mii_bus *bus, int addr, u16 regnum, u16 val);
+int mdiobus_read(struct mii_bus *bus, int addr, u32 regnum);
+int mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val);
#define PHY_INTERRUPT_DISABLED 0x0
@@ -422,7 +426,7 @@ struct phy_fixup {
* because the bus read/write functions may wait for an interrupt
* to conclude the operation.
*/
-static inline int phy_read(struct phy_device *phydev, u16 regnum)
+static inline int phy_read(struct phy_device *phydev, u32 regnum)
{
return mdiobus_read(phydev->bus, phydev->addr, regnum);
}
@@ -437,7 +441,7 @@ static inline int phy_read(struct phy_device *phydev, u16 regnum)
* because the bus read/write functions may wait for an interrupt
* to conclude the operation.
*/
-static inline int phy_write(struct phy_device *phydev, u16 regnum, u16 val)
+static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
{
return mdiobus_write(phydev->bus, phydev->addr, regnum, val);
}