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| author | Mike Dunn <mikedunn@newsguy.com> | 2013-01-07 13:55:12 -0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-01-17 08:44:08 -0800 |
| commit | e2abf662bcedc0be6f73e7575cc203a5e3c9262c (patch) | |
| tree | 1414164fda1b2b8fa8745bf0f2bfb0ebdb5b7839 /sound | |
| parent | 639fd95292222bf03e1bb8616437b261321e1536 (diff) | |
| download | kernel_samsung_smdk4412-e2abf662bcedc0be6f73e7575cc203a5e3c9262c.zip kernel_samsung_smdk4412-e2abf662bcedc0be6f73e7575cc203a5e3c9262c.tar.gz kernel_samsung_smdk4412-e2abf662bcedc0be6f73e7575cc203a5e3c9262c.tar.bz2 | |
ALSA: pxa27x: fix ac97 cold reset
commit 41b645c8624df6ace020a8863ad1449d69140f7d upstream.
Cold reset on the pxa27x currently fails and
pxa2xx_ac97_try_cold_reset: cold reset timeout (GSR=0x44)
appears in the kernel log. Through trial-and-error (the pxa270 developer's
manual is mostly incoherent on the topic of ac97 reset), I got cold reset to
complete by setting the WARM_RST bit in the GCR register (and later noticed that
pxa3xx does this for cold reset as well). Also, a timeout loop is needed to
wait for the reset to complete.
Tested on a palm treo 680 machine.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/arm/pxa2xx-ac97-lib.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c index 88eec38..05bdcb2 100644 --- a/sound/arm/pxa2xx-ac97-lib.c +++ b/sound/arm/pxa2xx-ac97-lib.c @@ -146,6 +146,8 @@ static inline void pxa_ac97_warm_pxa27x(void) static inline void pxa_ac97_cold_pxa27x(void) { + unsigned int timeout; + GCR &= GCR_COLD_RST; /* clear everything but nCRST */ GCR &= ~GCR_COLD_RST; /* then assert nCRST */ @@ -155,8 +157,10 @@ static inline void pxa_ac97_cold_pxa27x(void) clk_enable(ac97conf_clk); udelay(5); clk_disable(ac97conf_clk); - GCR = GCR_COLD_RST; - udelay(50); + GCR = GCR_COLD_RST | GCR_WARM_RST; + timeout = 100; /* wait for the codec-ready bit to be set */ + while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--) + mdelay(1); } #endif |