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authorSrinivas Kandagatla <srinivas.kandagatla@st.com>2011-08-15 10:43:44 +0100
committerGreg Kroah-Hartman <gregkh@suse.de>2011-10-03 11:40:03 -0700
commit0dbf5d84ecfa51949a4543da9b215ad36e3ac63f (patch)
treeca0d3a1af51960933ca6e7c03a2896054ddb9dff /sound
parent5297aef4dd2d5b7f17fe515a0a455bf969bb19a9 (diff)
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ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.
commit 43c734be5571a4daad9f0a3e0b3229a1c0049917 upstream. This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3 bits. The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits [19:17] for Way size, however the existing code only uses 2 bits to get this value. This results in incorrect cachesize calculations. It also results in performing operations on the whole cache when we erroneously decide that the range is big enough (due to l2x0_size being too small) and also prints incorrect cachesize. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'sound')
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