diff options
137 files changed, 596 insertions, 596 deletions
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index a33328e..d27b825 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -177,7 +177,7 @@ cflags-$(CONFIG_CPU_MIPS64) += \ cflags-$(CONFIG_CPU_R5000) += \ $(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \ - -Wa,--trap + -Wa,--trap cflags-$(CONFIG_CPU_R5432) += \ $(call set_gccflags,r5400,mips4,r5000,mips4,mips2) \ @@ -720,7 +720,7 @@ archclean: @$(MAKE) $(clean)=arch/mips/boot @$(MAKE) $(clean)=arch/mips/lasat -# Generate <asm/offset.h +# Generate <asm/offset.h # # The default rule is suffering from funny problems on MIPS so we using our # own ... diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c index 533721e..4e5a6e1 100644 --- a/arch/mips/au1000/common/pci.c +++ b/arch/mips/au1000/common/pci.c @@ -40,14 +40,14 @@ /* TBD */ static struct resource pci_io_resource = { - "pci IO space", + "pci IO space", (u32)PCI_IO_START, (u32)PCI_IO_END, IORESOURCE_IO }; static struct resource pci_mem_resource = { - "pci memory space", + "pci memory space", (u32)PCI_MEM_START, (u32)PCI_MEM_END, IORESOURCE_MEM @@ -68,7 +68,7 @@ static unsigned long virt_io_addr; static int __init au1x_pci_setup(void) { #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) - virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, + virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1); if (!virt_io_addr) { @@ -77,7 +77,7 @@ static int __init au1x_pci_setup(void) } #ifdef CONFIG_DMA_NONCOHERENT - /* + /* * Set the NC bit in controller for Au1500 pre-AC silicon */ u32 prid = read_c0_prid(); diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index dbc8b1b..eff89e1 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -97,7 +97,7 @@ static int __init au1x00_setup(void) argptr = prom_getcmdline(); strcat(argptr, " console=ttyS0,115200"); } -#endif +#endif #ifdef CONFIG_FB_AU1100 if ((argptr = strstr(argptr, "video=")) == NULL) { diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index fe418f1..57675b4 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -281,7 +281,7 @@ unsigned long cal_r4koff(void) cpu_speed = count * 2; } #else - cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * + cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; count = cpu_speed / 2; #endif @@ -356,7 +356,7 @@ static unsigned long do_fast_cp0_gettimeoffset(void) : "hi", "lo", GCC_REG_ACCUM); /* - * Due to possible jiffies inconsistencies, we need to check + * Due to possible jiffies inconsistencies, we need to check * the result so that we'll get a timer that is monotonic. */ if (res >= USECS_PER_JIFFY) @@ -375,8 +375,8 @@ static unsigned long do_fast_pm_gettimeoffset(void) au_sync(); offset = pc0 - last_pc0; if (offset > 2*MATCH20_INC) { - printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n", - (unsigned)offset, (unsigned)last_pc0, + printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n", + (unsigned)offset, (unsigned)last_pc0, (unsigned)last_match20, (unsigned)pc0); } offset = (unsigned long)((offset * 305) / 10); @@ -394,11 +394,11 @@ void au1xxx_timer_setup(struct irqaction *irq) r4k_offset = cal_r4koff(); printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); - //est_freq = 2*r4k_offset*HZ; - est_freq = r4k_offset*HZ; + //est_freq = 2*r4k_offset*HZ; + est_freq = r4k_offset*HZ; est_freq += 5000; /* round */ est_freq -= est_freq%10000; - printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, (est_freq%1000000)*100/1000000); set_au1x00_speed(est_freq); set_au1x00_lcd_clock(); // program the LCD clock diff --git a/arch/mips/au1000/csb250/board_setup.c b/arch/mips/au1000/csb250/board_setup.c index 90426ea..1c55c5f 100644 --- a/arch/mips/au1000/csb250/board_setup.c +++ b/arch/mips/au1000/csb250/board_setup.c @@ -182,7 +182,7 @@ void __init board_setup(void) au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); au_writel(0, Au1500_PCI_MWBASE_REV_CCL); au_writel(0x02a00356, Au1500_PCI_STATCMD); - au_writel(0x00003c04, Au1500_PCI_HDRTYPE); + au_writel(0x00003c04, Au1500_PCI_HDRTYPE); au_writel(0x00000008, Au1500_PCI_MBAR); au_sync(); @@ -216,7 +216,7 @@ csb250_pci_idsel(unsigned int devsel, int assert) unsigned int gpio2_pins; retval = 1; - + /* First, disable both selects, then assert the one requested. */ au_writel(0xc000c000, GPIO2_OUTPUT); diff --git a/arch/mips/au1000/csb250/init.c b/arch/mips/au1000/csb250/init.c index 4320057..bd99733 100644 --- a/arch/mips/au1000/csb250/init.c +++ b/arch/mips/au1000/csb250/init.c @@ -81,7 +81,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) csb_env[0] = env1; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_CSB250; + mips_machtype = MACH_CSB250; prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c index 51eee94..4b9d5e4 100644 --- a/arch/mips/au1000/db1x00/init.c +++ b/arch/mips/au1000/db1x00/init.c @@ -61,7 +61,7 @@ void __init prom_init(void) prom_envp = (char **) fw_arg2; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_DB1000; /* set the platform # */ + mips_machtype = MACH_DB1000; /* set the platform # */ prom_init_cmdline(); diff --git a/arch/mips/au1000/hydrogen3/init.c b/arch/mips/au1000/hydrogen3/init.c index eee4adf..8cc9879 100644 --- a/arch/mips/au1000/hydrogen3/init.c +++ b/arch/mips/au1000/hydrogen3/init.c @@ -63,7 +63,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) prom_envp = envp; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_DB1000; /* set the platform # */ + mips_machtype = MACH_DB1000; /* set the platform # */ prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/au1000/pb1000/board_setup.c index 2fa211b..0b4807d 100644 --- a/arch/mips/au1000/pb1000/board_setup.c +++ b/arch/mips/au1000/pb1000/board_setup.c @@ -174,7 +174,7 @@ void __init board_setup(void) case 0x02: /* HB */ break; default: /* HC and newer */ - /* Enable sys bus clock divider when IDLE state or no bus + /* Enable sys bus clock divider when IDLE state or no bus activity. */ au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); break; diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/au1000/xxs1500/board_setup.c index 9dadc82..1e59433 100644 --- a/arch/mips/au1000/xxs1500/board_setup.c +++ b/arch/mips/au1000/xxs1500/board_setup.c @@ -49,7 +49,7 @@ void board_reset (void) void __init board_setup(void) { u32 pin_func; - + // set multiple use pins (UART3/GPIO) to UART (it's used as UART too) pin_func = au_readl(SYS_PINFUNC) & (u32)(~SYS_PF_UR3); pin_func |= SYS_PF_UR3; @@ -75,11 +75,11 @@ void __init board_setup(void) au_writel(1, GPIO2_ENABLE); /* gpio2 208/9/10/11 are inputs */ au_writel((1<<8) | (1<<9) | (1<<10) | (1<<11), GPIO2_DIR); - + /* turn off power */ au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<14))|(1<<30), GPIO2_OUTPUT); #endif - + #ifdef CONFIG_PCI #if defined(__MIPSEB__) diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/au1000/xxs1500/init.c index 03f7552..f1c7653 100644 --- a/arch/mips/au1000/xxs1500/init.c +++ b/arch/mips/au1000/xxs1500/init.c @@ -55,7 +55,7 @@ void __init prom_init(void) prom_envp = (char **) fw_arg2; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_XXS1500; /* set the platform # */ + mips_machtype = MACH_XXS1500; /* set the platform # */ prom_init_cmdline(); diff --git a/arch/mips/au1000/xxs1500/irqmap.c b/arch/mips/au1000/xxs1500/irqmap.c index 954800a..52f2f7d 100644 --- a/arch/mips/au1000/xxs1500/irqmap.c +++ b/arch/mips/au1000/xxs1500/irqmap.c @@ -56,7 +56,7 @@ au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, - { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */ diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c index 5f027bf..9ffe1a9 100644 --- a/arch/mips/ddb5xxx/ddb5477/irq.c +++ b/arch/mips/ddb5xxx/ddb5477/irq.c @@ -76,7 +76,7 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) extern void vrc5477_irq_init(u32 base); extern void mips_cpu_irq_init(u32 base); extern asmlinkage void ddb5477_handle_int(void); -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); +extern int setup_irq(unsigned int irq, struct irqaction *irqaction); static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; void __init arch_init_irq(void) @@ -94,7 +94,7 @@ void __init arch_init_irq(void) /* setup PCI interrupt attributes */ set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); - if (mips_machtype == MACH_NEC_ROCKHOPPERII) + if (mips_machtype == MACH_NEC_ROCKHOPPERII) set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); else set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); @@ -134,7 +134,7 @@ void __init arch_init_irq(void) /* setup cascade interrupts */ setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); - setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); + setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); /* hook up the first-level interrupt handler */ set_except_vector(0, ddb5477_handle_int); diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c index 15c6e54..d62f5a7 100644 --- a/arch/mips/ddb5xxx/ddb5477/setup.c +++ b/arch/mips/ddb5xxx/ddb5477/setup.c @@ -141,7 +141,7 @@ static void __init ddb_time_init(void) /* mips_hpt_frequency is 1/2 of the cpu core freq */ i = (read_c0_config() >> 28 ) & 7; - if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) + if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) i = 4; mips_hpt_frequency = bus_frequency*(i+4)/4; } @@ -298,11 +298,11 @@ static void __init ddb5477_board_init(void) if (mips_machtype == MACH_NEC_ROCKHOPPER || mips_machtype == MACH_NEC_ROCKHOPPERII) { - /* Disable bus diagnostics. */ + /* Disable bus diagnostics. */ ddb_out32(DDB_PCICTL0_L, 0); ddb_out32(DDB_PCICTL0_H, 0); ddb_out32(DDB_PCICTL1_L, 0); - ddb_out32(DDB_PCICTL1_H, 0); + ddb_out32(DDB_PCICTL1_H, 0); } if (mips_machtype == MACH_NEC_ROCKHOPPER) { @@ -354,7 +354,7 @@ static void __init ddb5477_board_init(void) */ pci_write_config_byte(&dev_m1533, 0x58, 0x74); - /* + /* * positive decode (bit6 -0) * enable IDE controler interrupt (bit 4 -1) * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101) @@ -364,31 +364,31 @@ static void __init ddb5477_board_init(void) /* Setup M5229 registers */ dev_m5229.bus = &bus; dev_m5229.sysdata = NULL; - dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE + dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE /* * enable IDE in the M5229 config register 0x50 (bit 0 - 1) - * M5229 IDSEL is addr:15; see above setting + * M5229 IDSEL is addr:15; see above setting */ pci_read_config_byte(&dev_m5229, 0x50, &temp8); pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1); - /* - * enable bus master (bit 2) and IO decoding (bit 0) + /* + * enable bus master (bit 2) and IO decoding (bit 0) */ pci_read_config_byte(&dev_m5229, 0x04, &temp8); pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5); /* * enable native, copied from arch/ppc/k2boot/head.S - * TODO - need volatile, need to be portable + * TODO - need volatile, need to be portable */ pci_write_config_byte(&dev_m5229, 0x09, 0xef); - /* Set Primary Channel Command Block Timing */ + /* Set Primary Channel Command Block Timing */ pci_write_config_byte(&dev_m5229, 0x59, 0x31); - /* + /* * Enable primary channel 40-pin cable * M5229 register 0x4a (bit 0) */ diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c index 133fb7c..6dbce92 100644 --- a/arch/mips/dec/ecc-berr.c +++ b/arch/mips/dec/ecc-berr.c @@ -253,7 +253,7 @@ static inline void dec_kn03_be_init(void) kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); - + /* * Set normal ECC detection and generation, enable ECC correction. * For KN05 we also need to make sure EE (?) is enabled in the MB. diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c index d808a67..a5f6d84 100644 --- a/arch/mips/ite-boards/generic/it8172_setup.c +++ b/arch/mips/ite-boards/generic/it8172_setup.c @@ -129,7 +129,7 @@ static void __init it8172_setup(void) /* * IO/MEM resources. - * + * * revisit this area. */ set_io_port_base(KSEG1); diff --git a/arch/mips/ite-boards/generic/time.c b/arch/mips/ite-boards/generic/time.c index 30a6c0d..f5d67ee 100644 --- a/arch/mips/ite-boards/generic/time.c +++ b/arch/mips/ite-boards/generic/time.c @@ -72,7 +72,7 @@ static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; } static inline unsigned char bin_to_hw(unsigned char c) { - if (rtc_dm_binary()) + if (rtc_dm_binary()) return c; else return ((c/10) << 4) + (c%10); @@ -91,9 +91,9 @@ hw_to_bin(unsigned char c) static inline unsigned char hour_bin_to_hw(unsigned char c) { - if (rtc_24h()) + if (rtc_24h()) return bin_to_hw(c); - if (c >= 12) + if (c >= 12) return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */ else return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */ @@ -105,9 +105,9 @@ hour_hw_to_bin(unsigned char c) unsigned char tmp = hw_to_bin(c&0x3f); if (rtc_24h()) return tmp; - if (c & 0x80) + if (c & 0x80) return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */ - else + else return (tmp==12)?0:tmp; /* 12am is 0 */ } @@ -145,7 +145,7 @@ static unsigned long __init cal_r4koff(void) return (mips_hpt_frequency / HZ); } -static unsigned long +static unsigned long it8172_rtc_get_time(void) { unsigned int year, mon, day, hour, min, sec; @@ -166,12 +166,12 @@ it8172_rtc_get_time(void) hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS)); day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH)); mon = hw_to_bin(CMOS_READ(RTC_MONTH)); - year = hw_to_bin(CMOS_READ(RTC_YEAR)) + + year = hw_to_bin(CMOS_READ(RTC_YEAR)) + hw_to_bin(*rtc_century_reg) * 100; /* restore interrupts */ local_irq_restore(flags); - + return mktime(year, mon, day, hour, min, sec); } diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c index ed47041..6b645fb 100644 --- a/arch/mips/kernel/binfmt_elfn32.c +++ b/arch/mips/kernel/binfmt_elfn32.c @@ -103,7 +103,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) * Convert jiffies to nanoseconds and seperate with * one divide. */ - u64 nsec = (u64)jiffies * TICK_NSEC; + u64 nsec = (u64)jiffies * TICK_NSEC; value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec); value->tv_usec /= NSEC_PER_USEC; } diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c index ee21b18..b4075e9 100644 --- a/arch/mips/kernel/binfmt_elfo32.c +++ b/arch/mips/kernel/binfmt_elfo32.c @@ -105,7 +105,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) * Convert jiffies to nanoseconds and seperate with * one divide. */ - u64 nsec = (u64)jiffies * TICK_NSEC; + u64 nsec = (u64)jiffies * TICK_NSEC; value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec); value->tv_usec /= NSEC_PER_USEC; } diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c index 11ebe5d..47a087b 100644 --- a/arch/mips/kernel/cpu-bugs64.c +++ b/arch/mips/kernel/cpu-bugs64.c @@ -137,7 +137,7 @@ static inline void check_mult_sh(void) for (i = 0; i < 8; i++) if (v1[i] != w[i]) bug = 1; - + if (bug == 0) { printk("no.\n"); return; @@ -149,7 +149,7 @@ static inline void check_mult_sh(void) for (i = 0; i < 8; i++) if (v2[i] != w[i]) fix = 0; - + if (fix == 1) { printk("yes.\n"); return; diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c index 2698893..d3fd1ab 100644 --- a/arch/mips/kernel/gdb-stub.c +++ b/arch/mips/kernel/gdb-stub.c @@ -687,8 +687,8 @@ void handle_exception (struct gdb_regs *regs) * acquire the big kgdb spinlock */ if (!spin_trylock(&kgdb_lock)) { - /* - * some other CPU has the lock, we should go back to + /* + * some other CPU has the lock, we should go back to * receive the gdb_wait IPC */ return; @@ -703,7 +703,7 @@ void handle_exception (struct gdb_regs *regs) async_bp.addr = 0; } - /* + /* * acquire the CPU spinlocks */ for (i = num_online_cpus()-1; i >= 0; i--) @@ -894,7 +894,7 @@ void handle_exception (struct gdb_regs *regs) ptr = &input_buffer[1]; if (hexToLong(&ptr, &addr)) regs->cp0_epc = addr; - + goto exit_kgdb_exception; break; @@ -1001,7 +1001,7 @@ void breakpoint(void) return; __asm__ __volatile__( - ".globl breakinst\n\t" + ".globl breakinst\n\t" ".set\tnoreorder\n\t" "nop\n" "breakinst:\tbreak\n\t" @@ -1014,7 +1014,7 @@ void breakpoint(void) void async_breakpoint(void) { __asm__ __volatile__( - ".globl async_breakinst\n\t" + ".globl async_breakinst\n\t" ".set\tnoreorder\n\t" "nop\n" "async_breakinst:\tbreak\n\t" diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 3a1a3e7..9bb2caa 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -246,10 +246,10 @@ NESTED(nmi_handler, PT_SIZE, sp) LONG_L a1, PT_EPC(sp) #if CONFIG_32BIT PRINT("Got \nexception at %08lx\012") -#endif +#endif #if CONFIG_64BIT PRINT("Got \nexception at %016lx\012") -#endif +#endif .endm .macro __BUILD_count exception diff --git a/arch/mips/kernel/ioctl32.c b/arch/mips/kernel/ioctl32.c index 519cd5d..c069719 100644 --- a/arch/mips/kernel/ioctl32.c +++ b/arch/mips/kernel/ioctl32.c @@ -27,7 +27,7 @@ long sys_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg); #include "compat_ioctl.c" typedef int (* ioctl32_handler_t)(unsigned int, unsigned int, unsigned long, struct file *); - + #define COMPATIBLE_IOCTL(cmd) HANDLE_IOCTL((cmd),sys_ioctl) #define HANDLE_IOCTL(cmd,handler) { (cmd), (ioctl32_handler_t)(handler), NULL }, #define IOCTL_TABLE_START \ diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 441157a..7d93992 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -77,7 +77,7 @@ int show_interrupts(struct seq_file *p, void *v) if (i < NR_IRQS) { spin_lock_irqsave(&irq_desc[i].lock, flags); action = irq_desc[i].action; - if (!action) + if (!action) goto skip; seq_printf(p, "%3d: ",i); #ifndef CONFIG_SMP diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 993abc8..4613219 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -313,7 +313,7 @@ asmlinkage int sys32_sysinfo(struct sysinfo32 *info) struct sysinfo s; int ret, err; mm_segment_t old_fs = get_fs (); - + set_fs (KERNEL_DS); ret = sys_sysinfo(&s); set_fs (old_fs); @@ -560,7 +560,7 @@ struct ipc64_perm32 { compat_gid_t gid; compat_uid_t cuid; compat_gid_t cgid; - compat_mode_t mode; + compat_mode_t mode; unsigned short seq; unsigned short __pad1; unsigned int __unused1; @@ -1334,17 +1334,17 @@ asmlinkage int sys32_sendfile(int out_fd, int in_fd, compat_off_t *offset, mm_segment_t old_fs = get_fs(); int ret; off_t of; - + if (offset && get_user(of, offset)) return -EFAULT; - + set_fs(KERNEL_DS); ret = sys_sendfile(out_fd, in_fd, offset ? &of : NULL, count); set_fs(old_fs); - + if (offset && put_user(of, offset)) return -EFAULT; - + return ret; } @@ -1362,11 +1362,11 @@ static unsigned char socketcall_nargs[18]={AL(0),AL(3),AL(3),AL(3),AL(2),AL(3), #undef AL /* - * System call vectors. + * System call vectors. * * Argument checking cleaned up. Saved 20% in size. * This function doesn't need to set the kernel lock because - * it is set by the callees. + * it is set by the callees. */ asmlinkage long sys32_socketcall(int call, unsigned int *args32) @@ -1402,11 +1402,11 @@ asmlinkage long sys32_socketcall(int call, unsigned int *args32) /* copy_from_user should be SMP safe. */ if (copy_from_user(a, args32, socketcall_nargs[call])) return -EFAULT; - + a0=a[0]; a1=a[1]; - - switch(call) + + switch(call) { case SYS_SOCKET: err = sys_socket(a0,a1,a[2]); diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S index 243e7b6..f100196 100644 --- a/arch/mips/kernel/r2300_switch.S +++ b/arch/mips/kernel/r2300_switch.S @@ -35,7 +35,7 @@ /* * FPU context is saved iff the process has used it's FPU in the current * time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user - * space STATUS register should be 0, so that a process *always* starts its + * space STATUS register should be 0, so that a process *always* starts its * userland with FPU disabled after each context switch. * * FPU will be enabled as soon as the process accesses FPU again, through @@ -55,7 +55,7 @@ LEAF(resume) cpu_save_nonscratch a0 sw ra, THREAD_REG31(a0) - /* + /* * check if we need to save FPU registers */ lw t3, TASK_THREAD_INFO(a0) diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index 175dd1f..e02b772 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -33,7 +33,7 @@ /* * FPU context is saved iff the process has used it's FPU in the current * time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user - * space STATUS register should be 0, so that a process *always* starts its + * space STATUS register should be 0, so that a process *always* starts its * userland with FPU disabled after each context switch. * * FPU will be enabled as soon as the process accesses FPU again, through @@ -164,7 +164,7 @@ LEAF(_init_fpu) dmtc1 t1, $f31 1: #endif - + #ifdef CONFIG_CPU_MIPS32 mtc1 t1, $f0 mtc1 t1, $f1 diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index f6875f0..8ddfbd8 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -558,7 +558,7 @@ static inline int setup_sigcontext32(struct pt_regs *regs, if (!used_math()) goto out; - /* + /* * Save FPU state to signal context. Signal handler will "inherit" * current FPU state. */ diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index e830d78..482ac31 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -15,7 +15,7 @@ SECTIONS /* This is the value for an Origin kernel, taken from an IRIX kernel. */ /* . = 0xc00000000001c000; */ - /* Set the vaddr for the text segment to a value + /* Set the vaddr for the text segment to a value >= 0xa800 0000 0001 9000 if no symmon is going to configured >= 0xa800 0000 0030 0000 otherwise */ diff --git a/arch/mips/lasat/at93c.c b/arch/mips/lasat/at93c.c index f6add04..ca26e55 100644 --- a/arch/mips/lasat/at93c.c +++ b/arch/mips/lasat/at93c.c @@ -1,7 +1,7 @@ -/* +/* * Atmel AT93C46 serial eeprom driver * - * Brian Murphy <brian.murphy@eicon.com> + * Brian Murphy <brian.murphy@eicon.com> * */ #include <linux/kernel.h> @@ -21,12 +21,12 @@ struct at93c_defs *at93c; -static void at93c_reg_write(u32 val) +static void at93c_reg_write(u32 val) { *at93c->reg = val; } -static u32 at93c_reg_read(void) +static u32 at93c_reg_read(void) { u32 tmp = *at93c->reg; return tmp; @@ -81,7 +81,7 @@ static u8 at93c_read_byte(void) } static void at93c_write_bits(u32 data, int size) -{ +{ int i; int shift = size - 1; u32 mask = (1 << shift); @@ -90,7 +90,7 @@ static void at93c_write_bits(u32 data, int size) at93c_write_databit((data & mask) >> shift); data <<= 1; } -} +} static void at93c_init_op(void) { @@ -104,8 +104,8 @@ static void at93c_end_op(void) lasat_ndelay(250); } -static void at93c_wait(void) -{ +static void at93c_wait(void) +{ at93c_init_op(); while (!at93c_read_databit()) ; diff --git a/arch/mips/lasat/at93c.h b/arch/mips/lasat/at93c.h index a912ac2..cfe2f99 100644 --- a/arch/mips/lasat/at93c.h +++ b/arch/mips/lasat/at93c.h @@ -1,7 +1,7 @@ -/* +/* * Atmel AT93C46 serial eeprom driver * - * Brian Murphy <brian.murphy@eicon.com> + * Brian Murphy <brian.murphy@eicon.com> * */ diff --git a/arch/mips/lasat/ds1603.c b/arch/mips/lasat/ds1603.c index 7bbf6cf..9d7812e 100644 --- a/arch/mips/lasat/ds1603.c +++ b/arch/mips/lasat/ds1603.c @@ -1,7 +1,7 @@ -/* - * Dallas Semiconductors 1603 RTC driver +/* + * Dallas Semiconductors 1603 RTC driver * - * Brian Murphy <brian@murphy.dk> + * Brian Murphy <brian@murphy.dk> * */ #include <linux/kernel.h> @@ -20,12 +20,12 @@ struct ds_defs *ds1603 = NULL; /* HW specific register functions */ -static void rtc_reg_write(unsigned long val) +static void rtc_reg_write(unsigned long val) { *ds1603->reg = val; } -static unsigned long rtc_reg_read(void) +static unsigned long rtc_reg_read(void) { unsigned long tmp = *ds1603->reg; return tmp; @@ -80,7 +80,7 @@ static unsigned int rtc_read_databit(void) { unsigned int data; - data = (rtc_datareg_read() & (1 << ds1603->data_read_shift)) + data = (rtc_datareg_read() & (1 << ds1603->data_read_shift)) >> ds1603->data_read_shift; rtc_cycle_clock(rtc_reg_read()); return data; diff --git a/arch/mips/lasat/ds1603.h b/arch/mips/lasat/ds1603.h index 55f3b04..c2e5c76 100644 --- a/arch/mips/lasat/ds1603.h +++ b/arch/mips/lasat/ds1603.h @@ -1,7 +1,7 @@ -/* - * Dallas Semiconductors 1603 RTC driver +/* + * Dallas Semiconductors 1603 RTC driver * - * Brian Murphy <brian@murphy.dk> + * Brian Murphy <brian@murphy.dk> * */ #ifndef __DS1603_H diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile index 18b6430..35ecd64 100644 --- a/arch/mips/lasat/image/Makefile +++ b/arch/mips/lasat/image/Makefile @@ -21,7 +21,7 @@ LDSCRIPT= -L$(obj) -Tromscript.normal HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \ -D_kernel_entry=0x$(KERNEL_ENTRY) \ -D VERSION="\"$(Version)\"" \ - -D TIMESTAMP=$(shell date +%s) + -D TIMESTAMP=$(shell date +%s) $(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE) $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $< diff --git a/arch/mips/lasat/image/head.S b/arch/mips/lasat/image/head.S index 426bd7d..efb95f2 100644 --- a/arch/mips/lasat/image/head.S +++ b/arch/mips/lasat/image/head.S @@ -27,5 +27,5 @@ reldate: .word TIMESTAMP .org 0x50 -release: +release: .string VERSION diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index 1148a2d..c90da16 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -15,7 +15,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * Routines for generic manipulation of the interrupts found on the + * Routines for generic manipulation of the interrupts found on the * Lasat boards. */ #include <linux/init.h> @@ -101,7 +101,7 @@ static unsigned long get_int_status_100(void) return *lasat_int_status & *lasat_int_mask; } -static unsigned long get_int_status_200(void) +static unsigned long get_int_status_200(void) { unsigned long int_status; diff --git a/arch/mips/lasat/lasat_board.c b/arch/mips/lasat/lasat_board.c index 8c784bc..fc9b0e2 100644 --- a/arch/mips/lasat/lasat_board.c +++ b/arch/mips/lasat/lasat_board.c @@ -67,7 +67,7 @@ static void init_flash_sizes(void) if (mips_machtype == MACH_LASAT_100) { lasat_board_info.li_flash_base = 0x1e000000; - + lb[LASAT_MTD_BOOTLOADER] = 0x1e400000; if (lasat_board_info.li_flash_size > 0x200000) { @@ -103,7 +103,7 @@ int lasat_init_board_info(void) memset(&lasat_board_info, 0, sizeof(lasat_board_info)); /* First read the EEPROM info */ - EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info, + EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info, sizeof(struct lasat_eeprom_struct)); /* Check the CRC */ @@ -188,7 +188,7 @@ int lasat_init_board_info(void) case 0x1: lasat_board_info.li_cpu_hz = lasat_board_info.li_bus_hz + - (lasat_board_info.li_bus_hz >> 1); + (lasat_board_info.li_bus_hz >> 1); break; case 0x2: lasat_board_info.li_cpu_hz = @@ -271,7 +271,7 @@ void lasat_write_eeprom_info(void) lasat_board_info.li_eeprom_info.crc32 = crc; /* Write the EEPROM info */ - EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info, + EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info, sizeof(struct lasat_eeprom_struct)); } diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c index 5637cd1..9ae82c3 100644 --- a/arch/mips/lasat/picvue.c +++ b/arch/mips/lasat/picvue.c @@ -1,7 +1,7 @@ -/* +/* * Picvue PVC160206 display driver * - * Brian Murphy <brian@murphy.dk> + * Brian Murphy <brian@murphy.dk> * */ #include <linux/kernel.h> @@ -24,12 +24,12 @@ struct pvc_defs *picvue = NULL; DECLARE_MUTEX(pvc_sem); -static void pvc_reg_write(u32 val) +static void pvc_reg_write(u32 val) { *picvue->reg = val; } -static u32 pvc_reg_read(void) +static u32 pvc_reg_read(void) { u32 tmp = *picvue->reg; return tmp; @@ -65,12 +65,12 @@ static u8 pvc_read_data(void) { u32 data = pvc_reg_read(); u8 byte; - data |= picvue->rw; + data |= picvue->rw; data &= ~picvue->rs; pvc_reg_write(data); ndelay(40); byte = pvc_read_byte(data); - data |= picvue->rs; + data |= picvue->rs; pvc_reg_write(data); return byte; } diff --git a/arch/mips/lasat/picvue.h b/arch/mips/lasat/picvue.h index 74a3903..2a96bf9 100644 --- a/arch/mips/lasat/picvue.h +++ b/arch/mips/lasat/picvue.h @@ -1,7 +1,7 @@ -/* +/* * Picvue PVC160206 display driver * - * Brian Murphy <brian.murphy@eicon.com> + * Brian Murphy <brian.murphy@eicon.com> * */ #include <asm/semaphore.h> diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c index eaa2b46..cce7cdd 100644 --- a/arch/mips/lasat/picvue_proc.c +++ b/arch/mips/lasat/picvue_proc.c @@ -1,7 +1,7 @@ -/* +/* * Picvue PVC160206 display driver * - * Brian Murphy <brian.murphy@eicon.com> + * Brian Murphy <brian.murphy@eicon.com> * */ #include <linux/kernel.h> @@ -51,10 +51,10 @@ static int pvc_proc_read_line(char *page, char **start, page += sprintf(page, "%s\n", pvc_lines[lineno]); up(&pvc_sem); - return page - origpage; + return page - origpage; } -static int pvc_proc_write_line(struct file *file, const char *buffer, +static int pvc_proc_write_line(struct file *file, const char *buffer, unsigned long count, void *data) { int origcount = count; @@ -119,7 +119,7 @@ static int pvc_proc_read_scroll(char *page, char **start, page += sprintf(page, "%d\n", scroll_dir * scroll_interval); up(&pvc_sem); - return page - origpage; + return page - origpage; } diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c index ca62881..88c7ab8 100644 --- a/arch/mips/lasat/prom.c +++ b/arch/mips/lasat/prom.c @@ -42,7 +42,7 @@ static void null_prom_putc(char c) /* these are functions provided by the bootloader */ static void (* prom_putc)(char c) = null_prom_putc; void (* prom_printf)(const char * fmt, ...) = null_prom_printf; -void (* prom_display)(const char *string, int pos, int clear) = +void (* prom_display)(const char *string, int pos, int clear) = null_prom_display; void (* prom_monitor)(void) = null_prom_monitor; diff --git a/arch/mips/lasat/reset.c b/arch/mips/lasat/reset.c index 37e4912..8d7d7a4 100644 --- a/arch/mips/lasat/reset.c +++ b/arch/mips/lasat/reset.c @@ -1,4 +1,4 @@ -/* +/* * Thomas Horsten <thh@lasat.com> * Copyright (C) 2000 LASAT Networks A/S. * diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c index e371ed5..f2604fa 100644 --- a/arch/mips/lasat/setup.c +++ b/arch/mips/lasat/setup.c @@ -105,7 +105,7 @@ static int lasat_panic_prom_monitor(struct notifier_block *this, return NOTIFY_DONE; } -static struct notifier_block lasat_panic_block[] = +static struct notifier_block lasat_panic_block[] = { { lasat_panic_display, NULL, INT_MAX }, { lasat_panic_prom_monitor, NULL, INT_MIN } @@ -120,7 +120,7 @@ static void lasat_timer_setup(struct irqaction *irq) { write_c0_compare( - read_c0_count() + + read_c0_count() + mips_hpt_frequency / HZ); change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); } diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c index 1c0cc62..8ff43a1 100644 --- a/arch/mips/lasat/sysctl.c +++ b/arch/mips/lasat/sysctl.c @@ -37,14 +37,14 @@ static DECLARE_MUTEX(lasat_info_sem); -/* Strategy function to write EEPROM after changing string entry */ +/* Strategy function to write EEPROM after changing string entry */ int sysctl_lasatstring(ctl_table *table, int *name, int nlen, void *oldval, size_t *oldlenp, void *newval, size_t newlen, void **context) { int r; down(&lasat_info_sem); - r = sysctl_string(table, name, + r = sysctl_string(table, name, nlen, oldval, oldlenp, newval, newlen, context); if (r < 0) { up(&lasat_info_sem); @@ -74,7 +74,7 @@ int proc_dolasatstring(ctl_table *table, int write, struct file *filp, return 0; } -/* proc function to write EEPROM after changing int entry */ +/* proc function to write EEPROM after changing int entry */ int proc_dolasatint(ctl_table *table, int write, struct file *filp, void *buffer, size_t *lenp, loff_t *ppos) { @@ -93,7 +93,7 @@ int proc_dolasatint(ctl_table *table, int write, struct file *filp, static int rtctmp; #ifdef CONFIG_DS1603 -/* proc function to read/write RealTime Clock */ +/* proc function to read/write RealTime Clock */ int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, void *buffer, size_t *lenp, loff_t *ppos) { @@ -165,9 +165,9 @@ static char lasat_bcastaddr[16]; void update_bcastaddr(void) { unsigned int ip; - - ip = (lasat_board_info.li_eeprom_info.ipaddr & - lasat_board_info.li_eeprom_info.netmask) | + + ip = (lasat_board_info.li_eeprom_info.ipaddr & + lasat_board_info.li_eeprom_info.netmask) | ~lasat_board_info.li_eeprom_info.netmask; sprintf(lasat_bcastaddr, "%d.%d.%d.%d", @@ -205,7 +205,7 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp, break; len++; } - if (len >= sizeof(proc_lasat_ipbuf)-1) + if (len >= sizeof(proc_lasat_ipbuf)-1) len = sizeof(proc_lasat_ipbuf) - 1; if (copy_from_user(proc_lasat_ipbuf, buffer, len)) { @@ -249,8 +249,8 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp, } #endif /* defined(CONFIG_INET) */ -static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, - void *oldval, size_t *oldlenp, +static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, void *newval, size_t newlen, void **context) { @@ -293,7 +293,7 @@ int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp, if (!strcmp(filp->f_dentry->d_name.name, "debugaccess")) lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess; } - lasat_write_eeprom_info(); + lasat_write_eeprom_info(); up(&lasat_info_sem); return 0; } @@ -316,8 +316,8 @@ static ctl_table lasat_table[] = { 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec}, {LASAT_NETMASK, "netmask", &lasat_board_info.li_eeprom_info.netmask, sizeof(int), 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec}, - {LASAT_BCAST, "bcastaddr", &lasat_bcastaddr, - sizeof(lasat_bcastaddr), 0600, NULL, + {LASAT_BCAST, "bcastaddr", &lasat_bcastaddr, + sizeof(lasat_bcastaddr), 0600, NULL, &proc_dostring, &sysctl_string}, #endif {LASAT_PASSWORD, "passwd_hash", &lasat_board_info.li_eeprom_info.passwd_hash, sizeof(lasat_board_info.li_eeprom_info.passwd_hash), diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile index fd6a2ba..ad28578 100644 --- a/arch/mips/lib-32/Makefile +++ b/arch/mips/lib-32/Makefile @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o memset.o watch.o +lib-y += csum_partial.o memset.o watch.o obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile index fd6a2ba..ad28578 100644 --- a/arch/mips/lib-64/Makefile +++ b/arch/mips/lib-64/Makefile @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o memset.o watch.o +lib-y += csum_partial.o memset.o watch.o obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S index 00d73be..90ee8d4 100644 --- a/arch/mips/lib/memcpy.S +++ b/arch/mips/lib/memcpy.S @@ -101,7 +101,7 @@ #define NBYTES 8 #define LOG_NBYTES 3 -/* +/* * As we are sharing code base with the mips32 tree (which use the o32 ABI * register definitions). We need to redefine the register definitions from * the n64 ABI register naming to the o32 ABI register naming. @@ -118,7 +118,7 @@ #define t5 $13 #define t6 $14 #define t7 $15 - + #else #define LOAD lw diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index 8f1d875..19d4b07 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c @@ -122,7 +122,7 @@ void __init arch_init_irq(void) int i; atlas_hw0_icregs = (struct atlas_ictrl_regs *)ioremap (ATLAS_ICTRL_REGS_BASE, sizeof(struct atlas_ictrl_regs *)); - + /* * Mask out all interrupt by writing "1" to all bit position in * the interrupt reset reg. diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 31caf06..311155d 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -200,7 +200,7 @@ void __init kgdb_config (void) generic_putDebugChar = saa9730_putDebugChar; generic_getDebugChar = saa9730_getDebugChar; } - else + else #endif { speed = rs_kgdb_hook(line, speed); @@ -243,7 +243,7 @@ void __init prom_init(void) mips_revision_corid = MIPS_REVISION_CORID; if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { - if (BONITO_PCIDID == 0x0001df53 || + if (BONITO_PCIDID == 0x0001df53 || BONITO_PCIDID == 0x0003df53) mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; else @@ -310,7 +310,7 @@ void __init prom_init(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_EMUL_MSC: - _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); + _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); #ifdef CONFIG_CPU_LITTLE_ENDIAN MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index fe7fc17..1631544 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -89,7 +89,7 @@ static unsigned int __init estimate_cpu_frequency(void) * really calculate the timer frequency * For now we hardwire the SEAD board frequency to 12MHz. */ - + if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) count = 12000000; diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index 3377e66..df6db64 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -149,15 +149,15 @@ static int __init malta_setup(void) argptr = prom_getcmdline(); if (strstr(argptr, "iobcuncached")) { BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); printk("Disabled Bonito IOBC coherency\n"); } else { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG |= - (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); printk("Disabled Bonito IOBC coherency\n"); } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 20d4072..5ea84bc 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -126,13 +126,13 @@ static inline void tx49_blast_icache32(void) CACHE32_UNROLL32_ALIGN2; /* I'm in even chunk. blast odd chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start + 0x400; addr < end; addr += 0x400 * 2) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start + 0x400; addr < end; addr += 0x400 * 2) cache32_unroll32(addr|ws,Index_Invalidate_I); CACHE32_UNROLL32_ALIGN; /* I'm in odd chunk. blast even chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400 * 2) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400 * 2) cache32_unroll32(addr|ws,Index_Invalidate_I); } @@ -156,13 +156,13 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page) CACHE32_UNROLL32_ALIGN2; /* I'm in even chunk. blast odd chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start + 0x400; addr < end; addr += 0x400 * 2) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start + 0x400; addr < end; addr += 0x400 * 2) cache32_unroll32(addr|ws,Index_Invalidate_I); CACHE32_UNROLL32_ALIGN; /* I'm in odd chunk. blast even chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400 * 2) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400 * 2) cache32_unroll32(addr|ws,Index_Invalidate_I); } diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c index ab30afd..502f68c 100644 --- a/arch/mips/mm/c-sb1.c +++ b/arch/mips/mm/c-sb1.c @@ -270,7 +270,7 @@ static void local_sb1_flush_icache_range(unsigned long start, __sb1_writeback_inv_dcache_all(); else __sb1_writeback_inv_dcache_range(start, end); - + /* Just flush the whole icache if the range is big enough */ if ((end - start) > icache_range_cutoff) __sb1_flush_icache_all(); diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c index 13d96d6..7166ffe 100644 --- a/arch/mips/mm/cerr-sb1.c +++ b/arch/mips/mm/cerr-sb1.c @@ -25,7 +25,7 @@ #include <asm/sibyte/sb1250_regs.h> #include <asm/sibyte/sb1250_scd.h> #endif - + /* SB1 definitions */ /* XXX should come from config1 XXX */ @@ -136,14 +136,14 @@ static inline void breakout_cerrd(unsigned int val) #ifndef CONFIG_SIBYTE_BUS_WATCHER -static void check_bus_watcher(void) -{ +static void check_bus_watcher(void) +{ uint32_t status, l2_err, memio_err; /* Destructive read, clears register and interrupt */ status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); /* Bit 31 is always on, but there's no #define for that */ - if (status & ~(1UL << 31)) { + if (status & ~(1UL << 31)) { l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); @@ -153,14 +153,14 @@ static void check_bus_watcher(void) (int)(G_SCD_BERR_TID(status) >> 6), (int)G_SCD_BERR_RID(status), (int)G_SCD_BERR_DCODE(status)); - } else { - prom_printf("Bus watcher indicates no error\n"); - } -} -#else -extern void check_bus_watcher(void); -#endif - + } else { + prom_printf("Bus watcher indicates no error\n"); + } +} +#else +extern void check_bus_watcher(void); +#endif + asmlinkage void sb1_cache_error(void) { uint64_t cerr_dpa; diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c index 9895e32..59e54f1 100644 --- a/arch/mips/mm/dma-noncoherent.c +++ b/arch/mips/mm/dma-noncoherent.c @@ -162,7 +162,7 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, for (i = 0; i < nents; i++, sg++) { unsigned long addr; - + addr = (unsigned long) page_address(sg->page); if (addr) __dma_sync(addr + sg->offset, sg->length, direction); @@ -230,9 +230,9 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { unsigned long addr; - + BUG_ON(direction == DMA_NONE); - + addr = dma_handle + PAGE_OFFSET; __dma_sync(addr, size, direction); } @@ -282,9 +282,9 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction) { int i; - + BUG_ON(direction == DMA_NONE); - + /* Make sure that gcc doesn't leave the empty loop body. */ for (i = 0; i < nelems; i++, sg++) __dma_sync((unsigned long)page_address(sg->page), diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c index b63e1ca..1b6df71 100644 --- a/arch/mips/mm/pg-sb1.c +++ b/arch/mips/mm/pg-sb1.c @@ -198,7 +198,7 @@ static inline void copy_page_cpu(void *to, void *from) /* * Pad descriptors to cacheline, since each is exclusively owned by a - * particular CPU. + * particular CPU. */ typedef struct dmadscr_s { u64 dscr_a; diff --git a/arch/mips/momentum/jaguar_atx/int-handler.S b/arch/mips/momentum/jaguar_atx/int-handler.S index 43fd5a5..55bc789 100644 --- a/arch/mips/momentum/jaguar_atx/int-handler.S +++ b/arch/mips/momentum/jaguar_atx/int-handler.S @@ -27,11 +27,11 @@ SAVE_ALL CLI .set at - mfc0 t0, CP0_CAUSE + mfc0 t0, CP0_CAUSE mfc0 t2, CP0_STATUS and t0, t2 - + andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ bnez t1, ll_sw0_irq andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ @@ -103,25 +103,25 @@ ll_pcia_irq: move a1, sp jal do_IRQ j ret_from_irq - + ll_pcib_irq: li a0, 5 move a1, sp jal do_IRQ j ret_from_irq - + ll_uart_irq: li a0, 6 move a1, sp jal do_IRQ j ret_from_irq - + ll_cputimer_irq: li a0, 7 move a1, sp jal ll_timer_interrupt j ret_from_irq - + ll_mv64340_decode_irq: move a0, sp jal ll_mv64340_irq diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c index 8279608..14ae2e7 100644 --- a/arch/mips/momentum/jaguar_atx/prom.c +++ b/arch/mips/momentum/jaguar_atx/prom.c @@ -64,7 +64,7 @@ static u8 exchange_bit(u8 val, u8 cs) /* turn the clock off and read-strobe */ JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); - + /* return the data */ return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); } diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c index 3cf1e46..90288cf 100644 --- a/arch/mips/momentum/jaguar_atx/setup.c +++ b/arch/mips/momentum/jaguar_atx/setup.c @@ -451,7 +451,7 @@ static int __init momenco_jaguar_atx_setup(void) #ifdef GEMDEBUG_TRACEBUFFER { unsigned int tbControl; - tbControl = + tbControl = 0 << 26 | /* post trigger delay 0 */ 0x2 << 16 | /* sequential trace mode */ // 0x0 << 16 | /* non-sequential trace mode */ diff --git a/arch/mips/momentum/ocelot_c/int-handler.S b/arch/mips/momentum/ocelot_c/int-handler.S index 2f24306..52349d9 100644 --- a/arch/mips/momentum/ocelot_c/int-handler.S +++ b/arch/mips/momentum/ocelot_c/int-handler.S @@ -27,11 +27,11 @@ SAVE_ALL CLI .set at - mfc0 t0, CP0_CAUSE + mfc0 t0, CP0_CAUSE mfc0 t2, CP0_STATUS and t0, t2 - + andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ bnez t1, ll_sw0_irq andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ @@ -83,7 +83,7 @@ ll_pmc_irq: move a1, sp jal do_IRQ j ret_from_irq - + ll_cpci_decode_irq: move a0, sp jal ll_cpci_irq @@ -99,4 +99,4 @@ ll_cputimer_irq: move a1, sp jal do_IRQ j ret_from_irq - + diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c index 375877a..5b68097 100644 --- a/arch/mips/momentum/ocelot_c/prom.c +++ b/arch/mips/momentum/ocelot_c/prom.c @@ -67,7 +67,7 @@ static u8 exchange_bit(u8 val, u8 cs) /* turn the clock off and read-strobe */ OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); - + /* return the data */ return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); } diff --git a/arch/mips/pci/fixup-ddb5074.c b/arch/mips/pci/fixup-ddb5074.c index b345e52..5a4a7c2 100644 --- a/arch/mips/pci/fixup-ddb5074.c +++ b/arch/mips/pci/fixup-ddb5074.c @@ -5,7 +5,7 @@ static void ddb5074_fixup(struct pci_dev *dev) { extern struct pci_dev *pci_pmu; u8 t8; - + pci_pmu = dev; /* for LEDs D2 and D3 */ /* Program the lines for LEDs D2 and D3 to output */ pci_read_config_byte(dev, 0x7d, &t8); diff --git a/arch/mips/pci/fixup-ddb5477.c b/arch/mips/pci/fixup-ddb5477.c index 6abdc88..2f1444e 100644 --- a/arch/mips/pci/fixup-ddb5477.c +++ b/arch/mips/pci/fixup-ddb5477.c @@ -65,7 +65,7 @@ static void ddb5477_amd_lance_fixup(struct pci_dev *dev) ioaddr = pci_resource_start(dev, 0); inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */ - + /* bcr_18 |= 0x0800 */ outw(18, ioaddr + PCNET32_WIO_RAP); temp = inw(ioaddr + PCNET32_WIO_BDP); diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c index b9296d9..bf2c41d 100644 --- a/arch/mips/pci/fixup-malta.c +++ b/arch/mips/pci/fixup-malta.c @@ -56,7 +56,7 @@ static void __init malta_piix_func0_fixup(struct pci_dev *pdev) 0, 0, 0, 3, 4, 5, 6, 7, 0, 9, 10, 11, - 12, 0, 14, 15 + 12, 0, 14, 15 }; int i; diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index de4e443..ceeb186 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -7,7 +7,7 @@ * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * - * Copyright (C) 2000-2001 Toshiba Corporation + * Copyright (C) 2000-2001 Toshiba Corporation * * Copyright (C) 2004 MontaVista Software Inc. * Author: Manish Lachwani (mlachwani@mvista.com) diff --git a/arch/mips/pci/fixup-sni.c b/arch/mips/pci/fixup-sni.c index c8ef01a..a176f2c 100644 --- a/arch/mips/pci/fixup-sni.c +++ b/arch/mips/pci/fixup-sni.c @@ -32,7 +32,7 @@ * Device 4: Unused * Device 5: Slot 2 * Device 6: Slot 3 - * Device 7: Slot 4 + * Device 7: Slot 4 * * Documentation says the VGA is device 5 and device 3 is unused but that * seem to be a documentation error. At least on my RM200C the Cirrus diff --git a/arch/mips/pci/ops-ddb5477.c b/arch/mips/pci/ops-ddb5477.c index e955443..0406b50 100644 --- a/arch/mips/pci/ops-ddb5477.c +++ b/arch/mips/pci/ops-ddb5477.c @@ -127,7 +127,7 @@ static inline void ddb_close_config_base(struct pci_config_swap *swap) } static int read_config_dword(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, + struct pci_bus *bus, u32 devfn, u32 where, u32 * val) { u32 bus_num, slot_num, func_num; @@ -153,7 +153,7 @@ static int read_config_dword(struct pci_config_swap *swap, } static int read_config_word(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, + struct pci_bus *bus, u32 devfn, u32 where, u16 * val) { int status; diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 2a9d722..7688b77 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -1,16 +1,16 @@ /* * Copyright 2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. - * ahennessy@mvista.com + * ahennessy@mvista.com * - * Copyright (C) 2000-2001 Toshiba Corporation + * Copyright (C) 2000-2001 Toshiba Corporation * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) * * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c * * Define the pci_ops for the Toshiba rbtx4927 * - * Much of the code is derived from the original DDB5074 port by + * Much of the code is derived from the original DDB5074 port by * Geert Uytterhoeven <geert@sonycom.com> * * Copyright 2004 MontaVista Software Inc. diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c index 4ddd53e..826d653 100644 --- a/arch/mips/pci/pci-ddb5477.c +++ b/arch/mips/pci/pci-ddb5477.c @@ -76,7 +76,7 @@ struct pci_controller ddb5477_io_controller = { */ /* - * irq mapping : device -> pci int # -> vrc4377 irq# , + * irq mapping : device -> pci int # -> vrc4377 irq# , * ddb5477 board manual page 4 and vrc5477 manual page 46 */ @@ -137,9 +137,9 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) unsigned char *slot_irq_map; unsigned char irq; - /* + /* * We ignore the swizzled slot and pin values. The original - * pci_fixup_irq() codes largely base irq number on the dev slot + * pci_fixup_irq() codes largely base irq number on the dev slot * numbers because except for one case they are unique even * though there are multiple pci buses. */ @@ -160,7 +160,7 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if (mips_machtype == MACH_NEC_ROCKHOPPERII) { /* hack to distinquish overlapping slot 20s, one - * on bus 0 (ALI USB on the M1535 on the backplane), + * on bus 0 (ALI USB on the M1535 on the backplane), * and one on bus 2 (NEC USB controller on the CPU board) * Make the M1535 USB - ISA IRQ number 9. */ diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 8141dff..8a5b522 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -132,7 +132,7 @@ static int __init pcibios_init(void) hose->need_domain_info = need_domain_info; next_busno = bus->subordinate + 1; /* Don't allow 8-bit bus number overflow inside the hose - - reserve some space for bridges. */ + reserve some space for bridges. */ if (next_busno > 224) { next_busno = 0; need_domain_info = 1; @@ -260,7 +260,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { pci_read_bridge_bases(bus); pcibios_fixup_device_resources(dev, bus); - } + } for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { struct pci_dev *dev = pci_dev_b(ln); diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c index b067988..97862f4 100644 --- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c +++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c @@ -30,7 +30,7 @@ * * This code reads the ATMEL 24CXX EEPROM. The PMC-Sierra Yosemite board uses the ATMEL * 24C32/24C64 which uses two byte addressing as compared to 24C16. Note that this program - * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are + * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are * expected to have a connectivity from the EEPROM to the serial port. This program does * __not__ communicate using the I2C protocol */ @@ -64,14 +64,14 @@ static void send_ack(void) static void send_byte(unsigned char byte) { int i = 0; - - for (i = 7; i >= 0; i--) + + for (i = 7; i >= 0; i--) send_bit((byte >> i) & 0x01); } - + static void send_start(void) { - sda_hi; + sda_hi; delay(TXX); scl_hi; delay(TXX); @@ -114,9 +114,9 @@ static unsigned char recv_byte(void) { int i; unsigned char byte=0; - for (i=7;i>=0;i--) + for (i=7;i>=0;i--) byte |= (recv_bit() << i); - + return byte; } diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h index d27566d..c19f01a 100644 --- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h +++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h @@ -27,7 +27,7 @@ */ /* - * Header file for atmel_read_eeprom.c + * Header file for atmel_read_eeprom.c */ #include <linux/types.h> @@ -46,7 +46,7 @@ #define DEFAULT_PORT "/dev/ttyS0" /* Port to open */ #define TXX 0 /* Dummy loop for spinning */ -#define BLOCK_SEL 0x00 +#define BLOCK_SEL 0x00 #define SLAVE_ADDR 0xa0 #define READ_BIT 0x01 #define WRITE_BIT 0x00 diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c index 0ab4abf..fa0e719 100644 --- a/arch/mips/sgi-ip22/ip22-eisa.c +++ b/arch/mips/sgi-ip22/ip22-eisa.c @@ -242,7 +242,7 @@ int __init ip22_eisa_init(void) int i, c; char *str; u8 *slot_addr; - + if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) { printk(KERN_INFO "EISA: bus not present.\n"); return 1; diff --git a/arch/mips/sgi-ip22/ip22-hpc.c b/arch/mips/sgi-ip22/ip22-hpc.c index c0afecc..5c00cdd 100644 --- a/arch/mips/sgi-ip22/ip22-hpc.c +++ b/arch/mips/sgi-ip22/ip22-hpc.c @@ -49,7 +49,7 @@ void __init sgihpc_init(void) sgint = &sgioc->int3; system_type = "SGI Indy"; } - + sgi_ioc_reset = (SGIOC_RESET_PPORT | SGIOC_RESET_KBDMOUSE | SGIOC_RESET_EISA | SGIOC_RESET_ISDN | SGIOC_RESET_LC0OFF); diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index ea2844d..d16fb43 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -28,7 +28,7 @@ /* #define DEBUG_SGINT */ /* So far nothing hangs here */ -#undef USE_LIO3_IRQ +#undef USE_LIO3_IRQ struct sgint_regs *sgint; @@ -272,32 +272,32 @@ void indy_buserror_irq(struct pt_regs *regs) irq_exit(); } -static struct irqaction local0_cascade = { +static struct irqaction local0_cascade = { .handler = no_action, .flags = SA_INTERRUPT, .name = "local0 cascade", }; -static struct irqaction local1_cascade = { +static struct irqaction local1_cascade = { .handler = no_action, .flags = SA_INTERRUPT, .name = "local1 cascade", }; -static struct irqaction buserr = { +static struct irqaction buserr = { .handler = no_action, .flags = SA_INTERRUPT, .name = "Bus Error", }; -static struct irqaction map0_cascade = { +static struct irqaction map0_cascade = { .handler = no_action, .flags = SA_INTERRUPT, .name = "mapable0 cascade", }; #ifdef USE_LIO3_IRQ -static struct irqaction map1_cascade = { +static struct irqaction map1_cascade = { .handler = no_action, .flags = SA_INTERRUPT, .name = "mapable1 cascade", diff --git a/arch/mips/sgi-ip22/ip22-nvram.c b/arch/mips/sgi-ip22/ip22-nvram.c index de43e86..fd29fd4 100644 --- a/arch/mips/sgi-ip22/ip22-nvram.c +++ b/arch/mips/sgi-ip22/ip22-nvram.c @@ -39,7 +39,7 @@ *ptr |= EEPROM_CSEL; \ *ptr |= EEPROM_ECLK; }) - + #define eeprom_cs_off(ptr) ({ \ *ptr &= ~EEPROM_ECLK; \ *ptr &= ~EEPROM_CSEL; \ @@ -50,7 +50,7 @@ /* * clock in the nvram command and the register number. For the * national semiconductor nv ram chip the op code is 3 bits and - * the address is 6/8 bits. + * the address is 6/8 bits. */ static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd, unsigned reg) @@ -90,7 +90,7 @@ unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg) if (*ctrl & EEPROM_DATI) res |= 1; } - + eeprom_cs_off(ctrl); return res; @@ -113,7 +113,7 @@ unsigned short ip22_nvram_read(int reg) reg <<= 1; tmp = hpc3c0->bbram[reg++] & 0xff; return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff); - } + } } EXPORT_SYMBOL(ip22_nvram_read); diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c index ed5c60a..214ffd2 100644 --- a/arch/mips/sgi-ip22/ip22-reset.c +++ b/arch/mips/sgi-ip22/ip22-reset.c @@ -185,7 +185,7 @@ static irqreturn_t panel_int(int irq, void *dev_id, struct pt_regs *regs) add_timer(&debounce_timer); } - /* Power button was pressed + /* Power button was pressed * ioc.ps page 22: "The Panel Register is called Power Control by Full * House. Only lowest 2 bits are used. Guiness uses upper four bits * for volume control". This is not true, all bits are pulled high diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index 173f768..df9b569 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -126,7 +126,7 @@ static __init void indy_time_init(void) unsigned long r4k_ticks[3]; unsigned long r4k_tick; - /* + /* * Figure out the r4k offset, the algorithm is very simple and works in * _all_ cases as long as the 8254 counter register itself works ok (as * an interrupt driving timer it does not because of bug, this is why diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c index a160d04..ef20d9a 100644 --- a/arch/mips/sgi-ip27/ip27-memory.c +++ b/arch/mips/sgi-ip27/ip27-memory.c @@ -538,7 +538,7 @@ void __init mem_init(void) for_each_online_node(node) { unsigned slot, numslots; struct page *end, *p; - + /* * This will free up the bootmem, ie, slot 0 memory. */ diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c index 281f090..88e1f52 100644 --- a/arch/mips/sgi-ip32/ip32-reset.c +++ b/arch/mips/sgi-ip32/ip32-reset.c @@ -140,7 +140,7 @@ static irqreturn_t ip32_rtc_int(int irq, void *dev_id, struct pt_regs *regs) reg_c = CMOS_READ(RTC_INTR_FLAGS); if (!(reg_c & RTC_IRQF)) { - printk(KERN_WARNING + printk(KERN_WARNING "%s: RTC IRQ without RTC_IRQF\n", __FUNCTION__); } /* Wait until interrupt goes away */ diff --git a/arch/mips/sibyte/cfe/cfe_error.h b/arch/mips/sibyte/cfe/cfe_error.h index 77eb493..975f000 100644 --- a/arch/mips/sibyte/cfe/cfe_error.h +++ b/arch/mips/sibyte/cfe/cfe_error.h @@ -17,15 +17,15 @@ */ /* ********************************************************************* - * + * * Broadcom Common Firmware Environment (CFE) - * + * * Error codes File: cfe_error.h - * + * * CFE's global error code list is here. - * + * * Author: Mitch Lichtenberg - * + * ********************************************************************* */ diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c index 53a5c1e..7721100 100644 --- a/arch/mips/sibyte/cfe/console.c +++ b/arch/mips/sibyte/cfe/console.c @@ -38,7 +38,7 @@ static void cfe_console_write(struct console *cons, const char *str, last += written; } while (last < count); } - + } static int cfe_console_setup(struct console *cons, char *str) diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c index d86943f..7a2c7a8 100644 --- a/arch/mips/sibyte/cfe/setup.c +++ b/arch/mips/sibyte/cfe/setup.c @@ -285,7 +285,7 @@ void __init prom_init(void) while (1) ; } cfe_init(cfe_handle, cfe_ept); - /* + /* * Get the handle for (at least) prom_putchar, possibly for * boot console */ diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c index 7339219..e44ce1a 100644 --- a/arch/mips/sibyte/cfe/smp.c +++ b/arch/mips/sibyte/cfe/smp.c @@ -57,7 +57,7 @@ void __init prom_prepare_cpus(unsigned int max_cpus) void prom_boot_secondary(int cpu, struct task_struct *idle) { int retval; - + retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, __KSTK_TOS(idle), (unsigned long)idle->thread_info, 0); diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c index 182a16f..1a97e31 100644 --- a/arch/mips/sibyte/sb1250/bus_watcher.c +++ b/arch/mips/sibyte/sb1250/bus_watcher.c @@ -10,13 +10,13 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* +/* * The Bus Watcher monitors internal bus transactions and maintains * counts of transactions with error status, logging details and * causing one of several interrupts. This driver provides a handler @@ -155,7 +155,7 @@ static int bw_read_proc(char *page, char **start, off_t off, static void create_proc_decoder(struct bw_stats_struct *stats) { struct proc_dir_entry *ent; - + ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL, bw_read_proc, stats); if (!ent) { diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 2728abb..2725b26 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -377,7 +377,7 @@ void __init arch_init_irq(void) /* * Note that the timer interrupts are also mapped, but this is - * done in sb1250_time_init(). Also, the profiling driver + * done in sb1250_time_init(). Also, the profiling driver * does its own management of IP7. */ @@ -392,7 +392,7 @@ void __init arch_init_irq(void) if (kgdb_flag) { kgdb_irq = K_INT_UART_0 + kgdb_port; -#ifdef CONFIG_SIBYTE_SB1250_DUART +#ifdef CONFIG_SIBYTE_SB1250_DUART sb1250_duart_present[kgdb_port] = 0; #endif /* Setup uart 1 settings, mapper */ diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c index 0e633ee..a686bb7 100644 --- a/arch/mips/sibyte/swarm/rtc_m41t81.c +++ b/arch/mips/sibyte/swarm/rtc_m41t81.c @@ -128,7 +128,7 @@ static int m41t81_write(uint8_t addr, int b) /* Clear error bit by writing a 1 */ bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; - } + } /* read the same byte again to make sure it is written */ bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, @@ -136,7 +136,7 @@ static int m41t81_write(uint8_t addr, int b) while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - + return 0; } @@ -148,13 +148,13 @@ int m41t81_set_time(unsigned long t) /* * Note the write order matters as it ensures the correctness. - * When we write sec, 10th sec is clear. It is reasonable to + * When we write sec, 10th sec is clear. It is reasonable to * believe we should finish writing min within a second. */ tm.tm_sec = BIN2BCD(tm.tm_sec); m41t81_write(M41T81REG_SC, tm.tm_sec); - + tm.tm_min = BIN2BCD(tm.tm_min); m41t81_write(M41T81REG_MN, tm.tm_min); @@ -187,7 +187,7 @@ unsigned long m41t81_get_time(void) { unsigned int year, mon, day, hour, min, sec; - /* + /* * min is valid if two reads of sec are the same. */ for (;;) { diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 4742e4f..4daeaa4 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -98,7 +98,7 @@ static int __init swarm_setup(void) rtc_get_time = xicor_get_time; rtc_set_time = xicor_set_time; } - + if (m41t81_probe()) { printk("swarm setup: M41T81 RTC detected.\n"); rtc_get_time = m41t81_get_time; diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c index 62c760f..141a310 100644 --- a/arch/mips/sni/irq.c +++ b/arch/mips/sni/irq.c @@ -103,7 +103,7 @@ static unsigned int ls1bit8(unsigned int x) /* * hwint 1 deals with EISA and SCSI interrupts, - * + * * The EISA_INT bit in CSITPEND is high active, all others are low active. */ void pciasic_hwint1(struct pt_regs *regs) diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index 8f67cee..1b3f8a0 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c @@ -111,7 +111,7 @@ static struct resource sni_mem_resource = { * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used * for other purposes. Be paranoid and allocate all of the before the PCI * code gets a chance to to map anything else there ... - * + * * This leaves the following areas available: * * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory diff --git a/arch/mips/tx4927/common/tx4927_irq_handler.S b/arch/mips/tx4927/common/tx4927_irq_handler.S index ca123e2..dd3ceda 100644 --- a/arch/mips/tx4927/common/tx4927_irq_handler.S +++ b/arch/mips/tx4927/common/tx4927_irq_handler.S @@ -42,13 +42,13 @@ CLI .set at - mfc0 t0, CP0_CAUSE + mfc0 t0, CP0_CAUSE mfc0 t1, CP0_STATUS and t0, t1 - + andi t1, t0, STATUSF_IP7 /* cpu timer */ bnez t1, ll_ip7 - + /* IP6..IP3 multiplexed -- do not use */ andi t1, t0, STATUSF_IP2 /* tx4927 pic */ diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c index 16bcbdc..26d7c53 100644 --- a/arch/mips/tx4927/common/tx4927_setup.c +++ b/arch/mips/tx4927/common/tx4927_setup.c @@ -152,7 +152,7 @@ dump_cp0(char *key) print_cp0(key, 16, "CONFIG ", read_c0_config()); return; } - + void print_pic(char *key, u32 reg, char *name) { printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name, diff --git a/arch/mips/tx4927/toshiba_rbtx4927/Makefile b/arch/mips/tx4927/toshiba_rbtx4927/Makefile index 86ca4cf..c1a377a 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/Makefile +++ b/arch/mips/tx4927/toshiba_rbtx4927/Makefile @@ -1,5 +1,5 @@ -obj-y += toshiba_rbtx4927_prom.o -obj-y += toshiba_rbtx4927_setup.o -obj-y += toshiba_rbtx4927_irq.o +obj-y += toshiba_rbtx4927_prom.o +obj-y += toshiba_rbtx4927_setup.o +obj-y += toshiba_rbtx4927_irq.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index fd5b433..aee07ff 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -31,7 +31,7 @@ /* -IRQ Device +IRQ Device 00 RBTX4927-ISA/00 01 RBTX4927-ISA/01 PS2/Keyboard 02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) @@ -52,15 +52,15 @@ IRQ Device 16 TX4927-CP0/00 Software 0 17 TX4927-CP0/01 Software 1 18 TX4927-CP0/02 Cascade TX4927-CP0 -19 TX4927-CP0/03 Multiplexed -- do not use -20 TX4927-CP0/04 Multiplexed -- do not use -21 TX4927-CP0/05 Multiplexed -- do not use -22 TX4927-CP0/06 Multiplexed -- do not use +19 TX4927-CP0/03 Multiplexed -- do not use +20 TX4927-CP0/04 Multiplexed -- do not use +21 TX4927-CP0/05 Multiplexed -- do not use +22 TX4927-CP0/06 Multiplexed -- do not use 23 TX4927-CP0/07 CPU TIMER 24 TX4927-PIC/00 25 TX4927-PIC/01 -26 TX4927-PIC/02 +26 TX4927-PIC/02 27 TX4927-PIC/03 Cascade RBTX4927-IOC 28 TX4927-PIC/04 29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet @@ -80,7 +80,7 @@ IRQ Device 43 TX4927-PIC/19 44 TX4927-PIC/20 45 TX4927-PIC/21 -46 TX4927-PIC/22 TX4927 PCI PCI-ERR +46 TX4927-PIC/22 TX4927 PCI PCI-ERR 47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) 48 TX4927-PIC/24 49 TX4927-PIC/25 @@ -100,7 +100,7 @@ IRQ Device 62 RBTX4927-IOC/06 63 RBTX4927-IOC/07 -NOTES: +NOTES: SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 SouthBridge/ISA/pin=0 no pci irq used by this device SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 @@ -175,19 +175,19 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB static const u32 toshiba_rbtx4927_irq_debug_flag = (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR -// | TOSHIBA_RBTX4927_IRQ_IOC_INIT -// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP -// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN -// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE -// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE -// | TOSHIBA_RBTX4927_IRQ_IOC_MASK -// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ -// | TOSHIBA_RBTX4927_IRQ_ISA_INIT -// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP -// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN -// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE -// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE -// | TOSHIBA_RBTX4927_IRQ_ISA_MASK +// | TOSHIBA_RBTX4927_IRQ_IOC_INIT +// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP +// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN +// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE +// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE +// | TOSHIBA_RBTX4927_IRQ_IOC_MASK +// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ +// | TOSHIBA_RBTX4927_IRQ_ISA_INIT +// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP +// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN +// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE +// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE +// | TOSHIBA_RBTX4927_IRQ_ISA_MASK // | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ ); #endif diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index 8724ea3..fc07205 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -395,7 +395,7 @@ static int __init tx4927_pcibios_init(void) /* enable secondary ide */ v08_43 |= 0x80; - /* + /* * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! * * This line of code is intended to provide the user with a work diff --git a/arch/mips/vr41xx/common/vrc4173.c b/arch/mips/vr41xx/common/vrc4173.c index 5475dd7..ba58764 100644 --- a/arch/mips/vr41xx/common/vrc4173.c +++ b/arch/mips/vr41xx/common/vrc4173.c @@ -476,7 +476,7 @@ static inline int vrc4173_icu_init(int cascade_irq) if (cascade_irq < GIU_IRQ(0) || cascade_irq > GIU_IRQ(15)) return -EINVAL; - + vrc4173_outw(0, VRC4173_MSYSINT1REG); vr41xx_set_irq_trigger(GIU_IRQ_TO_PIN(cascade_irq), TRIGGER_LEVEL, SIGNAL_THROUGH); diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h index 40ceedc..30b18ea 100644 --- a/include/asm-mips/asmmacro.h +++ b/include/asm-mips/asmmacro.h @@ -7,10 +7,10 @@ */ #ifndef _ASM_ASMMACRO_H #define _ASM_ASMMACRO_H - + #include <linux/config.h> #include <asm/hazards.h> - + #ifdef CONFIG_32BIT #include <asm/asmmacro-32.h> #endif diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index bc136dc..eb8d79d 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -20,13 +20,13 @@ #define SZLONG_MASK 31UL #define __LL "ll " #define __SC "sc " -#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) +#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) #elif (_MIPS_SZLONG == 64) #define SZLONG_LOG 6 #define SZLONG_MASK 63UL #define __LL "lld " #define __SC "scd " -#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) +#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) #endif #ifdef __KERNEL__ diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h index ae3e2a3..a438548 100644 --- a/include/asm-mips/ddb5xxx/ddb5477.h +++ b/include/asm-mips/ddb5xxx/ddb5477.h @@ -247,7 +247,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); * All PCI irq but INTC are active low. */ -/* +/* * irq number block assignment */ @@ -285,7 +285,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); #define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */ #define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */ #define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */ -#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE) +#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE) #define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */ #define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */ #define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */ @@ -301,7 +301,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); /* * i2859 irq assignment */ -#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE) +#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE) #define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */ #define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE) #define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ diff --git a/include/asm-mips/fpregdef.h b/include/asm-mips/fpregdef.h index 1d9aa09..2b5fddc 100644 --- a/include/asm-mips/fpregdef.h +++ b/include/asm-mips/fpregdef.h @@ -13,7 +13,7 @@ #define _ASM_FPREGDEF_H #include <asm/sgidefs.h> - + #if _MIPS_SIM == _MIPS_SIM_ABI32 /* @@ -56,7 +56,7 @@ #define fcr31 $31 /* FPU status register */ #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - + #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 #define fv0 $f0 /* return value */ diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 6cb38d5..ea24e73 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -82,7 +82,7 @@ do { \ static inline int is_fpu_owner(void) { - return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); + return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); } static inline void own_fpu(void) @@ -90,7 +90,7 @@ static inline void own_fpu(void) if (cpu_has_fpu) { __enable_fpu(); KSTK_STATUS(current) |= ST0_CU1; - set_thread_flag(TIF_USEDFPU); + set_thread_flag(TIF_USEDFPU); } } @@ -98,7 +98,7 @@ static inline void lose_fpu(void) { if (cpu_has_fpu) { KSTK_STATUS(current) &= ~ST0_CU1; - clear_thread_flag(TIF_USEDFPU); + clear_thread_flag(TIF_USEDFPU); __disable_fpu(); } } @@ -127,7 +127,7 @@ static inline void restore_fp(struct task_struct *tsk) static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) { if (cpu_has_fpu) { - if ((tsk == current) && is_fpu_owner()) + if ((tsk == current) && is_fpu_owner()) _save_fp(current); return tsk->thread.fpu.hard.fpr; } diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h index 2b7b0fd..432011b 100644 --- a/include/asm-mips/ip32/mace.h +++ b/include/asm-mips/ip32/mace.h @@ -94,7 +94,7 @@ struct mace_video { unsigned long xxx; /* later... */ }; -/* +/* * Ethernet interface */ struct mace_ethernet { @@ -129,7 +129,7 @@ struct mace_ethernet { volatile unsigned long rx_fifo; }; -/* +/* * Peripherals */ @@ -251,7 +251,7 @@ struct mace_timers { timer_reg audio_out2; timer_reg video_in1; timer_reg video_in2; - timer_reg video_out; + timer_reg video_out; }; struct mace_perif { @@ -272,7 +272,7 @@ struct mace_perif { }; -/* +/* * ISA peripherals */ diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h index 21d0fb7..9e88c76 100644 --- a/include/asm-mips/lasat/serial.h +++ b/include/asm-mips/lasat/serial.h @@ -1,13 +1,13 @@ #include <asm/lasat/lasat.h> /* Lasat 100 boards serial configuration */ -#define LASAT_BASE_BAUD_100 ( 7372800 / 16 ) +#define LASAT_BASE_BAUD_100 ( 7372800 / 16 ) #define LASAT_UART_REGS_BASE_100 0x1c8b0000 #define LASAT_UART_REGS_SHIFT_100 2 #define LASATINT_UART_100 8 /* * LASAT 200 boards serial configuration */ -#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) +#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) #define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) #define LASAT_UART_REGS_SHIFT_200 3 #define LASATINT_UART_200 13 diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 2b36ea3..148bae2 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -1383,7 +1383,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define PCI_IO_START 0 #define PCI_IO_END 0 #define PCI_MEM_START 0 -#define PCI_MEM_END 0 +#define PCI_MEM_END 0 #define PCI_FIRST_DEVFN 0 #define PCI_LAST_DEVFN 0 #endif diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h index 4691398..efafe65 100644 --- a/include/asm-mips/mach-db1x00/db1x00.h +++ b/include/asm-mips/mach-db1x00/db1x00.h @@ -23,7 +23,7 @@ * * ######################################################################## * - * + * */ #ifndef __ASM_DB1X00_H #define __ASM_DB1X00_H diff --git a/include/asm-mips/mach-jazz/floppy.h b/include/asm-mips/mach-jazz/floppy.h index 8cf0d04..c9dad99 100644 --- a/include/asm-mips/mach-jazz/floppy.h +++ b/include/asm-mips/mach-jazz/floppy.h @@ -92,7 +92,7 @@ static inline int fd_request_irq(void) return request_irq(FLOPPY_IRQ, floppy_interrupt, SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL); } - + static inline void fd_free_irq(void) { free_irq(FLOPPY_IRQ, NULL); diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h index d6c7797..ff6d40c 100644 --- a/include/asm-mips/mach-pb1x00/pb1500.h +++ b/include/asm-mips/mach-pb1x00/pb1500.h @@ -33,11 +33,11 @@ #define PCI_BOARD_REG 0xAE000010 #define PCMCIA_BOARD_REG 0xAE000010 #define PC_DEASSERT_RST 0x80 - #define PC_DRV_EN 0x10 + #define PC_DRV_EN 0x10 #define PB1500_G_CONTROL 0xAE000014 #define PB1500_RST_VDDI 0xAE00001C #define PB1500_LEDS 0xAE000018 - + #define PB1500_HEX_LED 0xAF000004 #define PB1500_HEX_LED_BLANK 0xAF000008 diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index da03a32..5bea49f 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -171,11 +171,11 @@ static inline void blast_dcache16(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.dcache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << + unsigned long ws_end = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_D); } @@ -200,8 +200,8 @@ static inline void blast_dcache16_page_indexed(unsigned long page) current_cpu_data.dcache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_D); } @@ -214,8 +214,8 @@ static inline void blast_icache16(void) current_cpu_data.icache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Invalidate_I); } @@ -239,8 +239,8 @@ static inline void blast_icache16_page_indexed(unsigned long page) current_cpu_data.icache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Invalidate_I); } @@ -249,11 +249,11 @@ static inline void blast_scache16(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << + unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -278,8 +278,8 @@ static inline void blast_scache16_page_indexed(unsigned long page) current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -318,8 +318,8 @@ static inline void blast_dcache32(void) current_cpu_data.dcache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_D); } @@ -343,8 +343,8 @@ static inline void blast_dcache32_page_indexed(unsigned long page) current_cpu_data.dcache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_D); } @@ -357,8 +357,8 @@ static inline void blast_icache32(void) current_cpu_data.icache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Invalidate_I); } @@ -383,7 +383,7 @@ static inline void blast_icache32_page_indexed(unsigned long page) unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Invalidate_I); } @@ -392,11 +392,11 @@ static inline void blast_scache32(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << + unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -421,8 +421,8 @@ static inline void blast_scache32_page_indexed(unsigned long page) current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -461,8 +461,8 @@ static inline void blast_icache64(void) current_cpu_data.icache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Invalidate_I); } @@ -487,7 +487,7 @@ static inline void blast_icache64_page_indexed(unsigned long page) unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) + for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Invalidate_I); } @@ -496,11 +496,11 @@ static inline void blast_scache64(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << + unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -525,8 +525,8 @@ static inline void blast_scache64_page_indexed(unsigned long page) current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -561,11 +561,11 @@ static inline void blast_scache128(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << + unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x1000) cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -590,8 +590,8 @@ static inline void blast_scache128_page_indexed(unsigned long page) current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x1000) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x1000) cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); } diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h index 31c0c23..3c4b637 100644 --- a/include/asm-mips/rtc.h +++ b/include/asm-mips/rtc.h @@ -1,5 +1,5 @@ /* - * include/asm-mips/rtc.h + * include/asm-mips/rtc.h * * (Really an interface for drivers/char/genrtc.c) * diff --git a/include/asm-mips/sgi/gio.h b/include/asm-mips/sgi/gio.h index a38d66f..889cf02 100644 --- a/include/asm-mips/sgi/gio.h +++ b/include/asm-mips/sgi/gio.h @@ -16,7 +16,7 @@ * * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have * three physical connectors, but only two slots, GFX and EXP0. - * + * * There is 10MB of GIO address space for GIO64 slot devices * slot# slot type address range size * ----- --------- ----------------------- ----- diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h index a5b988d..ac3dfc7 100644 --- a/include/asm-mips/sgi/hpc3.h +++ b/include/asm-mips/sgi/hpc3.h @@ -221,7 +221,7 @@ struct hpc3_regs { #define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */ u32 _unused1[0x14000/4 - 5]; /* padding */ - + /* Now direct PIO per-HPC3 peripheral access to external regs. */ volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */ u32 _unused2[0x7c00/4]; @@ -304,7 +304,7 @@ struct hpc3_regs { volatile u32 bbram[8192-50-14]; /* Battery backed ram */ }; -/* +/* * It is possible to have two HPC3's within the address space on * one machine, though only having one is more likely on an Indy. */ diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h index 169187f..f3e3dc9 100644 --- a/include/asm-mips/sgi/ioc.h +++ b/include/asm-mips/sgi/ioc.h @@ -16,7 +16,7 @@ #include <linux/types.h> #include <asm/sgi/pi1.h> -/* +/* * All registers are 8-bit wide alligned on 32-bit boundary. Bad things * happen if you try word access them. You have been warned. */ @@ -138,7 +138,7 @@ struct sgioc_regs { u8 _sysid[3]; volatile u8 sysid; #define SGIOC_SYSID_FULLHOUSE 0x01 -#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) +#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) #define SGIOC_SYSID_CHIPREV(x) ((x & 0x1e) > 1) u32 _unused2; u8 _read[3]; diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h index 97d73ad..bbfc05c 100644 --- a/include/asm-mips/sgi/ip22.h +++ b/include/asm-mips/sgi/ip22.h @@ -12,7 +12,7 @@ #ifndef _SGI_IP22_H #define _SGI_IP22_H -/* +/* * These are the virtual IRQ numbers, we divide all IRQ's into * 'spaces', the 'space' determines where and how to enable/disable * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups diff --git a/include/asm-mips/sgi/mc.h b/include/asm-mips/sgi/mc.h index fd98f93..c52f783 100644 --- a/include/asm-mips/sgi/mc.h +++ b/include/asm-mips/sgi/mc.h @@ -182,14 +182,14 @@ struct sgimc_regs { volatile u32 dtlb_hi3; u32 _unused33; volatile u32 dtlb_lo3; - + u32 _unused34[0x0392]; - + u32 _unused35; volatile u32 rpsscounter; /* Chirps at 100ns */ u32 _unused36[0x1000/4-2*4]; - + u32 _unused37; volatile u32 maddronly; /* Address DMA goes at */ u32 _unused38; diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h index 7ac5da1..b5e7dae 100644 --- a/include/asm-mips/sibyte/carmel.h +++ b/include/asm-mips/sibyte/carmel.h @@ -25,12 +25,12 @@ #define SIBYTE_BOARD_NAME "Carmel" -#define GPIO_PHY_INTERRUPT 2 -#define GPIO_NONMASKABLE_INT 3 -#define GPIO_CF_INSERTED 6 -#define GPIO_MONTEREY_RESET 7 -#define GPIO_QUADUART_INT 8 -#define GPIO_CF_INT 9 +#define GPIO_PHY_INTERRUPT 2 +#define GPIO_NONMASKABLE_INT 3 +#define GPIO_CF_INSERTED 6 +#define GPIO_MONTEREY_RESET 7 +#define GPIO_QUADUART_INT 8 +#define GPIO_CF_INT 9 #define GPIO_FPGA_CCLK 10 #define GPIO_FPGA_DOUT 11 #define GPIO_FPGA_DIN 12 diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h index 96088fb..40ef97c 100644 --- a/include/asm-mips/sibyte/sb1250_defs.h +++ b/include/asm-mips/sibyte/sb1250_defs.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * - * Global constants and macros File: sb1250_defs.h - * + * + * Global constants and macros File: sb1250_defs.h + * * This file contains macros and definitions used by the other * include files. * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -105,7 +105,7 @@ #define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00 #define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100 -/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ +/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ #define SIBYTE_HDR_FMASK(chip, pass) \ (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass) #define SIBYTE_HDR_FMASK_ALLREVS(chip) \ @@ -150,31 +150,31 @@ /* ********************************************************************* * Naming schemes for constants in these files: - * - * M_xxx MASK constant (identifies bits in a register). + * + * M_xxx MASK constant (identifies bits in a register). * For multi-bit fields, all bits in the field will * be set. * * K_xxx "Code" constant (value for data in a multi-bit * field). The value is right justified. * - * V_xxx "Value" constant. This is the same as the + * V_xxx "Value" constant. This is the same as the * corresponding "K_xxx" constant, except it is * shifted to the correct position in the register. * * S_xxx SHIFT constant. This is the number of bits that - * a field value (code) needs to be shifted + * a field value (code) needs to be shifted * (towards the left) to put the value in the right * position for the register. * - * A_xxx ADDRESS constant. This will be a physical + * A_xxx ADDRESS constant. This will be a physical * address. Use the PHYS_TO_K1 macro to generate * a K1SEG address. * * R_xxx RELATIVE offset constant. This is an offset from * an A_xxx constant (usually the first register in * a group). - * + * * G_xxx(X) GET value. This macro obtains a multi-bit field * from a register, masks it, and shifts it to * the bottom of the register (retrieving a K_xxx @@ -189,7 +189,7 @@ /* - * Cast to 64-bit number. Presumably the syntax is different in + * Cast to 64-bit number. Presumably the syntax is different in * assembly language. * * Note: you'll need to define uint32_t and uint64_t in your headers. diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h index f1b08d3..3cdb48f 100644 --- a/include/asm-mips/sibyte/sb1250_dma.h +++ b/include/asm-mips/sibyte/sb1250_dma.h @@ -1,24 +1,24 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * DMA definitions File: sb1250_dma.h - * + * * This module contains constants and macros useful for * programming the SB1250's DMA controllers, both the data mover * and the Ethernet DMA. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -28,7 +28,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -43,9 +43,9 @@ * DMA Registers ********************************************************************* */ -/* +/* * Ethernet and Serial DMA Configuration Register 0 (Table 7-4) - * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 + * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 * Registers: DMA_CONFIG0_MAC_x_TX_CH_0 * Registers: DMA_CONFIG0_SER_x_RX * Registers: DMA_CONFIG0_SER_x_TX @@ -98,7 +98,7 @@ /* * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) - * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 + * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 * Registers: DMA_CONFIG1_DMA_x_TX_CH_0 * Registers: DMA_CONFIG1_SER_x_RX * Registers: DMA_CONFIG1_SER_x_TX @@ -152,11 +152,11 @@ /* * DMA Descriptor Count Registers (Table 7-8) */ - + /* No bitfields */ -/* +/* * Current Descriptor Address Register (Table 7-11) */ @@ -275,14 +275,14 @@ #define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS) #define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS) -/* +/* * Ethernet Descriptor Status Bits (Table 7-15) */ #define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) #define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) /* Note: BADTCPCS is actually in DSCR_B options field */ #define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) #endif /* 1250 PASS2 || 112x PASS1 */ @@ -324,7 +324,7 @@ #define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63) -/* +/* * Ethernet Transmit Options (Table 7-17) */ @@ -377,7 +377,7 @@ * Data Mover Registers ********************************************************************* */ -/* +/* * Data Mover Descriptor Base Address Register (Table 7-22) * Register: DM_DSCR_BASE_0 * Register: DM_DSCR_BASE_1 @@ -414,7 +414,7 @@ #define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62) #define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63) -/* +/* * Data Mover Descriptor Count Register (Table 7-25) */ diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h index 0d9dfac..f1f509f 100644 --- a/include/asm-mips/sibyte/sb1250_genbus.h +++ b/include/asm-mips/sibyte/sb1250_genbus.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * Generic Bus Constants File: sb1250_genbus.h - * - * This module contains constants and macros useful for + * + * This module contains constants and macros useful for * manipulating the SB1250's Generic Bus interface - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h index c3f74df..e173e2e 100644 --- a/include/asm-mips/sibyte/sb1250_int.h +++ b/include/asm-mips/sibyte/sb1250_int.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * Interrupt Mapper definitions File: sb1250_int.h - * + * * This module contains constants for manipulating the SB1250's * interrupt mapper and definitions for the interrupt sources. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -43,7 +43,7 @@ /* * Interrupt sources (Table 4-8, UM 0.2) - * + * * First, the interrupt numbers. */ diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h index 799db82..8afe8e0 100644 --- a/include/asm-mips/sibyte/sb1250_l2c.h +++ b/include/asm-mips/sibyte/sb1250_l2c.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * L2 Cache constants and macros File: sb1250_l2c.h - * + * * This module contains constants useful for manipulating the * level 2 cache. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h index d875388..f2617de 100644 --- a/include/asm-mips/sibyte/sb1250_ldt.h +++ b/include/asm-mips/sibyte/sb1250_ldt.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * LDT constants File: sb1250_ldt.h - * - * This module contains constants and macros to describe - * the LDT interface on the SB1250. - * + * + * This module contains constants and macros to describe + * the LDT interface on the SB1250. + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -155,7 +155,7 @@ /* * LDT Status Register (Table 8-14). Note that these constants - * assume you've read the command and status register + * assume you've read the command and status register * together (32-bit read at offset 0x04) * * These bits also apply to the secondary status @@ -183,8 +183,8 @@ #define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31) /* - * Bridge Control Register (Table 8-16). Note that these - * constants assume you've read the register as a 32-bit + * Bridge Control Register (Table 8-16). Note that these + * constants assume you've read the register as a 32-bit * read (offset 0x3C) */ diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h index 81f603f..18e74e4 100644 --- a/include/asm-mips/sibyte/sb1250_mac.h +++ b/include/asm-mips/sibyte/sb1250_mac.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * MAC constants and macros File: sb1250_mac.h - * + * * This module contains constants and macros for the SB1250's * ethernet controllers. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -311,7 +311,7 @@ /* * These constants are used to configure the fields within the Frame - * Configuration Register. + * Configuration Register. */ #define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ @@ -393,7 +393,7 @@ * Register: MAC_INT_MASK_2 */ -/* +/* * Use these constants to shift the appropriate channel * into the CH0 position so the same tests can be used * on each channel. diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h index 93a4833..1dd41c9 100644 --- a/include/asm-mips/sibyte/sb1250_mc.h +++ b/include/asm-mips/sibyte/sb1250_mc.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * - * Memory Controller constants File: sb1250_mc.h - * + * + * Memory Controller constants File: sb1250_mc.h + * * This module contains constants and macros useful for * programming the memory controller. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -166,7 +166,7 @@ #define K_MC_REF_RATE_100MHz 0x62 #define K_MC_REF_RATE_133MHz 0x81 -#define K_MC_REF_RATE_200MHz 0xC4 +#define K_MC_REF_RATE_200MHz 0xC4 #define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) #define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) @@ -228,7 +228,7 @@ V_MC_ADDR_DRIVE_DEFAULT | \ V_MC_DATA_DRIVE_DEFAULT | \ V_MC_CLOCK_DRIVE_DEFAULT | \ - V_MC_REF_RATE_DEFAULT + V_MC_REF_RATE_DEFAULT diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h index 5d496c6..9db80cd 100644 --- a/include/asm-mips/sibyte/sb1250_regs.h +++ b/include/asm-mips/sibyte/sb1250_regs.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * Register Definitions File: sb1250_regs.h - * + * * This module contains the addresses of the on-chip peripherals * on the SB1250. - * + * * SB1250 specification level: 01/02/2002 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -40,20 +40,20 @@ /* ********************************************************************* * Some general notes: - * + * * For the most part, when there is more than one peripheral * of the same type on the SOC, the constants below will be * offsets from the base of each peripheral. For example, * the MAC registers are described as offsets from the first * MAC register, and there will be a MAC_REGISTER() macro - * to calculate the base address of a given MAC. - * + * to calculate the base address of a given MAC. + * * The information in this file is based on the SB1250 SOC * manual version 0.2, July 2000. ********************************************************************* */ -/* ********************************************************************* +/* ********************************************************************* * Memory Controller Registers ********************************************************************* */ @@ -101,7 +101,7 @@ #define R_MC_TEST_ECC 0x0000000420 #define R_MC_MCLK_CFG 0x0000000500 -/* ********************************************************************* +/* ********************************************************************* * L2 Cache Control Registers ********************************************************************* */ @@ -126,7 +126,7 @@ #define A_L2_EEC_ADDRESS A_L2_ECC_TAG -/* ********************************************************************* +/* ********************************************************************* * PCI Interface Registers ********************************************************************* */ @@ -134,7 +134,7 @@ #define A_PCI_TYPE01_HEADER 0x00DE000800 -/* ********************************************************************* +/* ********************************************************************* * Ethernet DMA and MACs ********************************************************************* */ @@ -184,7 +184,7 @@ (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ (reg)) -/* +/* * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE */ @@ -259,7 +259,7 @@ #define MAC_CHMAP_COUNT 4 -/* ********************************************************************* +/* ********************************************************************* * DUART Registers ********************************************************************* */ @@ -363,7 +363,7 @@ #endif /* 1250 PASS2 || 112x PASS1 */ -/* ********************************************************************* +/* ********************************************************************* * Synchronous Serial Registers ********************************************************************* */ @@ -397,7 +397,7 @@ (reg)) -/* +/* * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE */ @@ -457,7 +457,7 @@ #define R_SER_RMON_RX_ERRORS 0x000001F0 #define R_SER_RMON_RX_BADADDR 0x000001F8 -/* ********************************************************************* +/* ********************************************************************* * Generic Bus Registers ********************************************************************* */ @@ -513,7 +513,7 @@ #define R_IO_PCMCIA_CFG 0x0A60 #define R_IO_PCMCIA_STATUS 0x0A70 -/* ********************************************************************* +/* ********************************************************************* * GPIO Registers ********************************************************************* */ @@ -537,7 +537,7 @@ #define R_GPIO_PIN_CLR 0x30 #define R_GPIO_PIN_SET 0x38 -/* ********************************************************************* +/* ********************************************************************* * SMBus Registers ********************************************************************* */ @@ -573,7 +573,7 @@ #define R_SMB_CONTROL 0x0000000060 #define R_SMB_PEC 0x0000000070 -/* ********************************************************************* +/* ********************************************************************* * Timer Registers ********************************************************************* */ @@ -641,7 +641,7 @@ #endif /* 1250 PASS2 || 112x PASS1 */ -/* ********************************************************************* +/* ********************************************************************* * System Control Registers ********************************************************************* */ @@ -649,7 +649,7 @@ #define A_SCD_SYSTEM_CFG 0x0010020008 #define A_SCD_SYSTEM_MANUF 0x0010038000 -/* ********************************************************************* +/* ********************************************************************* * System Address Trap Registers ********************************************************************* */ @@ -672,7 +672,7 @@ #endif /* 1250 PASS2 || 112x PASS1 */ -/* ********************************************************************* +/* ********************************************************************* * System Interrupt Mapper Registers ********************************************************************* */ @@ -701,7 +701,7 @@ #define R_IMR_INTERRUPT_MAP_BASE 0x0200 #define R_IMR_INTERRUPT_MAP_COUNT 64 -/* ********************************************************************* +/* ********************************************************************* * System Performance Counter Registers ********************************************************************* */ @@ -711,7 +711,7 @@ #define A_SCD_PERF_CNT_2 0x00100204E0 #define A_SCD_PERF_CNT_3 0x00100204E8 -/* ********************************************************************* +/* ********************************************************************* * System Bus Watcher Registers ********************************************************************* */ @@ -726,13 +726,13 @@ #define A_BUS_L2_ERRORS 0x00100208C0 #define A_BUS_MEM_IO_ERRORS 0x00100208C8 -/* ********************************************************************* +/* ********************************************************************* * System Debug Controller Registers ********************************************************************* */ #define A_SCD_JTAG_BASE 0x0010000000 -/* ********************************************************************* +/* ********************************************************************* * System Trace Buffer Registers ********************************************************************* */ @@ -755,7 +755,7 @@ #define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 #define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 -/* ********************************************************************* +/* ********************************************************************* * System Generic DMA Registers ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h index 22e8041..dbbd682 100644 --- a/include/asm-mips/sibyte/sb1250_scd.h +++ b/include/asm-mips/sibyte/sb1250_scd.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * SCD Constants and Macros File: sb1250_scd.h - * + * * This module contains constants and macros useful for * manipulating the System Control and Debug module on the 1250. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -130,40 +130,40 @@ /* System Manufacturing Register * Register: SCD_SYSTEM_MANUF */ - + /* Wafer ID: bits 31:0 */ #define S_SYS_WAFERID1_200 _SB_MAKE64(0) #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) #define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) #define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) - + #define S_SYS_BIN _SB_MAKE64(32) #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) #define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) #define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) - + /* Wafer ID: bits 39:36 */ #define S_SYS_WAFERID2_200 _SB_MAKE64(36) #define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) #define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) #define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) - + /* Wafer ID: bits 39:0 */ #define S_SYS_WAFERID_300 _SB_MAKE64(0) #define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) #define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) #define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) - + #define S_SYS_XPOS _SB_MAKE64(40) #define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) #define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) #define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) - + #define S_SYS_YPOS _SB_MAKE64(46) #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) - + /* * System Config Register (Table 4-2) * Register: SCD_SYSTEM_CFG diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h index 287cbfe..335c53e 100644 --- a/include/asm-mips/sibyte/sb1250_smbus.h +++ b/include/asm-mips/sibyte/sb1250_smbus.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * SMBUS Constants File: sb1250_smbus.h - * - * This module contains constants and macros useful for + * + * This module contains constants and macros useful for * manipulating the SB1250's SMbus devices. - * + * * SB1250 specification level: 01/02/2002 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h index 8d5e8edd..fa2760d 100644 --- a/include/asm-mips/sibyte/sb1250_syncser.h +++ b/include/asm-mips/sibyte/sb1250_syncser.h @@ -7,17 +7,17 @@ * manipulating the SB1250's Synchronous Serial * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg * ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h index 7655d69..923ea4f 100644 --- a/include/asm-mips/sibyte/sb1250_uart.h +++ b/include/asm-mips/sibyte/sb1250_uart.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * UART Constants File: sb1250_uart.h - * - * This module contains constants and macros useful for + * + * This module contains constants and macros useful for * manipulating the SB1250's UARTs * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -37,7 +37,7 @@ #include "sb1250_defs.h" -/* ********************************************************************** +/* ********************************************************************** * DUART Registers ********************************************************************** */ @@ -145,7 +145,7 @@ #define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) #define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) -#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) +#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) /* * DUART Status Register (Table 10-6) @@ -165,7 +165,7 @@ /* * DUART Baud Rate Register (Table 10-7) - * Register: DUART_CLK_SEL_A + * Register: DUART_CLK_SEL_A * Register: DUART_CLK_SEL_B */ @@ -332,7 +332,7 @@ (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* +/* * Full Interrupt Control Register */ diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h index 18939e8..f7fbeba 100644 --- a/include/asm-mips/sigcontext.h +++ b/include/asm-mips/sigcontext.h @@ -10,7 +10,7 @@ #define _ASM_SIGCONTEXT_H #include <asm/sgidefs.h> - + #if _MIPS_SIM == _MIPS_SIM_ABI32 /* @@ -38,7 +38,7 @@ struct sigcontext { }; #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - + #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 /* diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h index d478a86..753b662 100644 --- a/include/asm-mips/socket.h +++ b/include/asm-mips/socket.h @@ -82,7 +82,7 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ * @SOCK_STREAM - stream (connection) socket * @SOCK_RAW - raw socket * @SOCK_RDM - reliably-delivered message - * @SOCK_SEQPACKET - sequential packet socket + * @SOCK_SEQPACKET - sequential packet socket * @SOCK_PACKET - linux specific way of getting packets at the dev level. * For writing rarp and other similar things on the user level. */ diff --git a/include/asm-mips/statfs.h b/include/asm-mips/statfs.h index 5076fec..c3ddf97 100644 --- a/include/asm-mips/statfs.h +++ b/include/asm-mips/statfs.h @@ -57,7 +57,7 @@ struct statfs64 { }; #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - + #if _MIPS_SIM == _MIPS_SIM_ABI64 struct statfs64 { /* Same as struct statfs */ diff --git a/include/asm-mips/titan_dep.h b/include/asm-mips/titan_dep.h index fd9599e..fee1908 100644 --- a/include/asm-mips/titan_dep.h +++ b/include/asm-mips/titan_dep.h @@ -228,4 +228,4 @@ extern unsigned long ocd_base; #define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) #define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) -#endif +#endif diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index 5d939db..3bb7f00 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h @@ -45,14 +45,14 @@ /* TX4927 SDRAM controller (64-bit registers) */ -#define TX4927_SDRAMC_BASE 0x8000 -#define TX4927_SDRAMC_SDCCR0 0x8000 +#define TX4927_SDRAMC_BASE 0x8000 +#define TX4927_SDRAMC_SDCCR0 0x8000 #define TX4927_SDRAMC_SDCCR1 0x8008 #define TX4927_SDRAMC_SDCCR2 0x8010 #define TX4927_SDRAMC_SDCCR3 0x8018 #define TX4927_SDRAMC_SDCTR 0x8040 #define TX4927_SDRAMC_SDCMD 0x8058 -#define TX4927_SDRAMC_LIMIT 0x8fff +#define TX4927_SDRAMC_LIMIT 0x8fff /* TX4927 external bus controller (64-bit registers) */ @@ -289,8 +289,8 @@ /* TX4927 serial port 0 (32-bit registers) */ -#define TX4927_SIO0_BASE 0xf300 -#define TX4927_SIO0_SILCR0 0xf300 +#define TX4927_SIO0_BASE 0xf300 +#define TX4927_SIO0_SILCR0 0xf300 #define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31 #define TX4927_SIO0_SILCR0_RWUB BM_15_15 #define TX4927_SIO0_SILCR0_TWUB BM_14_14 @@ -309,7 +309,7 @@ #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01) #define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01 #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01 -#define TX4927_SIO0_SIDICR0 0xf304 +#define TX4927_SIO0_SIDICR0 0xf304 #define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31 #define TX4927_SIO0_SIDICR0_TDE BM_15_15 #define TX4927_SIO0_SIDICR0_RDE BM_14_14 @@ -330,7 +330,7 @@ #define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02 #define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01 #define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00 -#define TX4927_SIO0_SIDISR0 0xf308 +#define TX4927_SIO0_SIDISR0 0xf308 #define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31 #define TX4927_SIO0_SIDISR0_UBRK BM_15_15 #define TX4927_SIO0_SIDISR0_UVALID BM_14_14 @@ -344,7 +344,7 @@ #define TX4927_SIO0_SIDISR0_STIS BM_06_06 #define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05 #define TX4927_SIO0_SIDISR0_RFDN BM_00_04 -#define TX4927_SIO0_SISCISR0 0xf30c +#define TX4927_SIO0_SISCISR0 0xf30c #define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31 #define TX4927_SIO0_SISCISR0_OERS BM_05_05 #define TX4927_SIO0_SISCISR0_CTSS BM_04_04 @@ -352,7 +352,7 @@ #define TX4927_SIO0_SISCISR0_TRDY BM_02_02 #define TX4927_SIO0_SISCISR0_TXALS BM_01_01 #define TX4927_SIO0_SISCISR0_UBRKD BM_00_00 -#define TX4927_SIO0_SIFCR0 0xf310 +#define TX4927_SIO0_SIFCR0 0xf310 #define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31 #define TX4927_SIO0_SIFCR0_SWRST BM_16_31 #define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14 @@ -370,7 +370,7 @@ #define TX4927_SIO0_SIFCR0_TFRST BM_02_02 #define TX4927_SIO0_SIFCR0_RFRST BM_01_01 #define TX4927_SIO0_SIFCR0_FRSTE BM_00_00 -#define TX4927_SIO0_SIFLCR0 0xf314 +#define TX4927_SIO0_SIFLCR0 0xf314 #define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31 #define TX4927_SIO0_SIFLCR0_RCS BM_12_12 #define TX4927_SIO0_SIFLCR0_TES BM_11_11 @@ -381,7 +381,7 @@ #define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06 #define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04 #define TX4927_SIO0_SIFLCR0_TBRK BM_00_00 -#define TX4927_SIO0_SIBGR0 0xf318 +#define TX4927_SIO0_SIBGR0 0xf318 #define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31 #define TX4927_SIO0_SIBGR0_BCLK BM_08_09 #define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09) @@ -389,28 +389,28 @@ #define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09 #define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09 #define TX4927_SIO0_SIBGR0_BRD BM_00_07 -#define TX4927_SIO0_SITFIF00 0xf31c +#define TX4927_SIO0_SITFIF00 0xf31c #define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31 #define TX4927_SIO0_SITFIF00_TXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 +#define TX4927_SIO0_SIRFIFO0 0xf320 #define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31 #define TX4927_SIO0_SIRFIFO0_RXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 -#define TX4927_SIO0_LIMIT 0xf3ff +#define TX4927_SIO0_SIRFIFO0 0xf320 +#define TX4927_SIO0_LIMIT 0xf3ff /* TX4927 serial port 1 (32-bit registers) */ -#define TX4927_SIO1_BASE 0xf400 -#define TX4927_SIO1_SILCR1 0xf400 -#define TX4927_SIO1_SIDICR1 0xf404 -#define TX4927_SIO1_SIDISR1 0xf408 -#define TX4927_SIO1_SISCISR1 0xf40c -#define TX4927_SIO1_SIFCR1 0xf410 -#define TX4927_SIO1_SIFLCR1 0xf414 -#define TX4927_SIO1_SIBGR1 0xf418 -#define TX4927_SIO1_SITFIF01 0xf41c -#define TX4927_SIO1_SIRFIFO1 0xf420 -#define TX4927_SIO1_LIMIT 0xf4ff +#define TX4927_SIO1_BASE 0xf400 +#define TX4927_SIO1_SILCR1 0xf400 +#define TX4927_SIO1_SIDICR1 0xf404 +#define TX4927_SIO1_SIDISR1 0xf408 +#define TX4927_SIO1_SISCISR1 0xf40c +#define TX4927_SIO1_SIFCR1 0xf410 +#define TX4927_SIO1_SIFLCR1 0xf414 +#define TX4927_SIO1_SIBGR1 0xf418 +#define TX4927_SIO1_SITFIF01 0xf41c +#define TX4927_SIO1_SIRFIFO1 0xf420 +#define TX4927_SIO1_LIMIT 0xf4ff /* TX4927 parallel port (32-bit registers) */ diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h index 1704334..165f6b8 100644 --- a/include/asm-mips/tx4927/tx4927_pci.h +++ b/include/asm-mips/tx4927/tx4927_pci.h @@ -5,8 +5,8 @@ * * Copyright (C) 2000-2001 Toshiba Corporation */ -#ifndef __ASM_TX4927_TX4927_PCI_H -#define __ASM_TX4927_TX4927_PCI_H +#ifndef __ASM_TX4927_TX4927_PCI_H +#define __ASM_TX4927_TX4927_PCI_H #define TX4927_CCFG_TOE 0x00004000 diff --git a/include/asm-mips/vr41xx/vrc4173.h b/include/asm-mips/vr41xx/vrc4173.h index 58e193c..bb7a85c 100644 --- a/include/asm-mips/vr41xx/vrc4173.h +++ b/include/asm-mips/vr41xx/vrc4173.h @@ -21,8 +21,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __NEC_VRC4173_H -#define __NEC_VRC4173_H +#ifndef __NEC_VRC4173_H +#define __NEC_VRC4173_H #include <linux/config.h> #include <asm/io.h> diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c4a7041..04ee53b 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -113,7 +113,7 @@ */ #define BCM1250_M3_WAR 1 -/* +/* * This is a DUART workaround related to glitches around register accesses */ #define SIBYTE_1956_WAR 1 @@ -122,7 +122,7 @@ /* * Fill buffers not flushed on CACHE instructions - * + * * Hit_Invalidate_I cacheops invalidate an icache line but the refill * for that line can get stale data from the fill buffer instead of * accessing memory if the previous icache miss was also to that line. diff --git a/include/asm-mips/xxs1500.h b/include/asm-mips/xxs1500.h index 75c0ddf..4d84a90 100644 --- a/include/asm-mips/xxs1500.h +++ b/include/asm-mips/xxs1500.h @@ -22,7 +22,7 @@ * * ######################################################################## * - * + * */ #ifndef __ASM_XXS1500_H #define __ASM_XXS1500_H |