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Diffstat (limited to 'arch/arm/mach-exynos/cpufreq-4x12.c')
-rw-r--r--arch/arm/mach-exynos/cpufreq-4x12.c464
1 files changed, 281 insertions, 183 deletions
diff --git a/arch/arm/mach-exynos/cpufreq-4x12.c b/arch/arm/mach-exynos/cpufreq-4x12.c
index d5dd249..5213da1 100644
--- a/arch/arm/mach-exynos/cpufreq-4x12.c
+++ b/arch/arm/mach-exynos/cpufreq-4x12.c
@@ -25,7 +25,7 @@
#include <plat/clock.h>
#include <plat/cpu.h>
-#define CPUFREQ_LEVEL_END (L13 + 1)
+#define CPUFREQ_LEVEL_END (L14 + 1)
#undef PRINT_DIV_VAL
@@ -37,6 +37,7 @@ static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;
+static bool need_dynamic_ema = false;
struct cpufreq_clkdiv {
unsigned int index;
@@ -47,20 +48,21 @@ struct cpufreq_clkdiv {
static unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END];
static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
- {L0, 1500*1000},
- {L1, 1400*1000},
- {L2, 1300*1000},
- {L3, 1200*1000},
- {L4, 1100*1000},
- {L5, 1000*1000},
- {L6, 900*1000},
- {L7, 800*1000},
- {L8, 700*1000},
- {L9, 600*1000},
- {L10, 500*1000},
- {L11, 400*1000},
- {L12, 300*1000},
- {L13, 200*1000},
+ {L0, 1600*1000},
+ {L1, 1500*1000},
+ {L2, 1400*1000},
+ {L3, 1300*1000},
+ {L4, 1200*1000},
+ {L5, 1100*1000},
+ {L6, 1000*1000},
+ {L7, 900*1000},
+ {L8, 800*1000},
+ {L9, 700*1000},
+ {L10, 600*1000},
+ {L11, 500*1000},
+ {L12, 400*1000},
+ {L13, 300*1000},
+ {L14, 200*1000},
{0, CPUFREQ_TABLE_END},
};
@@ -72,46 +74,49 @@ static unsigned int clkdiv_cpu0_4212[CPUFREQ_LEVEL_END][8] = {
* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
* DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }
*/
- /* ARM L0: 1500Mhz */
+ /* ARM L0: 1600Mhz */
{ 0, 3, 7, 0, 6, 1, 2, 0 },
- /* ARM L1: 1400Mhz */
+ /* ARM L1: 1500Mhz */
{ 0, 3, 7, 0, 6, 1, 2, 0 },
- /* ARM L2: 1300Mhz */
+ /* ARM L2: 1400Mhz */
+ { 0, 3, 7, 0, 6, 1, 2, 0 },
+
+ /* ARM L3: 1300Mhz */
{ 0, 3, 7, 0, 5, 1, 2, 0 },
- /* ARM L3: 1200Mhz */
+ /* ARM L4: 1200Mhz */
{ 0, 3, 7, 0, 5, 1, 2, 0 },
- /* ARM L4: 1100MHz */
+ /* ARM L5: 1100MHz */
{ 0, 3, 6, 0, 4, 1, 2, 0 },
- /* ARM L5: 1000MHz */
+ /* ARM L6: 1000MHz */
{ 0, 2, 5, 0, 4, 1, 1, 0 },
- /* ARM L6: 900MHz */
+ /* ARM L7: 900MHz */
{ 0, 2, 5, 0, 3, 1, 1, 0 },
- /* ARM L7: 800MHz */
+ /* ARM L8: 800MHz */
{ 0, 2, 5, 0, 3, 1, 1, 0 },
- /* ARM L8: 700MHz */
+ /* ARM L9: 700MHz */
{ 0, 2, 4, 0, 3, 1, 1, 0 },
- /* ARM L9: 600MHz */
+ /* ARM L10: 600MHz */
{ 0, 2, 4, 0, 3, 1, 1, 0 },
- /* ARM L10: 500MHz */
+ /* ARM L11: 500MHz */
{ 0, 2, 4, 0, 3, 1, 1, 0 },
- /* ARM L11: 400MHz */
+ /* ARM L12: 400MHz */
{ 0, 2, 4, 0, 3, 1, 1, 0 },
- /* ARM L12: 300MHz */
+ /* ARM L13: 300MHz */
{ 0, 2, 4, 0, 2, 1, 1, 0 },
- /* ARM L13: 200MHz */
+ /* ARM L14: 200MHz */
{ 0, 1, 3, 0, 1, 1, 1, 0 },
};
@@ -121,46 +126,49 @@ static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = {
* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
* DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }
*/
- /* ARM L0: 1500Mhz */
- { 0, 3, 7, 0, 6, 1, 2, 0 },
+ /* ARM L0: 1600Mhz */
+ { 0, 3, 7, 0, 6, 1, 7, 0 },
- /* ARM L1: 1400Mhz */
- { 0, 3, 7, 0, 6, 1, 2, 0 },
+ /* ARM L1: 1500Mhz */
+ { 0, 3, 7, 0, 6, 1, 7, 0 },
- /* ARM L2: 1300Mhz */
- { 0, 3, 7, 0, 5, 1, 2, 0 },
+ /* ARM L2: 1400Mhz */
+ { 0, 3, 7, 0, 6, 1, 6, 0 },
- /* ARM L3: 1200Mhz */
- { 0, 3, 7, 0, 5, 1, 2, 0 },
+ /* ARM L3: 1300Mhz */
+ { 0, 3, 7, 0, 5, 1, 6, 0 },
- /* ARM L4: 1100MHz */
- { 0, 3, 6, 0, 4, 1, 2, 0 },
+ /* ARM L4: 1200Mhz */
+ { 0, 3, 7, 0, 5, 1, 5, 0 },
- /* ARM L5: 1000MHz */
- { 0, 2, 5, 0, 4, 1, 1, 0 },
+ /* ARM L5: 1100MHz */
+ { 0, 3, 6, 0, 4, 1, 5, 0 },
- /* ARM L6: 900MHz */
- { 0, 2, 5, 0, 3, 1, 1, 0 },
+ /* ARM L6: 1000MHz */
+ { 0, 2, 5, 0, 4, 1, 4, 0 },
- /* ARM L7: 800MHz */
- { 0, 2, 5, 0, 3, 1, 1, 0 },
+ /* ARM L7: 900MHz */
+ { 0, 2, 5, 0, 3, 1, 4, 0 },
- /* ARM L8: 700MHz */
- { 0, 2, 4, 0, 3, 1, 1, 0 },
+ /* ARM L8: 800MHz */
+ { 0, 2, 5, 0, 3, 1, 3, 0 },
- /* ARM L9: 600MHz */
- { 0, 2, 4, 0, 3, 1, 1, 0 },
+ /* ARM L9: 700MHz */
+ { 0, 2, 4, 0, 3, 1, 3, 0 },
- /* ARM L10: 500MHz */
- { 0, 2, 4, 0, 3, 1, 1, 0 },
+ /* ARM L10: 600MHz */
+ { 0, 2, 4, 0, 3, 1, 2, 0 },
+
+ /* ARM L11: 500MHz */
+ { 0, 2, 4, 0, 3, 1, 2, 0 },
- /* ARM L11: 400MHz */
+ /* ARM L12: 400MHz */
{ 0, 2, 4, 0, 3, 1, 1, 0 },
- /* ARM L12: 300MHz */
+ /* ARM L13: 300MHz */
{ 0, 2, 4, 0, 2, 1, 1, 0 },
- /* ARM L13: 200MHz */
+ /* ARM L14: 200MHz */
{ 0, 1, 3, 0, 1, 1, 1, 0 },
};
@@ -168,46 +176,49 @@ static unsigned int clkdiv_cpu1_4212[CPUFREQ_LEVEL_END][2] = {
/* Clock divider value for following
* { DIVCOPY, DIVHPM }
*/
- /* ARM L0: 1500MHz */
+ /* ARM L0: 1600MHz */
{ 6, 0 },
- /* ARM L1: 1400MHz */
+ /* ARM L1: 1500MHz */
{ 6, 0 },
- /* ARM L2: 1300MHz */
+ /* ARM L2: 1400MHz */
+ { 6, 0 },
+
+ /* ARM L3: 1300MHz */
{ 5, 0 },
- /* ARM L3: 1200MHz */
+ /* ARM L4: 1200MHz */
{ 5, 0 },
- /* ARM L4: 1100MHz */
+ /* ARM L5: 1100MHz */
{ 4, 0 },
- /* ARM L5: 1000MHz */
+ /* ARM L6: 1000MHz */
{ 4, 0 },
- /* ARM L6: 900MHz */
+ /* ARM L7: 900MHz */
{ 3, 0 },
- /* ARM L7: 800MHz */
+ /* ARM L8: 800MHz */
{ 3, 0 },
- /* ARM L8: 700MHz */
+ /* ARM L9: 700MHz */
{ 3, 0 },
- /* ARM L9: 600MHz */
+ /* ARM L10: 600MHz */
{ 3, 0 },
- /* ARM L10: 500MHz */
+ /* ARM L11: 500MHz */
{ 3, 0 },
- /* ARM L11: 400MHz */
+ /* ARM L12: 400MHz */
{ 3, 0 },
- /* ARM L12: 300MHz */
+ /* ARM L13: 300MHz */
{ 3, 0 },
- /* ARM L13: 200MHz */
+ /* ARM L14: 200MHz */
{ 3, 0 },
};
@@ -215,90 +226,96 @@ static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = {
/* Clock divider value for following
* { DIVCOPY, DIVHPM, DIVCORES }
*/
- /* ARM L0: 1500MHz */
+ /* ARM L0: 1600MHz */
+ { 6, 0, 7 },
+
+ /* ARM L1: 1500MHz */
{ 6, 0, 7 },
- /* ARM L1: 1400MHz */
+ /* ARM L2: 1400MHz */
{ 6, 0, 6 },
- /* ARM L2: 1300MHz */
+ /* ARM L3: 1300MHz */
{ 5, 0, 6 },
- /* ARM L3: 1200MHz */
+ /* ARM L4: 1200MHz */
{ 5, 0, 5 },
- /* ARM L4: 1100MHz */
+ /* ARM L5: 1100MHz */
{ 4, 0, 5 },
- /* ARM L5: 1000MHz */
+ /* ARM L6: 1000MHz */
{ 4, 0, 4 },
- /* ARM L6: 900MHz */
+ /* ARM L7: 900MHz */
{ 3, 0, 4 },
- /* ARM L7: 800MHz */
+ /* ARM L8: 800MHz */
{ 3, 0, 3 },
- /* ARM L8: 700MHz */
+ /* ARM L9: 700MHz */
{ 3, 0, 3 },
- /* ARM L9: 600MHz */
+ /* ARM L10: 600MHz */
{ 3, 0, 2 },
- /* ARM L10: 500MHz */
+ /* ARM L11: 500MHz */
{ 3, 0, 2 },
- /* ARM L11: 400MHz */
+ /* ARM L12: 400MHz */
{ 3, 0, 1 },
- /* ARM L12: 300MHz */
+ /* ARM L13: 300MHz */
{ 3, 0, 1 },
- /* ARM L13: 200MHz */
+ /* ARM L14: 200MHz */
{ 3, 0, 0 },
};
static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = {
- /* APLL FOUT L0: 1500MHz */
+ /* APLL FOUT L0: 1600MHz */
+ ((200<<16)|(3<<8)|(0x0)),
+
+ /* APLL FOUT L1: 1500MHz */
((250<<16)|(4<<8)|(0x0)),
- /* APLL FOUT L1: 1400MHz */
+ /* APLL FOUT L2: 1400MHz */
((175<<16)|(3<<8)|(0x0)),
- /* APLL FOUT L2: 1300MHz */
+ /* APLL FOUT L3: 1300MHz */
((325<<16)|(6<<8)|(0x0)),
- /* APLL FOUT L3: 1200MHz */
+ /* APLL FOUT L4: 1200MHz */
((200<<16)|(4<<8)|(0x0)),
- /* APLL FOUT L4: 1100MHz */
+ /* APLL FOUT L5: 1100MHz */
((275<<16)|(6<<8)|(0x0)),
- /* APLL FOUT L5: 1000MHz */
+ /* APLL FOUT L6: 1000MHz */
((125<<16)|(3<<8)|(0x0)),
- /* APLL FOUT L6: 900MHz */
+ /* APLL FOUT L7: 900MHz */
((150<<16)|(4<<8)|(0x0)),
- /* APLL FOUT L7: 800MHz */
+ /* APLL FOUT L8: 800MHz */
((100<<16)|(3<<8)|(0x0)),
- /* APLL FOUT L8: 700MHz */
+ /* APLL FOUT L9: 700MHz */
((175<<16)|(3<<8)|(0x1)),
- /* APLL FOUT L9: 600MHz */
+ /* APLL FOUT L10: 600MHz */
((200<<16)|(4<<8)|(0x1)),
- /* APLL FOUT L10: 500MHz */
+ /* APLL FOUT L11: 500MHz */
((125<<16)|(3<<8)|(0x1)),
- /* APLL FOUT L11 400MHz */
+ /* APLL FOUT L12 400MHz */
((100<<16)|(3<<8)|(0x1)),
- /* APLL FOUT L12: 300MHz */
+ /* APLL FOUT L13: 300MHz */
((200<<16)|(4<<8)|(0x2)),
- /* APLL FOUT L13: 200MHz */
+ /* APLL FOUT L14: 200MHz */
((100<<16)|(3<<8)|(0x2)),
};
@@ -312,19 +329,20 @@ static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = {
static const unsigned int asv_voltage_4212[CPUFREQ_LEVEL_END][12] = {
/* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 */
{ 0, 1300000, 1300000, 1275000, 1300000, 1287500, 1275000, 1250000, 1237500, 1225000, 1225000, 1212500 }, /* L0 */
- { 1300000, 1287500, 1250000, 1225000, 1237500, 1237500, 1225000, 1200000, 1187500, 1175000, 1175000, 1162500 }, /* L1 */
- { 1237500, 1225000, 1200000, 1175000, 1187500, 1187500, 1162500, 1150000, 1137500, 1125000, 1125000, 1112500 }, /* L2 */
- { 1187500, 1175000, 1150000, 1137500, 1150000, 1137500, 1125000, 1100000, 1087500, 1075000, 1075000, 1062500 }, /* L3 */
- { 1137500, 1125000, 1112500, 1087500, 1112500, 1112500, 1075000, 1062500, 1050000, 1025000, 1025000, 1012500 }, /* L4 */
- { 1100000, 1087500, 1075000, 1050000, 1075000, 1062500, 1037500, 1025000, 1012500, 1000000, 987500, 975000 }, /* L5 */
- { 1050000, 1037500, 1025000, 1000000, 1025000, 1025000, 987500, 975000, 962500, 950000, 937500, 925000 }, /* L6 */
- { 1012500, 1000000, 987500, 962500, 987500, 975000, 962500, 937500, 925000, 912500, 912500, 900000 }, /* L7 */
- { 962500, 950000, 937500, 912500, 937500, 937500, 925000, 900000, 900000, 900000, 900000, 900000 }, /* L8 */
- { 925000, 912500, 912500, 900000, 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L9 */
- { 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L10 */
+ { 0, 1300000, 1300000, 1275000, 1300000, 1287500, 1275000, 1250000, 1237500, 1225000, 1225000, 1212500 }, /* L1 */
+ { 1300000, 1287500, 1250000, 1225000, 1237500, 1237500, 1225000, 1200000, 1187500, 1175000, 1175000, 1162500 }, /* L2 */
+ { 1237500, 1225000, 1200000, 1175000, 1187500, 1187500, 1162500, 1150000, 1137500, 1125000, 1125000, 1112500 }, /* L3 */
+ { 1187500, 1175000, 1150000, 1137500, 1150000, 1137500, 1125000, 1100000, 1087500, 1075000, 1075000, 1062500 }, /* L4 */
+ { 1137500, 1125000, 1112500, 1087500, 1112500, 1112500, 1075000, 1062500, 1050000, 1025000, 1025000, 1012500 }, /* L5 */
+ { 1100000, 1087500, 1075000, 1050000, 1075000, 1062500, 1037500, 1025000, 1012500, 1000000, 987500, 975000 }, /* L6 */
+ { 1050000, 1037500, 1025000, 1000000, 1025000, 1025000, 987500, 975000, 962500, 950000, 937500, 925000 }, /* L7 */
+ { 1012500, 1000000, 987500, 962500, 987500, 975000, 962500, 937500, 925000, 912500, 912500, 900000 }, /* L8 */
+ { 962500, 950000, 937500, 912500, 937500, 937500, 925000, 900000, 900000, 900000, 900000, 900000 }, /* L9 */
+ { 925000, 912500, 912500, 900000, 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L10 */
{ 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L11 */
{ 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L12 */
{ 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L13 */
+ { 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L14 */
};
static const unsigned int asv_voltage_s[CPUFREQ_LEVEL_END] = {
@@ -333,30 +351,10 @@ static const unsigned int asv_voltage_s[CPUFREQ_LEVEL_END] = {
};
/* ASV table for 12.5mV step */
-#if 0
-/* 20120105 DVFS table version */
-static const unsigned int asv_voltage_step_12_5[CPUFREQ_LEVEL_END][12] = {
- /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L0 - Not used */
- { 1300000, 1300000, 1300000, 1287500, 1300000, 1287500, 1275000, 1250000, 1250000, 1237500, 1225000, 1212500 },
- { 1300000, 1300000, 1237500, 1237500, 1250000, 1250000, 1237500, 1212500, 1200000, 1200000, 1187500, 1175000 },
- { 1225000, 1212500, 1200000, 1187500, 1200000, 1187500, 1175000, 1150000, 1137500, 1125000, 1125000, 1112500 },
- { 1175000, 1162500, 1150000, 1137500, 1150000, 1137500, 1125000, 1100000, 1100000, 1075000, 1075000, 1062500 },
- { 1125000, 1112500, 1100000, 1087500, 1100000, 1087500, 1075000, 1050000, 1037500, 1025000, 1025000, 1012500 },
- { 1075000, 1062500, 1050000, 1050000, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 987500, 975000 },
- { 1037500, 1025000, 1012500, 1012500, 1012500, 1000000, 987500, 975000, 975000, 975000, 975000, 962500 },
- { 1012500, 1000000, 987500, 987500, 987500, 987500, 975000, 975000, 962500, 962500, 962500, 950000 },
- { 1000000, 987500, 975000, 975000, 975000, 975000, 962500, 962500, 950000, 950000, 950000, 937500 },
- { 987500, 975000, 962500, 950000, 962500, 950000, 950000, 950000, 925000, 925000, 925000, 912500 },
- { 975000, 962500, 950000, 925000, 950000, 925000, 925000, 925000, 900000, 900000, 900000, 887500 },
- { 950000, 937500, 925000, 900000, 925000, 900000, 900000, 900000, 900000, 887500, 875000, 862500 },
- { 925000, 912500, 900000, 900000, 900000, 900000, 900000, 900000, 887500, 875000, 875000, 862500 },
-};
-#else
-/* 20120210 DVFS table version */
static const unsigned int asv_voltage_step_12_5[CPUFREQ_LEVEL_END][12] = {
/* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L0 - Not used */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L1 - Not used */
{ 1325000, 1312500, 1300000, 1287500, 1300000, 1287500, 1275000, 1250000, 1250000, 1237500, 1225000, 1212500 },
{ 1300000, 1275000, 1237500, 1237500, 1250000, 1250000, 1237500, 1212500, 1200000, 1200000, 1187500, 1175000 },
{ 1225000, 1212500, 1200000, 1187500, 1200000, 1187500, 1175000, 1150000, 1137500, 1125000, 1125000, 1112500 },
@@ -371,7 +369,46 @@ static const unsigned int asv_voltage_step_12_5[CPUFREQ_LEVEL_END][12] = {
{ 950000, 937500, 925000, 900000, 925000, 900000, 900000, 900000, 900000, 887500, 875000, 862500 },
{ 925000, 912500, 900000, 900000, 900000, 900000, 900000, 900000, 887500, 875000, 875000, 862500 },
};
-#endif
+
+/* 20120725 DVFS table for pega prime */
+static const unsigned int asv_voltage_step_12_5_rev2[CPUFREQ_LEVEL_END][13] = {
+ /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 ASV12 */
+ { 1312500, 1312500, 1312500, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000, 1237500, 1212500, 1200000, 1187500 }, /* L0 */
+ { 1275000, 1262500, 1262500, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500, 1162500, 1150000, 1137500 }, /* L1 */
+ { 1237500, 1225000, 1225000, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, 1125000, 1112500, 1100000 }, /* L2 */
+ { 1187500, 1175000, 1175000, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1075000, 1062500, 1050000 }, /* L3 */
+ { 1150000, 1137500, 1137500, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1037500, 1025000, 1012500 }, /* L4 */
+ { 1112500, 1100000, 1100000, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1000000, 987500, 975000 }, /* L5 */
+ { 1087500, 1075000, 1075000, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 975000, 962500, 950000 }, /* L6 */
+ { 1062500, 1050000, 1050000, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000, 950000, 937500, 925000 }, /* L7 */
+ { 1025000, 1012500, 1012500, 1012500, 1000000, 987500, 975000, 962500, 950000, 937500, 912500, 900000, 887500 }, /* L8 */
+ { 1000000, 987500, 987500, 987500, 975000, 962500, 950000, 937500, 925000, 912500, 887500, 887500, 887500 }, /* L9 */
+ { 975000, 962500, 962500, 962500, 950000, 937500, 925000, 912500, 900000, 887500, 875000, 875000, 875000 }, /* L10 */
+ { 962500, 950000, 950000, 950000, 937500, 925000, 912500, 900000, 887500, 887500, 875000, 875000, 875000 }, /* L11 */
+ { 950000, 937500, 937500, 937500, 925000, 912500, 900000, 887500, 887500, 887500, 875000, 875000, 875000 }, /* L12 */
+ { 937500, 925000, 925000, 925000, 912500, 900000, 887500, 887500, 887500, 887500, 875000, 875000, 875000 }, /* L13 */
+ { 925000, 912500, 912500, 912500, 900000, 887500, 887500, 887500, 887500, 887500, 875000, 875000, 875000 }, /* L14 */
+};
+
+static const unsigned int asv_voltage_step_1ghz[CPUFREQ_LEVEL_END][12] = {
+ /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L0 - Not used */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L1 - Not used */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L2 - Not used */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L3 - Not used */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L4 - Not used */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L5 - Not used */
+ { 1200000, 1200000, 1200000, 1200000, 1125000, 1125000, 1125000, 1075000, 1075000, 1075000, 1075000, 1037500 },
+ { 1150000, 1150000, 1150000, 1150000, 1075000, 1075000, 1075000, 1037500, 1037500, 1037500, 1037500, 1000000 },
+ { 1100000, 1100000, 1100000, 1100000, 1025000, 1025000, 1025000, 987500, 987500, 987500, 987500, 975000 },
+ { 1050000, 1050000, 1050000, 1050000, 1000000, 1000000, 1000000, 987500, 987500, 987500, 987500, 962500 },
+ { 1025000, 1025000, 1025000, 1025000, 987500, 987500, 987500, 975000, 975000, 975000, 975000, 950000 },
+ { 1000000, 1000000, 1000000, 1000000, 975000, 975000, 975000, 962500, 962500, 962500, 962500, 925000 },
+ { 1000000, 1000000, 1000000, 1000000, 975000, 975000, 975000, 950000, 950000, 950000, 950000, 912500 },
+ { 975000, 975000, 975000, 975000, 950000, 950000, 950000, 925000, 925000, 925000, 925000, 887500 },
+ { 975000, 975000, 975000, 975000, 937500, 937500, 937500, 925000, 925000, 925000, 925000, 887500 },
+};
+
static void set_clkdiv(unsigned int div_index)
{
unsigned int tmp;
@@ -470,6 +507,16 @@ static void exynos4x12_set_frequency(unsigned int old_index,
unsigned int tmp;
if (old_index > new_index) {
+ if (exynos4x12_volt_table[new_index] >= 950000 &&
+ need_dynamic_ema)
+ __raw_writel(0x101, EXYNOS4_EMA_CONF);
+
+ if ((samsung_rev() >= EXYNOS4412_REV_2_0)
+ && (exynos_result_of_asv > 2)
+ && (old_index > L8) && (new_index <= L8)) {
+ exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_130V);
+ }
+
if (!exynos4x12_pms_change(old_index, new_index)) {
/* 1. Change the system clock divider values */
set_clkdiv(new_index);
@@ -502,62 +549,53 @@ static void exynos4x12_set_frequency(unsigned int old_index,
/* 2. Change the system clock divider values */
set_clkdiv(new_index);
}
+ if ((samsung_rev() >= EXYNOS4412_REV_2_0)
+ && (exynos_result_of_asv > 2)
+ && (old_index <= L8) && (new_index > L8)) {
+ exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_100V);
+ }
+ if (exynos4x12_volt_table[new_index] < 950000 &&
+ need_dynamic_ema)
+ __raw_writel(0x404, EXYNOS4_EMA_CONF);
}
/* ABB value is changed in below case */
- if (soc_is_exynos4412() && (exynos_result_of_asv > 3)) {
- if (new_index == L13)
+ if (soc_is_exynos4412() && (exynos_result_of_asv > 3)
+ && (samsung_rev() < EXYNOS4412_REV_2_0)) {
+ if (new_index == L14)
exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_100V);
else
exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_130V);
}
}
-static void __init set_volt_table(void)
+/* Get maximum cpufreq index of chip */
+static unsigned int get_max_cpufreq_idx(void)
{
- bool for_1500 = false, for_1200 = false, for_1400 = false;
- unsigned int i;
-
-#ifdef CONFIG_EXYNOS4X12_1500MHZ_SUPPORT
- for_1500 = true;
- max_support_idx = L0;
-#elif defined(CONFIG_EXYNOS4X12_1200MHZ_SUPPORT)
- for_1200 = true;
- max_support_idx = L3;
-#elif defined(CONFIG_EXYNOS4X12_1400MHZ_SUPPORT)
- for_1400 = true;
- max_support_idx = L1;
-
- /* It doesn't support 1400Mhz under EVT1 or when IDS >= 40 */
- if (samsung_rev() < EXYNOS4412_REV_1_0 || exynos_result_of_asv > 9) {
- for_1200 = true;
- max_support_idx = L3;
- }
-#else
- max_support_idx = L5;
-#endif
- /*
- * Should be fixed !!!
- */
-#if 0
- if ((asv_group == 0) || !for_1400)
- exynos4212_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
-#else
- if (!for_1500 && !for_1200 && !for_1400) {
- exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
- exynos4x12_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID;
- exynos4x12_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID;
- exynos4x12_freq_table[L3].frequency = CPUFREQ_ENTRY_INVALID;
- exynos4x12_freq_table[L4].frequency = CPUFREQ_ENTRY_INVALID;
- } else if (for_1200) {
- exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
- exynos4x12_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID;
- exynos4x12_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID;
- } else if (for_1400) {
- exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
+ unsigned int index;
+
+ /* exynos4x12 prime supports 1.6GHz */
+ if (samsung_rev() >= EXYNOS4412_REV_2_0)
+ index = L0;
+ else {
+ /* exynos4x12 supports only 1.4GHz and 1.1GHz */
+ if (exynos_armclk_max != 1400000)
+ index = L6;
+ else
+ index = L2;
}
-#endif
+ return index;
+}
+
+static void __init set_volt_table(void)
+{
+ unsigned int i, tmp;
+
+ max_support_idx = get_max_cpufreq_idx();
+
+ for (i = 0; i < max_support_idx; i++)
+ exynos4x12_freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
pr_info("DVFS : VDD_ARM Voltage table set with %d Group\n", exynos_result_of_asv);
@@ -570,13 +608,62 @@ static void __init set_volt_table(void)
exynos4x12_volt_table[i] =
asv_voltage_4212[i][exynos_result_of_asv];
} else if (soc_is_exynos4412()) {
- for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
- exynos4x12_volt_table[i] =
- asv_voltage_step_12_5[i][exynos_result_of_asv];
+ if (samsung_rev() >= EXYNOS4412_REV_2_0) {
+ for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
+ exynos4x12_volt_table[i] =
+ asv_voltage_step_12_5_rev2[i][exynos_result_of_asv];
+ } else {
+ if (exynos_armclk_max == 1000000) {
+ for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
+ exynos4x12_volt_table[i] =
+ asv_voltage_step_1ghz[i][exynos_result_of_asv];
+ } else {
+ for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
+ exynos4x12_volt_table[i] =
+ asv_voltage_step_12_5[i][exynos_result_of_asv];
+ }
+ }
} else {
pr_err("%s: Can't find SoC type \n", __func__);
}
}
+
+ if (soc_is_exynos4412() && (samsung_rev() >= EXYNOS4412_REV_2_0)) {
+ tmp = (is_special_flag() >> ARM_LOCK_FLAG) & 0x3;
+
+ if (tmp) {
+ pr_info("%s : special flag[%d]\n", __func__, tmp);
+ switch (tmp) {
+ case 1:
+ /* 500MHz fixed volt */
+ i = L11;
+ break;
+ case 2:
+ /* 700MHz fixed volt */
+ i = L9;
+ break;
+ case 3:
+ /* 800MHz fixed volt */
+ i = L8;
+ break;
+ default:
+ break;
+ }
+
+ pr_info("ARM voltage locking at L%d\n", i);
+
+ for (tmp = (i + 1) ; tmp < CPUFREQ_LEVEL_END ; tmp++) {
+ exynos4x12_volt_table[tmp] =
+ exynos4x12_volt_table[i];
+ pr_info("CPUFREQ: L%d : %d\n", tmp, exynos4x12_volt_table[tmp]);
+ }
+ }
+
+ if (exynos_dynamic_ema) {
+ need_dynamic_ema = true;
+ pr_info("%s: Dynamic EMA is enabled\n", __func__);
+ }
+ }
}
/*
@@ -586,10 +673,10 @@ static void __init set_volt_table(void)
*/
#ifdef CONFIG_SLP
static struct dvfs_qos_info exynos4x12_dma_lat_qos[] = {
- { 118, 200000, L13 },
- { 40, 500000, L10 },
- { 24, 800000, L7 },
- { 16, 1000000, L5 },
+ { 118, 200000, L14 },
+ { 40, 500000, L11 },
+ { 24, 800000, L8 },
+ { 16, 1000000, L6 },
{},
};
#endif
@@ -677,8 +764,8 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
info->mpll_freq_khz = rate;
#ifdef CONFIG_SLP
- /* S-Boot at 20120406 uses L7 at bootup */
- info->pm_lock_idx = L7;
+ /* S-Boot at 20120406 uses L8 at bootup */
+ info->pm_lock_idx = L8;
/*
* However, the bootup frequency might get changed anytime.
@@ -695,9 +782,20 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
pr_info("Bootup CPU Frequency = [%d] %dMHz\n", info->pm_lock_idx,
rate / 1000);
#else
- info->pm_lock_idx = L5;
+ info->pm_lock_idx = L6;
#endif
- info->pll_safe_idx = L7;
+ /*
+ * ARM clock source will be changed APLL to MPLL temporary
+ * in exynos4x12_set_frequency.
+ * To support MPLL, vdd_arm is supplied to voltage at frequency
+ * higher than MPLL.
+ * So, pll_safe_idx set to value based on MPLL clock.(800MHz or 880MHz)
+ */
+ if (samsung_rev() >= EXYNOS4412_REV_2_0)
+ info->pll_safe_idx = L7;
+ else
+ info->pll_safe_idx = L8;
+
info->max_support_idx = max_support_idx;
info->min_support_idx = min_support_idx;
info->cpu_clk = cpu_clk;
generated by cgit v1.1 at 2024-04-25 16:30:44 +0000