diff options
Diffstat (limited to 'arch/arm/mach-exynos/mach-smdkv310.c')
| -rw-r--r-- | arch/arm/mach-exynos/mach-smdkv310.c | 2406 |
1 files changed, 2348 insertions, 58 deletions
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index cec2afa..3bb14d5 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-exynos4/mach-smdkv310.c +/* linux/arch/arm/mach-exynos/mach-smdkv310.c * * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com @@ -11,37 +11,109 @@ #include <linux/serial_core.h> #include <linux/delay.h> #include <linux/gpio.h> +#include <linux/gpio_event.h> #include <linux/lcd.h> #include <linux/mmc/host.h> #include <linux/platform_device.h> #include <linux/smsc911x.h> #include <linux/io.h> #include <linux/i2c.h> -#include <linux/input.h> #include <linux/pwm_backlight.h> +#include <linux/input.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/max8649.h> +#include <linux/regulator/fixed.h> +#include <linux/mfd/wm8994/pdata.h> +#include <linux/mfd/max8997.h> +#include <linux/v4l2-mediabus.h> +#include <linux/memblock.h> +#if defined(CONFIG_CMA) +#include <linux/cma.h> +#endif #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <video/platform_lcd.h> + #include <plat/regs-serial.h> #include <plat/regs-srom.h> -#include <plat/regs-fb-v4.h> #include <plat/exynos4.h> +#include <plat/clock.h> +#include <plat/hwmon.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/fb.h> +#include <plat/fb-s5p.h> +#ifdef CONFIG_VIDEO_FIMC +#include <plat/fimc.h> +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC +#include <media/s5p_fimc.h> +#include <plat/fimc-core.h> +#endif +#ifdef CONFIG_VIDEO_FIMC_MIPI +#include <plat/csis.h> +#endif +#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS +#include <plat/mipi_csis.h> +#endif +#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X) +#include <plat/s5p-mfc.h> +#endif +#include <plat/gpio-cfg.h> +#include <plat/adc.h> +#include <plat/ts.h> #include <plat/keypad.h> #include <plat/sdhci.h> +#include <plat/mshci.h> #include <plat/iic.h> +#include <plat/sysmmu.h> #include <plat/pd.h> -#include <plat/gpio-cfg.h> #include <plat/backlight.h> -#include <plat/mfc.h> +#include <plat/regs-fb-v4.h> +#include <plat/media.h> +#include <plat/s5p-clock.h> +#include <plat/tvout.h> +#include <plat/fimg2d.h> #include <plat/ehci.h> -#include <plat/clock.h> +#include <plat/usbgadget.h> +#ifdef CONFIG_S3C64XX_DEV_SPI +#include <plat/s3c64xx-spi.h> +#endif #include <mach/map.h> +#include <mach/media.h> +#include <mach/dev-sysmmu.h> +#include <mach/regs-clock.h> +#include <mach/exynos-ion.h> +#ifdef CONFIG_S3C64XX_DEV_SPI +#include <mach/spi-clocks.h> +#endif +#ifdef CONFIG_EXYNOS4_DEV_DWMCI +#include <mach/dwmci.h> +#endif +#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION +#include <mach/secmem.h> +#endif +#include <mach/dev.h> + +#include <media/s5k4ba_platform.h> +#include <media/s5k4ea_platform.h> +#include <media/m5mo_platform.h> +#include <media/m5mols.h> + +#if defined(CONFIG_EXYNOS4_SETUP_THERMAL) +#include <plat/s5p-tmu.h> +#endif + +#if defined(CONFIG_FB_S5P_MIPI_DSIM) +#include <mach/mipi_ddi.h> +#include <mach/dsim.h> +#include <../../../drivers/video/samsung/s3cfb.h> +#endif /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -88,6 +160,472 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = { }, }; +#define WRITEBACK_ENABLED + +#if defined(CONFIG_VIDEO_FIMC) || defined(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) +/* + * External camera reset + * Because the most of cameras take i2c bus signal, so that + * you have to reset at the boot time for other i2c slave devices. + * This function also called at fimc_init_camera() + * Do optimization for cameras on your platform. +*/ +#if defined(CONFIG_ITU_A) || defined(CONFIG_CSI_C) +static int smdkv310_cam0_reset(int dummy) +{ + int err; + /* Camera A */ + err = gpio_request(EXYNOS4_GPX1(2), "GPX1"); + if (err) + printk(KERN_ERR "#### failed to request GPX1_2 ####\n"); + + s3c_gpio_setpull(EXYNOS4_GPX1(2), S3C_GPIO_PULL_NONE); + gpio_direction_output(EXYNOS4_GPX1(2), 0); + gpio_direction_output(EXYNOS4_GPX1(2), 1); + gpio_free(EXYNOS4_GPX1(2)); + + return 0; +} +#endif +#if defined(CONFIG_ITU_B) || defined(CONFIG_CSI_D) +static int smdkv310_cam1_reset(int dummy) +{ + int err; + + /* Camera B */ + err = gpio_request(EXYNOS4_GPX1(0), "GPX1"); + if (err) + printk(KERN_ERR "#### failed to request GPX1_0 ####\n"); + + s3c_gpio_setpull(EXYNOS4_GPX1(0), S3C_GPIO_PULL_NONE); + gpio_direction_output(EXYNOS4_GPX1(0), 0); + gpio_direction_output(EXYNOS4_GPX1(0), 1); + gpio_free(EXYNOS4_GPX1(0)); + + return 0; +} +#endif +/* for 12M camera */ +#ifdef CE143_MONACO +static int smdkv310_cam0_standby(void) +{ + int err; + /* Camera A */ + err = gpio_request(EXYNOS4_GPX3(3), "GPX3"); + if (err) + printk(KERN_ERR "#### failed to request GPX3_3 ####\n"); + s3c_gpio_setpull(EXYNOS4_GPX3(3), S3C_GPIO_PULL_NONE); + gpio_direction_output(EXYNOS4_GPX3(3), 0); + gpio_direction_output(EXYNOS4_GPX3(3), 1); + gpio_free(EXYNOS4_GPX3(3)); + + return 0; +} + +static int smdkv310_cam1_standby(void) +{ + int err; + + /* Camera B */ + err = gpio_request(EXYNOS4_GPX1(1), "GPX1"); + if (err) + printk(KERN_ERR "#### failed to request GPX1_1 ####\n"); + s3c_gpio_setpull(EXYNOS4_GPX1(1), S3C_GPIO_PULL_NONE); + gpio_direction_output(EXYNOS4_GPX1(1), 0); + gpio_direction_output(EXYNOS4_GPX1(1), 1); + gpio_free(EXYNOS4_GPX1(1)); + + return 0; +} +#endif +#endif + +#ifdef CONFIG_VIDEO_FIMC +#ifdef CONFIG_VIDEO_S5K4BA +static struct s5k4ba_platform_data s5k4ba_plat = { + .default_width = 800, + .default_height = 600, + .pixelformat = V4L2_PIX_FMT_YUYV, + .freq = 24000000, + .is_mipi = 0, +}; + +static struct i2c_board_info s5k4ba_i2c_info = { + I2C_BOARD_INFO("S5K4BA", 0x2d), + .platform_data = &s5k4ba_plat, +}; + +static struct s3c_platform_camera s5k4ba = { +#ifdef CONFIG_ITU_A + .id = CAMERA_PAR_A, + .clk_name = "sclk_cam0", + .i2c_busnum = 0, + .cam_power = smdkv310_cam0_reset, +#endif +#ifdef CONFIG_ITU_B + .id = CAMERA_PAR_B, + .clk_name = "sclk_cam1", + .i2c_busnum = 1, + .cam_power = smdkv310_cam1_reset, +#endif + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .info = &s5k4ba_i2c_info, + .pixelformat = V4L2_PIX_FMT_YUYV, + .srclk_name = "xusbxti", + .clk_rate = 24000000, + .line_length = 1920, + .width = 1600, + .height = 1200, + .window = { + .left = 0, + .top = 0, + .width = 1600, + .height = 1200, + }, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + .reset_camera = 1, + .initialized = 0, +}; +#endif + +/* 2 MIPI Cameras */ +#ifdef CONFIG_VIDEO_S5K4EA +static struct s5k4ea_platform_data s5k4ea_plat = { + .default_width = 1920, + .default_height = 1080, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 1, +}; + +static struct i2c_board_info s5k4ea_i2c_info = { + I2C_BOARD_INFO("S5K4EA", 0x2d), + .platform_data = &s5k4ea_plat, +}; + +static struct s3c_platform_camera s5k4ea = { +#ifdef CONFIG_CSI_C + .id = CAMERA_CSI_C, + .clk_name = "sclk_cam0", + .i2c_busnum = 0, + .cam_power = smdkv310_cam0_reset, +#endif +#ifdef CONFIG_CSI_D + .id = CAMERA_CSI_D, + .clk_name = "sclk_cam1", + .i2c_busnum = 1, + .cam_power = smdkv310_mipi_cam1_reset, +#endif + .type = CAM_TYPE_MIPI, + .fmt = MIPI_CSI_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .info = &s5k4ea_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "mout_mpll", + .clk_rate = 48000000, + .line_length = 1920, + .width = 1920, + .height = 1080, + .window = { + .left = 0, + .top = 0, + .width = 1920, + .height = 1080, + }, + + .mipi_lanes = 2, + .mipi_settle = 12, + .mipi_align = 32, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + + .initialized = 0, +}; +#endif + +#ifdef WRITEBACK_ENABLED +static struct i2c_board_info __initdata writeback_i2c_info = { + I2C_BOARD_INFO("WriteBack", 0x0), +}; + +static struct s3c_platform_camera writeback = { + .id = CAMERA_WB, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .i2c_busnum = 0, + .info = &writeback_i2c_info, + .pixelformat = V4L2_PIX_FMT_YUV444, + .line_length = 800, + .width = 480, + .height = 800, + .window = { + .left = 0, + .top = 0, + .width = 480, + .height = 800, + }, + + .initialized = 0, +}; +#endif + +/* legacy M5MOLS Camera driver configuration */ +#ifdef CONFIG_VIDEO_M5MO +#define CAM_CHECK_ERR_RET(x, msg) \ + if (unlikely((x) < 0)) { \ + printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x); \ + return x; \ + } +#define CAM_CHECK_ERR(x, msg) \ + if (unlikely((x) < 0)) { \ + printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x); \ + } + +static int m5mo_config_isp_irq(void) +{ + s3c_gpio_cfgpin(EXYNOS4_GPX0(5), S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(EXYNOS4_GPX0(5), S3C_GPIO_PULL_NONE); + return 0; +} + +static struct m5mo_platform_data m5mo_plat = { + .default_width = 640, /* 1920 */ + .default_height = 480, /* 1080 */ + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 1, + .config_isp_irq = m5mo_config_isp_irq, + .irq = IRQ_EINT(5), +}; + +static struct i2c_board_info m5mo_i2c_info = { + I2C_BOARD_INFO("M5MO", 0x1F), + .platform_data = &m5mo_plat, + .irq = IRQ_EINT(5), +}; + +static struct s3c_platform_camera m5mo = { +#ifdef CONFIG_CSI_C + .id = CAMERA_CSI_C, + .clk_name = "sclk_cam0", + .i2c_busnum = 0, + .cam_power = smdkv310_cam0_reset, +#endif +#ifdef CONFIG_CSI_D + .id = CAMERA_CSI_D, + .clk_name = "sclk_cam1", + .i2c_busnum = 1, + .cam_power = smdkv310_mipi_cam1_reset, +#endif + .type = CAM_TYPE_MIPI, + .fmt = MIPI_CSI_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_YCBYCR, + .info = &m5mo_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", /* "mout_mpll" */ + .clk_rate = 24000000, /* 48000000 */ + .line_length = 1920, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + .mipi_lanes = 2, + .mipi_settle = 12, + .mipi_align = 32, + + /* Polarity */ + .inv_pclk = 1, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + .reset_camera = 0, + .initialized = 0, +}; +#endif + +/* Interface setting */ +static struct s3c_platform_fimc fimc_plat = { +#ifdef CONFIG_ITU_A + .default_cam = CAMERA_PAR_A, +#endif +#ifdef CONFIG_ITU_B + .default_cam = CAMERA_PAR_B, +#endif +#ifdef CONFIG_CSI_C + .default_cam = CAMERA_CSI_C, +#endif +#ifdef CONFIG_CSI_D + .default_cam = CAMERA_CSI_D, +#endif +#ifdef WRITEBACK_ENABLED + .default_cam = CAMERA_WB, +#endif + .camera = { +#ifdef CONFIG_VIDEO_S5K4BA + &s5k4ba, +#endif +#ifdef CONFIG_VIDEO_S5K4EA + &s5k4ea, +#endif +#ifdef CONFIG_VIDEO_M5MO + &m5mo, +#endif +#ifdef WRITEBACK_ENABLED + &writeback, +#endif + }, + .hw_ver = 0x51, +}; +#endif /* CONFIG_VIDEO_FIMC */ + +/* for mainline fimc interface */ +#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC +#ifdef WRITEBACK_ENABLED +struct writeback_mbus_platform_data { + int id; + struct v4l2_mbus_framefmt fmt; +}; + +static struct i2c_board_info __initdata writeback_info = { + I2C_BOARD_INFO("writeback", 0x0), +}; +#endif + +#ifdef CONFIG_VIDEO_S5K4BA +static struct s5k4ba_mbus_platform_data s5k4ba_mbus_plat = { + .id = 0, + .fmt = { + .width = 1600, + .height = 1200, + /*.code = V4L2_MBUS_FMT_UYVY8_2X8,*/ + .code = V4L2_MBUS_FMT_VYUY8_2X8, + }, + .clk_rate = 24000000UL, +#ifdef CONFIG_ITU_A + .set_power = smdkv310_cam0_reset, +#endif +#ifdef CONFIG_ITU_B + .set_power = smdkv310_cam1_reset, +#endif +}; + +static struct i2c_board_info s5k4ba_info = { + I2C_BOARD_INFO("S5K4BA", 0x2d), + .platform_data = &s5k4ba_mbus_plat, +}; +#endif + +/* 2 MIPI Cameras */ +#ifdef CONFIG_VIDEO_S5K4EA +static struct s5k4ea_mbus_platform_data s5k4ea_mbus_plat = { +#ifdef CONFIG_CSI_C + .id = 0, + .set_power = smdkv310_cam0_reset, +#endif +#ifdef CONFIG_CSI_D + .id = 1, + .set_power = smdkv310_cam1_reset, +#endif + .fmt = { + .width = 1920, + .height = 1080, + .code = V4L2_MBUS_FMT_VYUY8_2X8, + }, + .clk_rate = 24000000UL, +}; + +static struct i2c_board_info s5k4ea_info = { + I2C_BOARD_INFO("S5K4EA", 0x2d), + .platform_data = &s5k4ea_mbus_plat, +}; +#endif + +#ifdef CONFIG_VIDEO_M5MOLS +static struct m5mols_platform_data m5mols_platdata = { +#ifdef CONFIG_CSI_C + .gpio_rst = EXYNOS4_GPX1(2), /* ISP_RESET */ +#endif +#ifdef CONFIG_CSI_D + .gpio_rst = EXYNOS4_GPX1(0), /* ISP_RESET */ +#endif + .enable_rst = true, /* positive reset */ + .irq = IRQ_EINT(5), +}; + +static struct i2c_board_info m5mols_board_info = { + I2C_BOARD_INFO("M5MOLS", 0x1F), + .platform_data = &m5mols_platdata, +}; + +#endif +#endif /* CONFIG_VIDEO_SAMSUNG_S5P_FIMC */ + +#ifdef CONFIG_EXYNOS4_DEV_DWMCI +static void exynos_dwmci_cfg_gpio(int width) +{ + unsigned int gpio; + + for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); + } + + switch (width) { + case MMC_BUS_WIDTH_8: + for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); + } + case MMC_BUS_WIDTH_4: + for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); + } + break; + case MMC_BUS_WIDTH_1: + gpio = EXYNOS4_GPK0(3); + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); + default: + break; + } +} + +static struct dw_mci_board exynos_dwmci_pdata __initdata = { + .num_slots = 1, + .quirks = DW_MCI_QUIRK_BROKEN_CARD_DETECTION | DW_MCI_QUIRK_HIGHSPEED, + .bus_hz = 80 * 1000 * 1000, + .caps = MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | + MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, + .fifo_depth = 0x20, + .detect_delay_ms = 200, + .hclk_name = "dwmci", + .cclk_name = "sclk_dwmci", + .cfg_gpio = exynos_dwmci_cfg_gpio, +}; +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = { .cd_type = S3C_SDHCI_CD_INTERNAL, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, @@ -96,14 +634,16 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = { .host_caps = MMC_CAP_8_BIT_DATA, #endif }; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_GPIO, - .ext_cd_gpio = EXYNOS4_GPK0(2), - .ext_cd_gpio_invert = 1, + .cd_type = S3C_SDHCI_CD_INTERNAL, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = { .cd_type = S3C_SDHCI_CD_INTERNAL, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, @@ -112,14 +652,253 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = { .host_caps = MMC_CAP_8_BIT_DATA, #endif }; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_GPIO, - .ext_cd_gpio = EXYNOS4_GPK2(2), - .ext_cd_gpio_invert = 1, + .cd_type = S3C_SDHCI_CD_INTERNAL, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; +#endif + +#ifdef CONFIG_S5P_DEV_MSHC +static struct s3c_mshci_platdata exynos4_mshc_pdata __initdata = { + .cd_type = S3C_MSHCI_CD_PERMANENT, + .has_wp_gpio = true, + .wp_gpio = 0xffffffff, +#if defined(CONFIG_EXYNOS4_MSHC_8BIT) && \ + defined(CONFIG_EXYNOS4_MSHC_DDR) + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA | MMC_CAP_1_8V_DDR | + MMC_CAP_UHS_DDR50, +#elif defined(CONFIG_EXYNOS4_MSHC_8BIT) + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#elif defined(CONFIG_EXYNOS4_MSHC_DDR) + .host_caps = MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50, +#endif +}; +#endif + +#ifdef CONFIG_VIDEO_FIMG2D +static struct fimg2d_platdata fimg2d_data __initdata = { + .hw_ver = 30, + .parent_clkname = "mout_g2d0", + .clkname = "sclk_fimg2d", + .gate_clkname = "fimg2d", + .clkrate = 267 * 1000000, /* 266 Mhz */ +}; +#endif + +#ifdef CONFIG_FB_S3C +#if defined(CONFIG_LCD_AMS369FG06) +static int lcd_power_on(struct lcd_device *ld, int enable) +{ + return 1; +} + +static int reset_lcd(struct lcd_device *ld) +{ + int err = 0; + + err = gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0"); + if (err) { + printk(KERN_ERR "failed to request GPX0 for " + "lcd reset control\n"); + return err; + } + gpio_set_value(EXYNOS4_GPX0(6), 0); + mdelay(1); + + gpio_set_value(EXYNOS4_GPX0(6), 1); + + gpio_free(EXYNOS4_GPX0(6)); + + return 1; +} + +static struct lcd_platform_data ams369fg06_platform_data = { + .reset = reset_lcd, + .power_on = lcd_power_on, + .lcd_enabled = 0, + .reset_delay = 100, /* 100ms */ +}; + +#define LCD_BUS_NUM 3 +#define DISPLAY_CS EXYNOS4_GPB(5) +#define DISPLAY_CLK EXYNOS4_GPB(4) +#define DISPLAY_SI EXYNOS4_GPB(7) + +static struct spi_board_info spi_board_info[] __initdata = { + { + .modalias = "ams369fg06", + .platform_data = (void *)&ams369fg06_platform_data, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + } +}; +static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = { + .sck = DISPLAY_CLK, + .mosi = DISPLAY_SI, + .miso = -1, + .num_chipselect = 1, +}; + +static struct platform_device s3c_device_spi_gpio = { + .name = "spi_gpio", + .id = LCD_BUS_NUM, + .dev = { + .parent = &s5p_device_fimd0.dev, + .platform_data = &ams369fg06_spi_gpio_data, + }, +}; + +static struct s3c_fb_pd_win smdkv310_fb_win0 = { + .win_mode = { + .left_margin = 9, + .right_margin = 9, + .upper_margin = 5, + .lower_margin = 5, + .hsync_len = 2, + .vsync_len = 2, + .xres = 480, + .yres = 800, + }, + .virtual_x = 480, + .virtual_y = 1600, + .width = 48, + .height = 80, + .max_bpp = 32, + .default_bpp = 24, +}; + +static struct s3c_fb_pd_win smdkv310_fb_win1 = { + .win_mode = { + .left_margin = 9, + .right_margin = 9, + .upper_margin = 5, + .lower_margin = 5, + .hsync_len = 2, + .vsync_len = 2, + .xres = 480, + .yres = 800, + }, + .virtual_x = 480, + .virtual_y = 1600, + .width = 48, + .height = 80, + .max_bpp = 32, + .default_bpp = 24, +}; + +static struct s3c_fb_pd_win smdkv310_fb_win2 = { + .win_mode = { + .left_margin = 9, + .right_margin = 9, + .upper_margin = 5, + .lower_margin = 5, + .hsync_len = 2, + .vsync_len = 2, + .xres = 480, + .yres = 800, + }, + .virtual_x = 480, + .virtual_y = 1600, + .width = 48, + .height = 80, + .max_bpp = 32, + .default_bpp = 24, +}; + +#elif defined(CONFIG_LCD_WA101S) +static void lcd_wa101s_set_power(struct plat_lcd_data *pd, + unsigned int power) +{ + if (power) { +#if !defined(CONFIG_BACKLIGHT_PWM) + gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0"); + gpio_free(EXYNOS4_GPD0(1)); +#endif + } else { +#if !defined(CONFIG_BACKLIGHT_PWM) + gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0"); + gpio_free(EXYNOS4_GPD0(1)); +#endif + } +} + +static struct plat_lcd_data smdkv310_lcd_wa101s_data = { + .set_power = lcd_wa101s_set_power, +}; + +static struct platform_device smdkv310_lcd_wa101s = { + .name = "platform-lcd", + .dev.parent = &s5p_device_fimd0.dev, + .dev.platform_data = &smdkv310_lcd_wa101s_data, +}; + +static struct s3c_fb_pd_win smdkv310_fb_win0 = { + .win_mode = { + .left_margin = 80, + .right_margin = 48, + .upper_margin = 14, + .lower_margin = 3, + .hsync_len = 32, + .vsync_len = 5, + .xres = 1360, /* real size : 1366 */ + .yres = 768, + }, + .virtual_x = 1360, /* real size : 1366 */ + .virtual_y = 768 * 2, + .width = 223, + .height = 125, + .max_bpp = 32, + .default_bpp = 24, +}; + +static struct s3c_fb_pd_win smdkv310_fb_win1 = { + .win_mode = { + .left_margin = 80, + .right_margin = 48, + .upper_margin = 14, + .lower_margin = 3, + .hsync_len = 32, + .vsync_len = 5, + .xres = 1360, /* real size : 1366 */ + .yres = 768, + }, + .virtual_x = 1360, /* real size : 1366 */ + .virtual_y = 768 * 2, + .width = 223, + .height = 125, + .max_bpp = 32, + .default_bpp = 24, +}; + +static struct s3c_fb_pd_win smdkv310_fb_win2 = { + .win_mode = { + .left_margin = 80, + .right_margin = 48, + .upper_margin = 14, + .lower_margin = 3, + .hsync_len = 32, + .vsync_len = 5, + .xres = 1360, /* real size : 1366 */ + .yres = 768, + }, + .virtual_x = 1360, /* real size : 1366 */ + .virtual_y = 768 * 2, + .width = 223, + .height = 125, + .max_bpp = 32, + .default_bpp = 24, +}; + +#elif defined(CONFIG_LCD_LTE480WV) static void lcd_lte480wv_set_power(struct plat_lcd_data *pd, unsigned int power) { @@ -129,9 +908,7 @@ static void lcd_lte480wv_set_power(struct plat_lcd_data *pd, gpio_free(EXYNOS4_GPD0(1)); #endif /* fire nRESET on power up */ - gpio_request(EXYNOS4_GPX0(6), "GPX0"); - - gpio_direction_output(EXYNOS4_GPX0(6), 1); + gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0"); mdelay(100); gpio_set_value(EXYNOS4_GPX0(6), 0); @@ -156,7 +933,7 @@ static struct plat_lcd_data smdkv310_lcd_lte480wv_data = { static struct platform_device smdkv310_lcd_lte480wv = { .name = "platform-lcd", .dev.parent = &s5p_device_fimd0.dev, - .dev.platform_data = &smdkv310_lcd_lte480wv_data, + .dev.platform_data = &smdkv310_lcd_lte480wv_data, }; static struct s3c_fb_pd_win smdkv310_fb_win0 = { @@ -170,16 +947,266 @@ static struct s3c_fb_pd_win smdkv310_fb_win0 = { .xres = 800, .yres = 480, }, + .virtual_x = 800, + .virtual_y = 960, + .width = 104, + .height = 62, + .max_bpp = 32, + .default_bpp = 24, +}; + +static struct s3c_fb_pd_win smdkv310_fb_win1 = { + .win_mode = { + .left_margin = 13, + .right_margin = 8, + .upper_margin = 7, + .lower_margin = 5, + .hsync_len = 3, + .vsync_len = 1, + .xres = 800, + .yres = 480, + }, + .virtual_x = 800, + .virtual_y = 960, + .width = 104, + .height = 62, + .max_bpp = 32, + .default_bpp = 24, +}; + +static struct s3c_fb_pd_win smdkv310_fb_win2 = { + .win_mode = { + .left_margin = 13, + .right_margin = 8, + .upper_margin = 7, + .lower_margin = 5, + .hsync_len = 3, + .vsync_len = 1, + .xres = 800, + .yres = 480, + }, + .virtual_x = 800, + .virtual_y = 960, + .width = 104, + .height = 62, .max_bpp = 32, .default_bpp = 24, }; +#endif static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = { +#if defined(CONFIG_LCD_AMS369FG06) || defined(CONFIG_LCD_WA101S) || \ + defined(CONFIG_LCD_LTE480WV) .win[0] = &smdkv310_fb_win0, + .win[1] = &smdkv310_fb_win1, + .win[2] = &smdkv310_fb_win2, +#endif + .default_win = 2, .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, +#if defined(CONFIG_LCD_AMS369FG06) + .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN | + VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, +#elif defined(CONFIG_LCD_WA101S) + .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_HSYNC | + VIDCON1_INV_VSYNC, +#elif defined(CONFIG_LCD_LTE480WV) .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, +#endif .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, }; +#endif + +#ifdef CONFIG_S3C64XX_DEV_SPI +static struct s3c64xx_spi_csinfo spi0_csi[] = { + [0] = { + .line = EXYNOS4_GPB(1), + .set_level = gpio_set_value, + .fb_delay = 0x0, + }, +}; + +static struct spi_board_info spi0_board_info[] __initdata = { + { + .modalias = "spidev", + .platform_data = NULL, + .max_speed_hz = 10*1000*1000, + .bus_num = 0, + .chip_select = 0, + .mode = SPI_MODE_0, + .controller_data = &spi0_csi[0], + } +}; + +static struct s3c64xx_spi_csinfo spi2_csi[] = { + [0] = { + .line = EXYNOS4_GPC1(2), + .set_level = gpio_set_value, + .fb_delay = 0x1, + }, +}; + +static struct spi_board_info spi2_board_info[] __initdata = { + { + .modalias = "spidev", + .platform_data = NULL, + .max_speed_hz = 10*1000*1000, + .bus_num = 2, + .chip_select = 0, + .mode = SPI_MODE_0, + .controller_data = &spi2_csi[0], + } +}; +#endif + +#ifdef CONFIG_FB_S5P +#ifdef CONFIG_FB_S5P_AMS369FG06 +static struct s3c_platform_fb ams369fg06_data __initdata = { + .hw_ver = 0x70, + .clk_name = "sclk_lcd", + .nr_wins = 5, + .default_win = CONFIG_FB_S5P_DEFAULT_WINDOW, + .swap = FB_SWAP_HWORD | FB_SWAP_WORD, +}; + +#define LCD_BUS_NUM 3 +#define DISPLAY_CS EXYNOS4_GPB(5) +#define DISPLAY_CLK EXYNOS4_GPB(4) +#define DISPLAY_SI EXYNOS4_GPB(7) + +static struct spi_board_info spi_board_info[] __initdata = { + { + .modalias = "ams369fg06", + .platform_data = NULL, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + } +}; +static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = { + .sck = DISPLAY_CLK, + .mosi = DISPLAY_SI, + .miso = -1, + .num_chipselect = 1, +}; + +static struct platform_device s3c_device_spi_gpio = { + .name = "spi_gpio", + .id = LCD_BUS_NUM, + .dev = { + .parent = &s3c_device_fb.dev, + .platform_data = &ams369fg06_spi_gpio_data, + }, +}; +#elif defined(CONFIG_FB_S5P_DUMMY_MIPI_LCD) +#define LCD_BUS_NUM 3 +#define DISPLAY_CS EXYNOS4_GPB(5) +#define DISPLAY_CLK EXYNOS4_GPB(4) +#define DISPLAY_SI EXYNOS4_GPB(7) + +static struct s3cfb_lcd dummy_mipi_lcd = { + .width = 480, + .height = 800, + .bpp = 24, + + .freq = 60, + + .timing = { + .h_fp = 0x16, + .h_bp = 0x16, + .h_sw = 0x2, + .v_fp = 0x28, + .v_fpe = 2, + .v_bp = 0x1, + .v_bpe = 1, + .v_sw = 3, + .cmd_allow_len = 4, + }, + + .polarity = { + .rise_vclk = 0, + .inv_hsync = 0, + .inv_vsync = 0, + .inv_vden = 0, + }, +}; + +static struct s3c_platform_fb fb_platform_data __initdata = { + .hw_ver = 0x70, + .clk_name = "fimd", + .nr_wins = 5, +#if defined(CONFIG_FB_S5P_DEFAULT_WINDOW) + .default_win = CONFIG_FB_S5P_DEFAULT_WINDOW, +#else + .default_win = 0, +#endif + .swap = FB_SWAP_HWORD | FB_SWAP_WORD, +}; + +static void lcd_cfg_gpio(void) +{ + return; +} + +static int reset_lcd(void) +{ + int err = 0; + /* fire nRESET on power off */ + err = gpio_request_one(EXYNOS4_GPX3(1), GPIOF_OUT_INIT_HIGH, "GPX3"); + if (err) { + printk(KERN_ERR "failed to request GPX0 for " + "lcd reset control\n"); + return err; + } + mdelay(100); + + gpio_set_value(EXYNOS4_GPX3(1), 0); + mdelay(100); + gpio_set_value(EXYNOS4_GPX3(1), 1); + mdelay(100); + gpio_free(EXYNOS4_GPX3(1)); + + return 0; +} + +static int lcd_power_on(void *pdev, int enable) +{ + return 1; +} + +static void __init mipi_fb_init(void) +{ + struct s5p_platform_dsim *dsim_pd = NULL; + struct mipi_ddi_platform_data *mipi_ddi_pd = NULL; + struct dsim_lcd_config *dsim_lcd_info = NULL; + + /* gpio pad configuration for rgb and spi interface. */ + lcd_cfg_gpio(); + + /* register lcd panel data. */ + dsim_pd = (struct s5p_platform_dsim *) + s5p_device_dsim.dev.platform_data; + + strcpy(dsim_pd->lcd_panel_name, "dummy_mipi_lcd"); + + dsim_lcd_info = dsim_pd->dsim_lcd_info; + dsim_lcd_info->lcd_panel_info = (void *)&dummy_mipi_lcd; + + mipi_ddi_pd = (struct mipi_ddi_platform_data *) + dsim_lcd_info->mipi_ddi_pd; + mipi_ddi_pd->lcd_reset = reset_lcd; + mipi_ddi_pd->lcd_power_on = lcd_power_on; + + platform_device_register(&s5p_device_dsim); + + s3cfb_set_platdata(&fb_platform_data); + + printk(KERN_INFO "platform data of %s lcd panel has been registered.\n", + dsim_pd->lcd_panel_name); +} +#endif +#endif static struct resource smdkv310_smsc911x_resources[] = { [0] = { @@ -212,6 +1239,409 @@ static struct platform_device smdkv310_smsc911x = { }, }; +/* max8649 */ +static struct regulator_consumer_supply max8952_supply = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply max8649_supply = + REGULATOR_SUPPLY("vdd_int", NULL); + +static struct regulator_consumer_supply max8649a_supply = + REGULATOR_SUPPLY("vdd_g3d", NULL); + +static struct regulator_init_data max8952_init_data = { + .constraints = { + .name = "vdd_arm range", + .min_uV = 770000, + .max_uV = 1400000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .uV = 1200000, + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8952_supply, +}; + +static struct regulator_init_data max8649_init_data = { + .constraints = { + .name = "vdd_int range", + .min_uV = 750000, + .max_uV = 1380000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .uV = 1100000, + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8649_supply, +}; + +static struct regulator_init_data max8649a_init_data = { + .constraints = { + .name = "vdd_g3d range", + .min_uV = 750000, + .max_uV = 1380000, + .always_on = 0, + .boot_on = 0, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 1200000, + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8649a_supply, +}; + +static struct max8649_platform_data exynos4_max8952_info = { + .mode = 3, /* VID1 = 1, VID0 = 1 */ + .extclk = 0, + .ramp_timing = MAX8649_RAMP_32MV, + .regulator = &max8952_init_data, +}; + +static struct max8649_platform_data exynos4_max8649_info = { + .mode = 2, /* VID1 = 1, VID0 = 0 */ + .extclk = 0, + .ramp_timing = MAX8649_RAMP_32MV, + .regulator = &max8649_init_data, +}; + +static struct max8649_platform_data exynos4_max8649a_info = { + .mode = 2, /* VID1 = 1, VID0 = 0 */ + .extclk = 0, + .ramp_timing = MAX8649_RAMP_32MV, + .regulator = &max8649a_init_data, +}; + +/* max8997 */ +static struct regulator_consumer_supply max8997_buck1 = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply max8997_buck2 = + REGULATOR_SUPPLY("vdd_int", NULL); + +static struct regulator_consumer_supply max8997_buck3 = + REGULATOR_SUPPLY("vdd_g3d", NULL); + +static struct regulator_init_data max8997_buck1_data = { + .constraints = { + .name = "vdd_arm range", + .min_uV = 925000, + .max_uV = 1350000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck1, +}; + +static struct regulator_init_data max8997_buck2_data = { + .constraints = { + .name = "vdd_int range", + .min_uV = 950000, + .max_uV = 1150000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck2, +}; + +static struct regulator_init_data max8997_buck3_data = { + .constraints = { + .name = "vdd_g3d range", + .min_uV = 950000, + .max_uV = 1150000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck3, +}; + +static struct max8997_regulator_data max8997_regulators[] = { + { MAX8997_BUCK1, &max8997_buck1_data, }, + { MAX8997_BUCK2, &max8997_buck2_data, }, + { MAX8997_BUCK3, &max8997_buck3_data, }, +}; + +static struct max8997_platform_data exynos4_max8997_info = { + .num_regulators = ARRAY_SIZE(max8997_regulators), + .regulators = max8997_regulators, + + .buck1_voltage[0] = 1350000, /* 1.35V */ + .buck1_voltage[1] = 1300000, /* 1.3V */ + .buck1_voltage[2] = 1250000, /* 1.25V */ + .buck1_voltage[3] = 1200000, /* 1.2V */ + .buck1_voltage[4] = 1150000, /* 1.15V */ + .buck1_voltage[5] = 1100000, /* 1.1V */ + .buck1_voltage[6] = 1000000, /* 1.0V */ + .buck1_voltage[7] = 950000, /* 0.95V */ + + .buck2_voltage[0] = 1100000, /* 1.1V */ + .buck2_voltage[1] = 1000000, /* 1.0V */ + .buck2_voltage[2] = 950000, /* 0.95V */ + .buck2_voltage[3] = 900000, /* 0.9V */ + .buck2_voltage[4] = 1100000, /* 1.1V */ + .buck2_voltage[5] = 1000000, /* 1.0V */ + .buck2_voltage[6] = 950000, /* 0.95V */ + .buck2_voltage[7] = 900000, /* 0.9V */ + + .buck5_voltage[0] = 1100000, /* 1.1V */ + .buck5_voltage[1] = 1100000, /* 1.1V */ + .buck5_voltage[2] = 1100000, /* 1.1V */ + .buck5_voltage[3] = 1100000, /* 1.1V */ + .buck5_voltage[4] = 1100000, /* 1.1V */ + .buck5_voltage[5] = 1100000, /* 1.1V */ + .buck5_voltage[6] = 1100000, /* 1.1V */ + .buck5_voltage[7] = 1100000, /* 1.1V */ +}; + +#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS +static struct regulator_consumer_supply mipi_csi_fixed_voltage_supplies[] = { + REGULATOR_SUPPLY("mipi_csi", "s5p-mipi-csis.0"), + REGULATOR_SUPPLY("mipi_csi", "s5p-mipi-csis.1"), +}; + +static struct regulator_init_data mipi_csi_fixed_voltage_init_data = { + .constraints = { + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(mipi_csi_fixed_voltage_supplies), + .consumer_supplies = mipi_csi_fixed_voltage_supplies, +}; + +static struct fixed_voltage_config mipi_csi_fixed_voltage_config = { + .supply_name = "DC_5V", + .microvolts = 5000000, + .gpio = -EINVAL, + .init_data = &mipi_csi_fixed_voltage_init_data, +}; + +static struct platform_device mipi_csi_fixed_voltage = { + .name = "reg-fixed-voltage", + .id = 3, + .dev = { + .platform_data = &mipi_csi_fixed_voltage_config, + }, +}; +#endif + +#ifdef CONFIG_VIDEO_M5MOLS +static struct regulator_consumer_supply m5mols_fixed_voltage_supplies[] = { + REGULATOR_SUPPLY("core", NULL), + REGULATOR_SUPPLY("dig_18", NULL), + REGULATOR_SUPPLY("d_sensor", NULL), + REGULATOR_SUPPLY("dig_28", NULL), + REGULATOR_SUPPLY("a_sensor", NULL), + REGULATOR_SUPPLY("dig_12", NULL), +}; + +static struct regulator_init_data m5mols_fixed_voltage_init_data = { + .constraints = { + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(m5mols_fixed_voltage_supplies), + .consumer_supplies = m5mols_fixed_voltage_supplies, +}; + +static struct fixed_voltage_config m5mols_fixed_voltage_config = { + .supply_name = "CAM_SENSOR", + .microvolts = 1800000, + .gpio = -EINVAL, + .init_data = &m5mols_fixed_voltage_init_data, +}; + +static struct platform_device m5mols_fixed_voltage = { + .name = "reg-fixed-voltage", + .id = 4, + .dev = { + .platform_data = &m5mols_fixed_voltage_config, + }, +}; +#endif + +static struct gpio_event_direct_entry smdkv310_keypad_key_map[] = { + { + .gpio = EXYNOS4_GPX0(0), + .code = KEY_POWER, + } +}; + +static struct gpio_event_input_info smdkv310_keypad_key_info = { + .info.func = gpio_event_input_func, + .info.no_suspend = true, + .debounce_time.tv64 = 5 * NSEC_PER_MSEC, + .type = EV_KEY, + .keymap = smdkv310_keypad_key_map, + .keymap_size = ARRAY_SIZE(smdkv310_keypad_key_map) +}; + +static struct gpio_event_info *smdkv310_input_info[] = { + &smdkv310_keypad_key_info.info, +}; + +static struct gpio_event_platform_data smdkv310_input_data = { + .names = { + "smdkv310-keypad", + NULL, + }, + .info = smdkv310_input_info, + .info_count = ARRAY_SIZE(smdkv310_input_info), +}; + +static struct platform_device smdkv310_input_device = { + .name = GPIO_EVENT_DEV_NAME, + .id = 0, + .dev = { + .platform_data = &smdkv310_input_data, + }, +}; + +#ifdef CONFIG_WAKEUP_ASSIST +static struct platform_device wakeup_assist_device = { + .name = "wakeup_assist", +}; +#endif + +static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = { + REGULATOR_SUPPLY("AVDD2", "1-001a"), + REGULATOR_SUPPLY("CPVDD", "1-001a"), +}; + +static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = { + REGULATOR_SUPPLY("SPKVDD1", "1-001a"), + REGULATOR_SUPPLY("SPKVDD2", "1-001a"), +}; + +static struct regulator_consumer_supply wm8994_fixed_voltage2_supplies = + REGULATOR_SUPPLY("DBVDD", "1-001a"); + +static struct regulator_init_data wm8994_fixed_voltage0_init_data = { + .constraints = { + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies), + .consumer_supplies = wm8994_fixed_voltage0_supplies, +}; + +static struct regulator_init_data wm8994_fixed_voltage1_init_data = { + .constraints = { + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies), + .consumer_supplies = wm8994_fixed_voltage1_supplies, +}; + +static struct regulator_init_data wm8994_fixed_voltage2_init_data = { + .constraints = { + .always_on = 1, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &wm8994_fixed_voltage2_supplies, +}; + +static struct fixed_voltage_config wm8994_fixed_voltage0_config = { + .supply_name = "VDD_1.8V", + .microvolts = 1800000, + .gpio = -EINVAL, + .init_data = &wm8994_fixed_voltage0_init_data, +}; + +static struct fixed_voltage_config wm8994_fixed_voltage1_config = { + .supply_name = "DC_5V", + .microvolts = 5000000, + .gpio = -EINVAL, + .init_data = &wm8994_fixed_voltage1_init_data, +}; + +static struct fixed_voltage_config wm8994_fixed_voltage2_config = { + .supply_name = "VDD_3.3V", + .microvolts = 3300000, + .gpio = -EINVAL, + .init_data = &wm8994_fixed_voltage2_init_data, +}; + +static struct platform_device wm8994_fixed_voltage0 = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &wm8994_fixed_voltage0_config, + }, +}; + +static struct platform_device wm8994_fixed_voltage1 = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &wm8994_fixed_voltage1_config, + }, +}; + +static struct platform_device wm8994_fixed_voltage2 = { + .name = "reg-fixed-voltage", + .id = 2, + .dev = { + .platform_data = &wm8994_fixed_voltage2_config, + }, +}; + +static struct regulator_consumer_supply wm8994_avdd1_supply = + REGULATOR_SUPPLY("AVDD1", "1-001a"); + +static struct regulator_consumer_supply wm8994_dcvdd_supply = + REGULATOR_SUPPLY("DCVDD", "1-001a"); + +static struct regulator_init_data wm8994_ldo1_data = { + .constraints = { + .name = "AVDD1", + }, + .num_consumer_supplies = 1, + .consumer_supplies = &wm8994_avdd1_supply, +}; + +static struct regulator_init_data wm8994_ldo2_data = { + .constraints = { + .name = "DCVDD", + }, + .num_consumer_supplies = 1, + .consumer_supplies = &wm8994_dcvdd_supply, +}; + +static struct wm8994_pdata wm8994_platform_data = { + /* configure gpio1 function: 0x0001(Logic level input/output) */ + .gpio_defaults[0] = 0x0001, + /* configure gpio3/4/5/7 function for AIF2 voice */ + .gpio_defaults[2] = 0x8100,/* BCLK2 in */ + .gpio_defaults[3] = 0x8100,/* LRCLK2 in */ + .gpio_defaults[4] = 0x8100,/* DACDAT2 in */ + /* configure gpio6 function: 0x0001(Logic level input/output) */ + .gpio_defaults[5] = 0x0001, + .gpio_defaults[6] = 0x0100,/* ADCDAT2 out */ + .ldo[0] = { 0, NULL, &wm8994_ldo1_data }, + .ldo[1] = { 0, NULL, &wm8994_ldo2_data }, +}; + static uint32_t smdkv310_keymap[] __initdata = { /* KEY(row, col, keycode) */ KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), @@ -231,11 +1661,67 @@ static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = { .cols = 8, }; +#ifdef CONFIG_BATTERY_SAMSUNG +static struct platform_device samsung_device_battery = { + .name = "samsung-fake-battery", + .id = -1, +}; +#endif + +static struct i2c_board_info i2c_devs0[] __initdata = { + { + I2C_BOARD_INFO("max8649", 0x62), + .platform_data = &exynos4_max8649a_info, + }, { + I2C_BOARD_INFO("max8952", 0x60), + .platform_data = &exynos4_max8952_info, + }, { + I2C_BOARD_INFO("max8997", 0x66), + .platform_data = &exynos4_max8997_info, + } +}; + static struct i2c_board_info i2c_devs1[] __initdata = { - {I2C_BOARD_INFO("wm8994", 0x1a),}, + { + I2C_BOARD_INFO("wm8994", 0x1a), + .platform_data = &wm8994_platform_data, + }, { + I2C_BOARD_INFO("max8649", 0x60), + .platform_data = &exynos4_max8649_info, + }, +#ifdef CONFIG_VIDEO_TVOUT + { + I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)), + }, +#endif }; +#ifdef CONFIG_TOUCHSCREEN_S3C2410 +static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { + .delay = 10000, + .presc = 49, + .oversampling_shift = 2, + .cal_x_max = 480, + .cal_y_max = 800, + .cal_param = { + 33, -9156, 34720100, 14819, 57, -4234968, 65536 + }, +}; +#endif + +#ifdef CONFIG_S3C_DEV_HWMON +static struct s3c_hwmon_pdata smdkv310_hwmon_pdata __initdata = { + /* Reference voltage (1.2V) */ + .in[0] = &(struct s3c_hwmon_chcfg) { + .name = "smdk:reference-voltage", + .mult = 3300, + .div = 4096, + }, +}; +#endif + /* USB EHCI */ +#ifdef CONFIG_USB_EHCI_S5P static struct s5p_ehci_platdata smdkv310_ehci_pdata; static void __init smdkv310_ehci_init(void) @@ -244,27 +1730,85 @@ static void __init smdkv310_ehci_init(void) s5p_ehci_set_platdata(pdata); } +#endif + +#ifdef CONFIG_USB_OHCI_S5P +static struct s5p_ohci_platdata smdkv310_ohci_pdata; + +static void __init smdkv310_ohci_init(void) +{ + struct s5p_ohci_platdata *pdata = &smdkv310_ohci_pdata; + + s5p_ohci_set_platdata(pdata); +} +#endif +/* USB GADGET */ +#ifdef CONFIG_USB_GADGET +static struct s5p_usbgadget_platdata smdkv310_usbgadget_pdata; + +static void __init smdkv310_usbgadget_init(void) +{ + struct s5p_usbgadget_platdata *pdata = &smdkv310_usbgadget_pdata; + + s5p_usbgadget_set_platdata(pdata); +} +#endif + +#ifdef CONFIG_BUSFREQ_OPP +/* BUSFREQ to control memory/bus*/ +static struct device_domain busfreq; +#endif + +static struct platform_device exynos4_busfreq = { + .id = -1, + .name = "exynos-busfreq", +}; static struct platform_device *smdkv310_devices[] __initdata = { +#ifdef CONFIG_S3C_DEV_HSMMC &s3c_device_hsmmc0, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 &s3c_device_hsmmc1, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 &s3c_device_hsmmc2, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 &s3c_device_hsmmc3, +#endif +#ifdef CONFIG_S5P_DEV_MSHC + &s3c_device_mshci, +#endif +#ifdef CONFIG_EXYNOS4_DEV_DWMCI + &exynos_device_dwmci, +#endif + &s3c_device_i2c0, &s3c_device_i2c1, - &s5p_device_i2c_hdmiphy, + &s3c_device_adc, +#ifdef CONFIG_S3C_DEV_HWMON + &s3c_device_hwmon, +#endif +#ifdef CONFIG_TOUCHSCREEN_S3C2410 +#ifdef CONFIG_S3C_DEV_ADC + &s3c_device_ts, +#elif CONFIG_S3C_DEV_ADC1 + &s3c_device_ts1, +#endif +#endif &s3c_device_rtc, &s3c_device_wdt, - &s5p_device_ehci, - &s5p_device_fimc0, - &s5p_device_fimc1, - &s5p_device_fimc2, - &s5p_device_fimc3, - &exynos4_device_ac97, - &exynos4_device_i2s0, + &exynos_device_ac97, + &exynos_device_i2s0, + &exynos_device_pcm0, + &exynos_device_spdif, +#ifdef CONFIG_SND_SAMSUNG_RP + &exynos_device_srp, +#endif &samsung_device_keypad, - &s5p_device_mfc, - &s5p_device_mfc_l, - &s5p_device_mfc_r, +#ifdef CONFIG_BATTERY_SAMSUNG + &samsung_device_battery, +#endif &exynos4_device_pd[PD_MFC], &exynos4_device_pd[PD_G3D], &exynos4_device_pd[PD_LCD0], @@ -272,17 +1816,259 @@ static struct platform_device *smdkv310_devices[] __initdata = { &exynos4_device_pd[PD_CAM], &exynos4_device_pd[PD_TV], &exynos4_device_pd[PD_GPS], - &exynos4_device_spdif, - &exynos4_device_sysmmu, +#ifdef CONFIG_S5P_SYSTEM_MMU + &SYSMMU_PLATDEV(sss), + &SYSMMU_PLATDEV(fimc0), + &SYSMMU_PLATDEV(fimc1), + &SYSMMU_PLATDEV(fimc2), + &SYSMMU_PLATDEV(fimc3), + &SYSMMU_PLATDEV(jpeg), + &SYSMMU_PLATDEV(fimd0), + &SYSMMU_PLATDEV(fimd1), + &SYSMMU_PLATDEV(pcie), + &SYSMMU_PLATDEV(2d), + &SYSMMU_PLATDEV(rot), + &SYSMMU_PLATDEV(mdma), + &SYSMMU_PLATDEV(tv), + &SYSMMU_PLATDEV(mfc_l), + &SYSMMU_PLATDEV(mfc_r), +#endif +#ifdef CONFIG_ION_EXYNOS + &exynos_device_ion, +#endif + &wm8994_fixed_voltage0, + &wm8994_fixed_voltage1, + &wm8994_fixed_voltage2, &samsung_asoc_dma, &samsung_asoc_idma, +#ifdef CONFIG_S3C64XX_DEV_SPI + &exynos_device_spi0, + &exynos_device_spi2, +#endif +/* mainline fimd */ +#ifdef CONFIG_FB_S3C &s5p_device_fimd0, +#if defined(CONFIG_LCD_AMS369FG06) + &s3c_device_spi_gpio, +#elif defined(CONFIG_LCD_WA101S) + &smdkv310_lcd_wa101s, +#elif defined(CONFIG_LCD_LTE480WV) &smdkv310_lcd_lte480wv, +#endif +#endif +/* legacy fimd */ +#ifdef CONFIG_FB_S5P + &s3c_device_fb, +#ifdef CONFIG_FB_S5P_AMS369FG06 + &s3c_device_spi_gpio, +#endif +#endif +#ifdef CONFIG_VIDEO_TVOUT + &s5p_device_tvout, + &s5p_device_cec, + &s5p_device_hpd, +#endif &smdkv310_smsc911x, + &smdkv310_input_device, +#ifdef CONFIG_WAKEUP_ASSIST + &wakeup_assist_device, +#endif +#ifdef CONFIG_VIDEO_FIMC + &s3c_device_fimc0, + &s3c_device_fimc1, + &s3c_device_fimc2, + &s3c_device_fimc3, +#endif +#ifdef CONFIG_VIDEO_FIMC_MIPI + &s3c_device_csis0, + &s3c_device_csis1, +#endif +/* CONFIG_VIDEO_SAMSUNG_S5P_FIMC & CONFIG_VIDEO_SAMSUNG_S5P_FIMC are the + * feature for mainline */ +#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC + &s5p_device_fimc0, + &s5p_device_fimc1, + &s5p_device_fimc2, + &s5p_device_fimc3, +#endif +#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS + &s5p_device_mipi_csis0, + &s5p_device_mipi_csis1, +#endif + +#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS + &mipi_csi_fixed_voltage, +#endif +#ifdef CONFIG_VIDEO_M5MOLS + &m5mols_fixed_voltage, +#endif + +#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) + &s5p_device_mfc, +#endif +#ifdef CONFIG_VIDEO_FIMG2D + &s5p_device_fimg2d, +#endif +#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR + &exynos_device_rotator, +#endif +#ifdef CONFIG_VIDEO_JPEG + &s5p_device_jpeg, +#endif +#ifdef CONFIG_USB_EHCI_S5P + &s5p_device_ehci, +#endif +#ifdef CONFIG_USB_OHCI_S5P + &s5p_device_ohci, +#endif +#ifdef CONFIG_USB_GADGET + &s3c_device_usbgadget, +#endif +#ifdef CONFIG_USB_ANDROID_RNDIS + &s3c_device_rndis, +#endif +#ifdef CONFIG_USB_ANDROID + &s3c_device_android_usb, + &s3c_device_usb_mass_storage, +#endif +#ifdef CONFIG_EXYNOS4_SETUP_THERMAL + &s5p_device_tmu, +#endif +#ifdef CONFIG_SATA_AHCI_PLATFORM &exynos4_device_ahci, - &s5p_device_hdmi, - &s5p_device_mixer, +#endif +#ifdef CONFIG_S5P_DEV_ACE + &s5p_device_ace, +#endif + &exynos4_busfreq, +}; + +#if defined(CONFIG_VIDEO_TVOUT) +static struct s5p_platform_hpd hdmi_hpd_data __initdata = { + +}; +static struct s5p_platform_cec hdmi_cec_data __initdata = { + }; +#endif + +static void __init smdkv310_button_init(void) +{ + s3c_gpio_cfgpin(EXYNOS4_GPX0(0), (0xf << 0)); + s3c_gpio_setpull(EXYNOS4_GPX0(0), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(EXYNOS4_GPX3(7), (0xf << 28)); + s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); +} + +#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC +static struct s5p_fimc_isp_info isp_info[] = { +#if defined(CONFIG_VIDEO_S5K4BA) + { + .board_info = &s5k4ba_info, + .clk_frequency = 24000000UL, + .bus_type = FIMC_ITU_601, +#ifdef CONFIG_ITU_A + .i2c_bus_num = 0, + .mux_id = 0, /* A-Port : 0, B-Port : 1 */ +#endif +#ifdef CONFIG_ITU_B + .i2c_bus_num = 1, + .mux_id = 1, /* A-Port : 0, B-Port : 1 */ +#endif + .flags = FIMC_CLK_INV_VSYNC, + }, +#endif +#if defined(CONFIG_VIDEO_S5K4EA) + { + .board_info = &s5k4ea_info, + .clk_frequency = 24000000UL, + .bus_type = FIMC_MIPI_CSI2, +#ifdef CONFIG_CSI_C + .i2c_bus_num = 0, + .mux_id = 0, /* A-Port : 0, B-Port : 1 */ +#endif +#ifdef CONFIG_CSI_D + .i2c_bus_num = 1, + .mux_id = 1, /* A-Port : 0, B-Port : 1 */ +#endif + .flags = FIMC_CLK_INV_VSYNC, + .csi_data_align = 32, + }, +#endif +#if defined(CONFIG_VIDEO_M5MOLS) + { + .board_info = &m5mols_board_info, + .clk_frequency = 24000000UL, + .bus_type = FIMC_MIPI_CSI2, +#ifdef CONFIG_CSI_C + .i2c_bus_num = 0, + .mux_id = 0, /* A-Port : 0, B-Port : 1 */ +#endif +#ifdef CONFIG_CSI_D + .i2c_bus_num = 1, + .mux_id = 1, /* A-Port : 0, B-Port : 1 */ +#endif + .flags = FIMC_CLK_INV_PCLK | FIMC_CLK_INV_VSYNC, + .csi_data_align = 32, + }, +#endif + +#if defined(WRITEBACK_ENABLED) + { + .board_info = &writeback_info, + .bus_type = FIMC_LCD_WB, + .i2c_bus_num = 0, + .mux_id = 0, /* A-Port : 0, B-Port : 1 */ + .flags = FIMC_CLK_INV_VSYNC, + }, +#endif +}; + +static void __init smdkv310_subdev_config(void) +{ + s3c_fimc0_default_data.isp_info[0] = &isp_info[0]; + s3c_fimc0_default_data.isp_info[0]->use_cam = true; + /* support using two fimc as one sensore */ + { + static struct s5p_fimc_isp_info camcording; + memcpy(&camcording, &isp_info[0], sizeof(struct s5p_fimc_isp_info)); + s3c_fimc2_default_data.isp_info[0] = &camcording; + s3c_fimc2_default_data.isp_info[0]->use_cam = false; + } +} + +static void __init smdkv310_camera_config(void) +{ + int i = 0; + + /* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */ + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(EXYNOS4210_GPJ0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4210_GPJ0(i), S3C_GPIO_PULL_NONE); + } + /* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */ + for (i = 0; i < 5; i++) { + s3c_gpio_cfgpin(EXYNOS4210_GPJ1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4210_GPJ1(i), S3C_GPIO_PULL_NONE); + } + /* CAM B port(b0011) : DATA[0-7] */ + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(EXYNOS4210_GPE1(i), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(EXYNOS4210_GPE1(i), S3C_GPIO_PULL_NONE); + } + /* CAM B port(b0011) : PCLK, VSYNC, HREF, FIELD, CLCKOUT */ + for (i = 0; i < 5; i++) { + s3c_gpio_cfgpin(EXYNOS4210_GPE0(i), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(EXYNOS4210_GPE0(i), S3C_GPIO_PULL_NONE); + } + /* note : driver strength to max is unnecessary */ +#ifdef CONFIG_VIDEO_M5MOLS + s3c_gpio_cfgpin(EXYNOS4_GPX0(5), S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(EXYNOS4_GPX0(5), S3C_GPIO_PULL_NONE); +#endif +} +#endif static void __init smdkv310_smsc911x_init(void) { @@ -307,6 +2093,183 @@ static void __init smdkv310_smsc911x_init(void) (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); } +#if defined(CONFIG_CMA) +static void __init exynos4_reserve_mem(void) +{ + static struct cma_region regions[] = { +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG + { + .name = "jpeg", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG * SZ_1K, + .start = 0 + }, +#endif +#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP + { + .name = "srp", + .size = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K, + .start = 0, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D + { + .name = "fimg2d", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D * SZ_1K, + .start = 0 + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD + { + .name = "fimd", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K, + .start = 0 + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2 + { + .name = "fimc2", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2 * SZ_1K, + .start = 0 + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3 + { + .name = "fimc3", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3 * SZ_1K, + .start = 0 + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 + { + .name = "fimc0", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 * SZ_1K, + .start = 0 + }, +#endif +#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \ + defined(CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1) + { + .name = "fimc1", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL + { + .name = "mfc-normal", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL * SZ_1K, + { .alignment = 1 << 17 }, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 + { + .name = "mfc1", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 * SZ_1K, + { .alignment = 1 << 17 }, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 + { + .name = "mfc0", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 * SZ_1K, + { .alignment = 1 << 17 }, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC + { + .name = "mfc", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K, + { .alignment = 1 << 17 }, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_ROT + { + .name = "rot", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_ROT * SZ_1K, + .start = 0, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC + { + .name = "b2", + .size = 32 << 20, + { .alignment = 128 << 10 }, + }, + { + .name = "b1", + .size = 32 << 20, + { .alignment = 128 << 10 }, + }, + { + .name = "fw", + .size = 1 << 20, + { .alignment = 128 << 10 }, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT + { + .name = "tvout", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT * SZ_1K, + .start = 0 + }, +#endif + { + .size = 0 + }, + }; +#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION + static struct cma_region regions_secure[] = { +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 + { + .name = "fimc1", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE + { + .name = "mfc-secure", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE * SZ_1K, + { + .alignment = SZ_64M, + }, + }, +#endif + { + .size = 0 + }, + }; +#else /* !CONFIG_EXYNOS_CONTENT_PATH_PROTECTION */ + struct cma_region *regions_secure = NULL; +#endif + static const char map[] __initconst = + "s3cfb.0=fimd;exynos4-fb.0=fimd;" + "s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;s3c-fimc.3=fimc3;" + "exynos4210-fimc.0=fimc0;exynos4210-fimc.1=fimc1;exynos4210-fimc.2=fimc2;exynos4210-fimc.3=fimc3;" +#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR + "exynos-rot=rot;" +#endif +#ifdef CONFIG_VIDEO_MFC5X + "s3c-mfc/A=mfc0,mfc-secure;" + "s3c-mfc/B=mfc1,mfc-normal;" + "s3c-mfc/AB=mfc;" +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC + "s5p-mfc/f=fw;" + "s5p-mfc/a=b1;" + "s5p-mfc/b=b2;" +#endif + "samsung-rp=srp;" + "s5p-jpeg=jpeg;" + "s5p-fimg2d=fimg2d;" + "s5p-tvout=tvout;" + "s5p-smem/mfc=mfc0,mfc-secure;" + "s5p-smem/fimc=fimc1;" + "s5p-smem/mfc-shm=mfc1,mfc-normal;" + "ion-exynos=fimd,fimc0,fimc1,fimc2,fimc3,fw,b1,b2;"; + + s5p_cma_region_reserve(regions, regions_secure, SZ_64M, map); +} +#endif + /* LCD Backlight data */ static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = { .no = EXYNOS4_GPD0(1), @@ -315,74 +2278,401 @@ static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = { static struct platform_pwm_backlight_data smdkv310_bl_data = { .pwm_id = 1, +#if defined(CONFIG_LCD_LTE480WV) .pwm_period_ns = 1000, +#endif }; -static void s5p_tv_setup(void) -{ - /* direct HPD to HDMI chip */ - WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug")); - s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); - s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); - - /* setup dependencies between TV devices */ - s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev; - s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev; -} - static void __init smdkv310_map_io(void) { + clk_xusbxti.rate = 24000000; + s5p_init_io(NULL, 0, S5P_VA_CHIPID); s3c24xx_init_clocks(24000000); s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); + +#if defined(CONFIG_CMA) + exynos4_reserve_mem(); +#else + s5p_reserve_mem(S5P_RANGE_MFC); +#endif } -static void __init smdkv310_reserve(void) +static void __init exynos_sysmmu_init(void) { - s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); + ASSIGN_SYSMMU_POWERDOMAIN(fimc0, &exynos4_device_pd[PD_CAM].dev); + ASSIGN_SYSMMU_POWERDOMAIN(fimc1, &exynos4_device_pd[PD_CAM].dev); + ASSIGN_SYSMMU_POWERDOMAIN(fimc2, &exynos4_device_pd[PD_CAM].dev); + ASSIGN_SYSMMU_POWERDOMAIN(fimc3, &exynos4_device_pd[PD_CAM].dev); + ASSIGN_SYSMMU_POWERDOMAIN(jpeg, &exynos4_device_pd[PD_CAM].dev); + ASSIGN_SYSMMU_POWERDOMAIN(fimd0, &exynos4_device_pd[PD_LCD0].dev); + ASSIGN_SYSMMU_POWERDOMAIN(2d, &exynos4_device_pd[PD_LCD0].dev); + ASSIGN_SYSMMU_POWERDOMAIN(rot, &exynos4_device_pd[PD_LCD0].dev); + ASSIGN_SYSMMU_POWERDOMAIN(tv, &exynos4_device_pd[PD_TV].dev); + ASSIGN_SYSMMU_POWERDOMAIN(mfc_l, &exynos4_device_pd[PD_MFC].dev); + ASSIGN_SYSMMU_POWERDOMAIN(mfc_r, &exynos4_device_pd[PD_MFC].dev); +#if defined CONFIG_VIDEO_FIMC + sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s3c_device_fimc0.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s3c_device_fimc1.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s3c_device_fimc2.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s3c_device_fimc3.dev); +#elif defined CONFIG_VIDEO_SAMSUNG_S5P_FIMC + sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s5p_device_fimc0.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s5p_device_fimc1.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s5p_device_fimc2.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s5p_device_fimc3.dev); +#endif +#ifdef CONFIG_VIDEO_JPEG + sysmmu_set_owner(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev); +#endif +#ifdef CONFIG_FB_S3C + sysmmu_set_owner(&SYSMMU_PLATDEV(fimd0).dev, &s5p_device_fimd0.dev); +#endif +#ifdef CONFIG_VIDEO_FIMG2D + sysmmu_set_owner(&SYSMMU_PLATDEV(2d).dev, &s5p_device_fimg2d.dev); +#endif +#ifdef CONFIG_VIDEO_TVOUT + sysmmu_set_owner(&SYSMMU_PLATDEV(tv).dev, &s5p_device_tvout.dev); +#endif +#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) + sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_l).dev, &s5p_device_mfc.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_r).dev, &s5p_device_mfc.dev); +#endif +#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR + sysmmu_set_owner(&SYSMMU_PLATDEV(rot).dev, &exynos_device_rotator.dev); +#endif } static void __init smdkv310_machine_init(void) { +#ifdef CONFIG_S3C64XX_DEV_SPI + struct clk *sclk = NULL; + struct clk *prnt = NULL; + struct device *spi0_dev = &exynos_device_spi0.dev; + struct device *spi2_dev = &exynos_device_spi2.dev; +#endif +#if defined(CONFIG_FB_S5P_MIPI_DSIM) + mipi_fb_init(); +#endif + +#if defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME) + exynos_pd_disable(&exynos4_device_pd[PD_MFC].dev); + exynos_pd_disable(&exynos4_device_pd[PD_G3D].dev); + exynos_pd_disable(&exynos4_device_pd[PD_LCD0].dev); + exynos_pd_disable(&exynos4_device_pd[PD_LCD1].dev); + exynos_pd_disable(&exynos4_device_pd[PD_CAM].dev); + exynos_pd_disable(&exynos4_device_pd[PD_TV].dev); + exynos_pd_disable(&exynos4_device_pd[PD_GPS].dev); +#elif defined(CONFIG_EXYNOS_DEV_PD) + /* + * These power domains should be always on + * without runtime pm support. + */ + exynos_pd_enable(&exynos4_device_pd[PD_MFC].dev); + exynos_pd_enable(&exynos4_device_pd[PD_G3D].dev); + exynos_pd_enable(&exynos4_device_pd[PD_LCD0].dev); + exynos_pd_enable(&exynos4_device_pd[PD_LCD1].dev); + exynos_pd_enable(&exynos4_device_pd[PD_CAM].dev); + exynos_pd_enable(&exynos4_device_pd[PD_TV].dev); + exynos_pd_enable(&exynos4_device_pd[PD_GPS].dev); +#endif + s3c_i2c0_set_platdata(NULL); + i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); + s3c_i2c1_set_platdata(NULL); i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); + smdkv310_button_init(); smdkv310_smsc911x_init(); +#ifdef CONFIG_EXYNOS4_DEV_DWMCI + if (samsung_rev() != EXYNOS4210_REV_1_1) + exynos_dwmci_pdata.caps &= ~(MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR); + exynos_dwmci_set_platdata(&exynos_dwmci_pdata. 0); +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata); +#endif +#ifdef CONFIG_S5P_DEV_MSHC + s3c_mshci_set_platdata(&exynos4_mshc_pdata); +#endif +#ifdef CONFIG_S3C_DEV_HWMON + s3c_hwmon_set_platdata(&smdkv310_hwmon_pdata); +#endif - s5p_tv_setup(); - s5p_i2c_hdmiphy_set_platdata(NULL); +#ifdef CONFIG_FB_S3C + dev_set_name(&s5p_device_fimd0.dev, "s3cfb.0"); + clk_add_alias("lcd", "exynos4-fb.0", "lcd", &s5p_device_fimd0.dev); + clk_add_alias("sclk_fimd", "exynos4-fb.0", "sclk_fimd", &s5p_device_fimd0.dev); +#ifdef CONFIG_LCD_AMS369FG06 + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); +#endif + s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata); +#ifdef CONFIG_EXYNOS_DEV_PD + s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev; +#endif +#endif - samsung_keypad_set_platdata(&smdkv310_keypad_data); +#ifdef CONFIG_FB_S5P +#ifdef CONFIG_FB_S5P_AMS369FG06 + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); + s3cfb_set_platdata(&ams369fg06_data); +#elif defined(CONFIG_FB_S5P_DUMMY_MIPI_LCD) + exynos4_fimd0_gpio_setup_24bpp(); +#else + s3cfb_set_platdata(NULL); +#endif +#ifdef CONFIG_EXYNOS_DEV_PD + s3c_device_fb.dev.parent = &exynos4_device_pd[PD_LCD0].dev; +#endif +#endif +#ifdef CONFIG_EXYNOS_DEV_PD +#ifdef CONFIG_VIDEO_JPEG + s5p_device_jpeg.dev.parent = &exynos4_device_pd[PD_CAM].dev; +#endif +#ifdef CONFIG_FB_S5P_MIPI_DSIM + s5p_device_dsim.dev.parent = &exynos4_device_pd[PD_LCD0].dev; +#endif +#endif +#if defined(CONFIG_VIDEO_TVOUT) + s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data); + s5p_hdmi_cec_set_platdata(&hdmi_cec_data); +#ifdef CONFIG_EXYNOS_DEV_PD + s5p_device_tvout.dev.parent = &exynos4_device_pd[PD_TV].dev; +#endif +#endif samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data); - s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata); + samsung_keypad_set_platdata(&smdkv310_keypad_data); + +#ifdef CONFIG_TOUCHSCREEN_S3C2410 +#ifdef CONFIG_S3C_DEV_ADC + s3c24xx_ts_set_platdata(&s3c_ts_platform); +#endif +#ifdef CONFIG_S3C_DEV_ADC1 + s3c24xx_ts1_set_platdata(&s3c_ts_platform); +#endif +#endif +#ifdef CONFIG_VIDEO_FIMC + s3c_fimc0_set_platdata(&fimc_plat); + s3c_fimc1_set_platdata(NULL); + s3c_fimc2_set_platdata(&fimc_plat); + s3c_fimc3_set_platdata(NULL); +#ifdef CONFIG_EXYNOS_DEV_PD + s3c_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s3c_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s3c_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s3c_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev; +#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION + secmem.parent = &exynos4_device_pd[PD_CAM].dev; +#endif +#endif +#ifdef CONFIG_VIDEO_FIMC_MIPI + s3c_csis0_set_platdata(NULL); + s3c_csis1_set_platdata(NULL); +#ifdef CONFIG_EXYNOS_DEV_PD + s3c_device_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s3c_device_csis1.dev.parent = &exynos4_device_pd[PD_CAM].dev; +#endif +#endif +#if defined(CONFIG_ITU_A) || defined(CONFIG_CSI_C) + smdkv310_cam0_reset(1); +#endif +#if defined(CONFIG_ITU_B) || defined(CONFIG_CSI_D) + smdkv310_cam1_reset(1); +#endif +#endif /* CONFIG_VIDEO_FIMC */ + +#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC + smdkv310_camera_config(); + smdkv310_subdev_config(); + + dev_set_name(&s5p_device_fimc0.dev, "s3c-fimc.0"); + dev_set_name(&s5p_device_fimc1.dev, "s3c-fimc.1"); + dev_set_name(&s5p_device_fimc2.dev, "s3c-fimc.2"); + dev_set_name(&s5p_device_fimc3.dev, "s3c-fimc.3"); + + clk_add_alias("fimc", "exynos4210-fimc.0", "fimc", &s5p_device_fimc0.dev); + clk_add_alias("sclk_fimc", "exynos4210-fimc.0", "sclk_fimc", + &s5p_device_fimc0.dev); + clk_add_alias("fimc", "exynos4210-fimc.1", "fimc", &s5p_device_fimc1.dev); + clk_add_alias("sclk_fimc", "exynos4210-fimc.1", "sclk_fimc", + &s5p_device_fimc1.dev); + clk_add_alias("fimc", "exynos4210-fimc.2", "fimc", &s5p_device_fimc2.dev); + clk_add_alias("sclk_fimc", "exynos4210-fimc.2", "sclk_fimc", + &s5p_device_fimc2.dev); + clk_add_alias("fimc", "exynos4210-fimc.3", "fimc", &s5p_device_fimc3.dev); + clk_add_alias("sclk_fimc", "exynos4210-fimc.3", "sclk_fimc", + &s5p_device_fimc3.dev); + + s3c_fimc_setname(0, "exynos4210-fimc"); + s3c_fimc_setname(1, "exynos4210-fimc"); + s3c_fimc_setname(2, "exynos4210-fimc"); + s3c_fimc_setname(3, "exynos4210-fimc"); + /* FIMC */ + s3c_set_platdata(&s3c_fimc0_default_data, + sizeof(s3c_fimc0_default_data), &s5p_device_fimc0); + s3c_set_platdata(&s3c_fimc1_default_data, + sizeof(s3c_fimc1_default_data), &s5p_device_fimc1); + s3c_set_platdata(&s3c_fimc2_default_data, + sizeof(s3c_fimc2_default_data), &s5p_device_fimc2); + s3c_set_platdata(&s3c_fimc3_default_data, + sizeof(s3c_fimc3_default_data), &s5p_device_fimc3); +#ifdef CONFIG_EXYNOS_DEV_PD + s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev; +#endif +#ifdef CONFIG_VIDEO_S5P_MIPI_CSIS + s3c_set_platdata(&s5p_mipi_csis0_default_data, + sizeof(s5p_mipi_csis0_default_data), &s5p_device_mipi_csis0); + s3c_set_platdata(&s5p_mipi_csis1_default_data, + sizeof(s5p_mipi_csis1_default_data), &s5p_device_mipi_csis1); +#ifdef CONFIG_EXYNOS_DEV_PD + s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s5p_device_mipi_csis1.dev.parent = &exynos4_device_pd[PD_CAM].dev; +#endif +#endif +#if defined(CONFIG_ITU_A) || defined(CONFIG_CSI_C) + smdkv310_cam0_reset(1); +#endif +#if defined(CONFIG_ITU_B) || defined(CONFIG_CSI_D) + smdkv310_cam1_reset(1); +#endif +#endif + +#ifdef CONFIG_ION_EXYNOS + exynos_ion_set_platdata(); +#endif + +#ifdef CONFIG_EXYNOS4_SETUP_THERMAL + s5p_tmu_set_platdata(NULL); +#endif + +#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) +#ifdef CONFIG_EXYNOS_DEV_PD + s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev; +#endif +#endif + +#if defined(CONFIG_VIDEO_MFC5X) + exynos4_mfc_setup_clock(&s5p_device_mfc.dev, 200 * MHZ); +#endif +#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) + dev_set_name(&s5p_device_mfc.dev, "s3c-mfc"); + clk_add_alias("mfc", "s5p-mfc", "mfc", &s5p_device_mfc.dev); + s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc"); +#endif + +#ifdef CONFIG_VIDEO_FIMG2D + s5p_fimg2d_set_platdata(&fimg2d_data); +#ifdef CONFIG_EXYNOS_DEV_PD + s5p_device_fimg2d.dev.parent = &exynos4_device_pd[PD_LCD0].dev; +#endif +#endif + +#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR + exynos_device_rotator.dev.parent = &exynos4_device_pd[PD_LCD0].dev; +#endif + +#ifdef CONFIG_USB_EHCI_S5P smdkv310_ehci_init(); - clk_xusbxti.rate = 24000000; +#endif +#ifdef CONFIG_USB_OHCI_S5P + smdkv310_ohci_init(); +#endif +#ifdef CONFIG_USB_GADGET + smdkv310_usbgadget_init(); +#endif + + exynos_sysmmu_init(); platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); - s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev; + +#ifdef CONFIG_FB_S3C + exynos4_fimd0_setup_clock(&s5p_device_fimd0.dev, "mout_mpll", + 800 * MHZ); +#endif + +#ifdef CONFIG_S3C64XX_DEV_SPI + sclk = clk_get(spi0_dev, "sclk_spi"); + if (IS_ERR(sclk)) + dev_err(spi0_dev, "failed to get sclk for SPI-0\n"); + + prnt = clk_get(spi0_dev, "mout_mpll"); + if (IS_ERR(prnt)) + dev_err(spi0_dev, "failed to get prnt\n"); + + if (!IS_ERR(sclk) && !IS_ERR(prnt)) + if (clk_set_parent(sclk, prnt)) + printk(KERN_ERR "Unable to set parent %s of clock %s.\n", + prnt->name, sclk->name); + clk_put(sclk); + clk_put(prnt); + + if (!gpio_request(EXYNOS4_GPB(1), "SPI_CS0")) { + gpio_direction_output(EXYNOS4_GPB(1), 1); + s3c_gpio_cfgpin(EXYNOS4_GPB(1), S3C_GPIO_SFN(1)); + s3c_gpio_setpull(EXYNOS4_GPB(1), S3C_GPIO_PULL_UP); + exynos_spi_set_info(0, EXYNOS_SPI_SRCCLK_SCLK, + ARRAY_SIZE(spi0_csi)); + } + spi_register_board_info(spi0_board_info, ARRAY_SIZE(spi0_board_info)); + + sclk = clk_get(spi2_dev, "sclk_spi"); + if (IS_ERR(sclk)) + dev_err(spi2_dev, "failed to get sclk for SPI-2\n"); + + prnt = clk_get(spi2_dev, "mout_mpll"); + if (IS_ERR(prnt)) + dev_err(spi2_dev, "failed to get prnt\n"); + + if (!IS_ERR(sclk) && !IS_ERR(prnt)) + if (clk_set_parent(sclk, prnt)) + printk(KERN_ERR "Unable to set parent %s of clock %s.\n", + prnt->name, sclk->name); + clk_put(sclk); + clk_put(prnt); + + if (!gpio_request(EXYNOS4_GPC1(2), "SPI_CS2")) { + gpio_direction_output(EXYNOS4_GPC1(2), 1); + s3c_gpio_cfgpin(EXYNOS4_GPC1(2), S3C_GPIO_SFN(1)); + s3c_gpio_setpull(EXYNOS4_GPC1(2), S3C_GPIO_PULL_UP); + exynos_spi_set_info(2, EXYNOS_SPI_SRCCLK_SCLK, + ARRAY_SIZE(spi2_csi)); + } + spi_register_board_info(spi2_board_info, ARRAY_SIZE(spi2_board_info)); +#endif +#ifdef CONFIG_BUSFREQ_OPP + dev_add(&busfreq, &exynos4_busfreq.dev); +#endif } -MACHINE_START(SMDKV310, "SMDKV310") +MACHINE_START(SMDKC210, "SMDKC210") /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ - .atag_offset = 0x100, + .boot_params = S5P_PA_SDRAM + 0x100, .init_irq = exynos4_init_irq, .map_io = smdkv310_map_io, .init_machine = smdkv310_machine_init, .timer = &exynos4_timer, - .reserve = &smdkv310_reserve, MACHINE_END -MACHINE_START(SMDKC210, "SMDKC210") +MACHINE_START(SMDKV310, "SMDKV310") /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - .atag_offset = 0x100, + /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ + .boot_params = S5P_PA_SDRAM + 0x100, .init_irq = exynos4_init_irq, .map_io = smdkv310_map_io, .init_machine = smdkv310_machine_init, |