diff options
Diffstat (limited to 'arch/arm/mach-s5p64x0')
| -rw-r--r-- | arch/arm/mach-s5p64x0/include/mach/pm-core.h | 117 | ||||
| -rw-r--r-- | arch/arm/mach-s5p64x0/irq-eint.c | 155 | ||||
| -rw-r--r-- | arch/arm/mach-s5p64x0/irq-pm.c | 92 | ||||
| -rw-r--r-- | arch/arm/mach-s5p64x0/pm.c | 204 | ||||
| -rw-r--r-- | arch/arm/mach-s5p64x0/setup-fb-24bpp.c | 29 |
5 files changed, 597 insertions, 0 deletions
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h new file mode 100644 index 0000000..e52f754 --- /dev/null +++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h @@ -0,0 +1,117 @@ +/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c + * + * Based on PM core support for S3C64XX by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <mach/regs-gpio.h> + +static inline void s3c_pm_debug_init_uart(void) +{ + u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK); + + /* + * As a note, since the S5P64X0 UARTs generally have multiple + * clock sources, we simply enable PCLK at the moment and hope + * that the resume settings for the UART are suitable for the + * use with PCLK. + */ + tmp |= S5P64X0_CLK_GATE_PCLK_UART0; + tmp |= S5P64X0_CLK_GATE_PCLK_UART1; + tmp |= S5P64X0_CLK_GATE_PCLK_UART2; + tmp |= S5P64X0_CLK_GATE_PCLK_UART3; + + __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK); + udelay(10); +} + +static inline void s3c_pm_arch_prepare_irqs(void) +{ + /* VIC should have already been taken care of */ + + /* clear any pending EINT0 interrupts */ + __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND); +} + +static inline void s3c_pm_arch_stop_clocks(void) { } +static inline void s3c_pm_arch_show_resume_irqs(void) { } + +/* + * make these defines, we currently do not have any need to change + * the IRQ wake controls depending on the CPU we are running on + */ +#define s3c_irqwake_eintallow ((1 << 16) - 1) +#define s3c_irqwake_intallow (~0) + +static inline void s3c_pm_arch_update_uart(void __iomem *regs, + struct pm_uart_save *save) +{ + u32 ucon = __raw_readl(regs + S3C2410_UCON); + u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK; + u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK; + u32 new_ucon; + u32 delta; + + /* + * S5P64X0 UART blocks only support level interrupts, so ensure that + * when we restore unused UART blocks we force the level interrupt + * settings. + */ + save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; + + /* + * We have a constraint on changing the clock type of the UART + * between UCLKx and PCLK, so ensure that when we restore UCON + * that the CLK field is correctly modified if the bootloader + * has changed anything. + */ + if (ucon_clk != save_clk) { + new_ucon = save->ucon; + delta = ucon_clk ^ save_clk; + + /* + * change from UCLKx => wrong PCLK, + * either UCLK can be tested for by a bit-test + * with UCLK0 + */ + if (ucon_clk & S3C6400_UCON_UCLK0 && + !(save_clk & S3C6400_UCON_UCLK0) && + delta & S3C6400_UCON_PCLK2) { + new_ucon &= ~S3C6400_UCON_UCLK0; + } else if (delta == S3C6400_UCON_PCLK2) { + /* + * as a precaution, don't change from + * PCLK2 => PCLK or vice-versa + */ + new_ucon ^= S3C6400_UCON_PCLK2; + } + + S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n", + ucon, new_ucon, save->ucon); + save->ucon = new_ucon; + } +} + +static inline void s3c_pm_restored_gpios(void) +{ + /* ensure sleep mode has been cleared from the system */ + __raw_writel(0, S5P64X0_SLPEN); +} + +static inline void samsung_pm_saved_gpios(void) +{ + /* + * turn on the sleep mode and keep it there, as it seems that during + * suspend the xCON registers get re-set and thus you can end up with + * problems between going to sleep and resuming. + */ + __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN); +} diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c new file mode 100644 index 0000000..275dc74 --- /dev/null +++ b/arch/arm/mach-s5p64x0/irq-eint.c @@ -0,0 +1,155 @@ +/* arch/arm/mach-s5p64x0/irq-eint.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd + * http://www.samsung.com/ + * + * Based on linux/arch/arm/mach-s3c64xx/irq-eint.c + * + * S5P64X0 - Interrupt handling for External Interrupts. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <plat/cpu.h> +#include <plat/regs-irqtype.h> +#include <plat/gpio-cfg.h> +#include <plat/pm.h> + +#include <mach/regs-gpio.h> +#include <mach/regs-clock.h> + +#define eint_offset(irq) ((irq) - IRQ_EINT(0)) + +static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type) +{ + int offs = eint_offset(data->irq); + int shift; + u32 ctrl, mask; + u32 newvalue = 0; + + if (offs > 15) + return -EINVAL; + + switch (type) { + case IRQ_TYPE_NONE: + printk(KERN_WARNING "No edge setting!\n"); + break; + case IRQ_TYPE_EDGE_RISING: + newvalue = S3C2410_EXTINT_RISEEDGE; + break; + case IRQ_TYPE_EDGE_FALLING: + newvalue = S3C2410_EXTINT_FALLEDGE; + break; + case IRQ_TYPE_EDGE_BOTH: + newvalue = S3C2410_EXTINT_BOTHEDGE; + break; + case IRQ_TYPE_LEVEL_LOW: + newvalue = S3C2410_EXTINT_LOWLEV; + break; + case IRQ_TYPE_LEVEL_HIGH: + newvalue = S3C2410_EXTINT_HILEV; + break; + default: + printk(KERN_ERR "No such irq type %d", type); + return -EINVAL; + } + + shift = (offs / 2) * 4; + mask = 0x7 << shift; + + ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask; + ctrl |= newvalue << shift; + __raw_writel(ctrl, S5P64X0_EINT0CON0); + + /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */ + if (soc_is_s5p6450()) + s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2)); + else + s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2)); + + return 0; +} + +/* + * s5p64x0_irq_demux_eint + * + * This function demuxes the IRQ from the group0 external interrupts, + * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into + * the specific handlers s5p64x0_irq_demux_eintX_Y. + */ +static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end) +{ + u32 status = __raw_readl(S5P64X0_EINT0PEND); + u32 mask = __raw_readl(S5P64X0_EINT0MASK); + unsigned int irq; + + status &= ~mask; + status >>= start; + status &= (1 << (end - start + 1)) - 1; + + for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { + if (status & 1) + generic_handle_irq(irq); + status >>= 1; + } +} + +static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +{ + s5p64x0_irq_demux_eint(0, 3); +} + +static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc) +{ + s5p64x0_irq_demux_eint(4, 11); +} + +static void s5p64x0_irq_demux_eint12_15(unsigned int irq, + struct irq_desc *desc) +{ + s5p64x0_irq_demux_eint(12, 15); +} + +static int s5p64x0_alloc_gc(void) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + + gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE, + S5P_VA_GPIO, handle_level_irq); + if (!gc) { + printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0" + "external interrupts failed\n", __func__); + return -EINVAL; + } + + ct = gc->chip_types; + ct->chip.irq_ack = irq_gc_ack_set_bit; + ct->chip.irq_mask = irq_gc_mask_set_bit; + ct->chip.irq_unmask = irq_gc_mask_clr_bit; + ct->chip.irq_set_type = s5p64x0_irq_eint_set_type; + ct->chip.irq_set_wake = s3c_irqext_wake; + ct->regs.ack = EINT0PEND_OFFSET; + ct->regs.mask = EINT0MASK_OFFSET; + irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); + return 0; +} + +static int __init s5p64x0_init_irq_eint(void) +{ + int ret = s5p64x0_alloc_gc(); + irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3); + irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11); + irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15); + + return ret; +} +arch_initcall(s5p64x0_init_irq_eint); diff --git a/arch/arm/mach-s5p64x0/irq-pm.c b/arch/arm/mach-s5p64x0/irq-pm.c new file mode 100644 index 0000000..3e6f245 --- /dev/null +++ b/arch/arm/mach-s5p64x0/irq-pm.c @@ -0,0 +1,92 @@ +/* linux/arch/arm/mach-s5p64x0/irq-pm.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5P64X0 - Interrupt handling Power Management + * + * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/syscore_ops.h> +#include <linux/serial_core.h> +#include <linux/io.h> + +#include <plat/regs-serial.h> +#include <plat/pm.h> + +#include <mach/regs-gpio.h> + +static struct sleep_save irq_save[] = { + SAVE_ITEM(S5P64X0_EINT0CON0), + SAVE_ITEM(S5P64X0_EINT0FLTCON0), + SAVE_ITEM(S5P64X0_EINT0FLTCON1), + SAVE_ITEM(S5P64X0_EINT0MASK), +}; + +static struct irq_grp_save { + u32 con; + u32 fltcon; + u32 mask; +} eint_grp_save[4]; + +static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS]; + +static int s5p64x0_irq_pm_suspend(void) +{ + struct irq_grp_save *grp = eint_grp_save; + int i; + + S3C_PMDBG("%s: suspending IRQs\n", __func__); + + s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); + + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) + irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM); + + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { + grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4)); + grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4)); + grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4)); + } + + return 0; +} + +static void s5p64x0_irq_pm_resume(void) +{ + struct irq_grp_save *grp = eint_grp_save; + int i; + + S3C_PMDBG("%s: resuming IRQs\n", __func__); + + s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); + + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) + __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM); + + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { + __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4)); + __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4)); + __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4)); + } + + S3C_PMDBG("%s: IRQ configuration restored\n", __func__); +} + +static struct syscore_ops s5p64x0_irq_syscore_ops = { + .suspend = s5p64x0_irq_pm_suspend, + .resume = s5p64x0_irq_pm_resume, +}; + +static int __init s5p64x0_syscore_init(void) +{ + register_syscore_ops(&s5p64x0_irq_syscore_ops); + + return 0; +} +core_initcall(s5p64x0_syscore_init); diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c new file mode 100644 index 0000000..6992724 --- /dev/null +++ b/arch/arm/mach-s5p64x0/pm.c @@ -0,0 +1,204 @@ +/* linux/arch/arm/mach-s5p64x0/pm.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5P64X0 Power Management Support + * + * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/suspend.h> +#include <linux/syscore_ops.h> +#include <linux/io.h> + +#include <plat/cpu.h> +#include <plat/pm.h> +#include <plat/regs-timer.h> +#include <plat/wakeup-mask.h> + +#include <mach/regs-clock.h> +#include <mach/regs-gpio.h> + +static struct sleep_save s5p64x0_core_save[] = { + SAVE_ITEM(S5P64X0_APLL_CON), + SAVE_ITEM(S5P64X0_MPLL_CON), + SAVE_ITEM(S5P64X0_EPLL_CON), + SAVE_ITEM(S5P64X0_EPLL_CON_K), + SAVE_ITEM(S5P64X0_CLK_SRC0), + SAVE_ITEM(S5P64X0_CLK_SRC1), + SAVE_ITEM(S5P64X0_CLK_DIV0), + SAVE_ITEM(S5P64X0_CLK_DIV1), + SAVE_ITEM(S5P64X0_CLK_DIV2), + SAVE_ITEM(S5P64X0_CLK_DIV3), + SAVE_ITEM(S5P64X0_CLK_GATE_MEM0), + SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1), + SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1), +}; + +static struct sleep_save s5p64x0_misc_save[] = { + SAVE_ITEM(S5P64X0_AHB_CON0), + SAVE_ITEM(S5P64X0_SPCON0), + SAVE_ITEM(S5P64X0_SPCON1), + SAVE_ITEM(S5P64X0_MEM0CONSLP0), + SAVE_ITEM(S5P64X0_MEM0CONSLP1), + SAVE_ITEM(S5P64X0_MEM0DRVCON), + SAVE_ITEM(S5P64X0_MEM1DRVCON), + + SAVE_ITEM(S3C64XX_TINT_CSTAT), +}; + +/* DPLL is present only in S5P6450 */ +static struct sleep_save s5p6450_core_save[] = { + SAVE_ITEM(S5P6450_DPLL_CON), + SAVE_ITEM(S5P6450_DPLL_CON_K), +}; + +void s3c_pm_configure_extint(void) +{ + __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK); +} + +void s3c_pm_restore_core(void) +{ + __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK); + + s3c_pm_do_restore_core(s5p64x0_core_save, + ARRAY_SIZE(s5p64x0_core_save)); + + if (soc_is_s5p6450()) + s3c_pm_do_restore_core(s5p6450_core_save, + ARRAY_SIZE(s5p6450_core_save)); + + s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save)); +} + +void s3c_pm_save_core(void) +{ + s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save)); + + if (soc_is_s5p6450()) + s3c_pm_do_save(s5p6450_core_save, + ARRAY_SIZE(s5p6450_core_save)); + + s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save)); +} + +static int s5p64x0_cpu_suspend(unsigned long arg) +{ + unsigned long tmp = 0; + + /* + * Issue the standby signal into the pm unit. Note, we + * issue a write-buffer drain just in case. + */ + asm("b 1f\n\t" + ".align 5\n\t" + "1:\n\t" + "mcr p15, 0, %0, c7, c10, 5\n\t" + "mcr p15, 0, %0, c7, c10, 4\n\t" + "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp)); + + /* we should never get past here */ + panic("sleep resumed to originator?"); +} + +/* mapping of interrupts to parts of the wakeup mask */ +static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = { + { .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWR_CFG_RTC_ALRM_DISABLE, }, + { .irq = IRQ_RTC_TIC, .bit = S5P64X0_PWR_CFG_RTC_TICK_DISABLE, }, + { .irq = IRQ_HSMMC0, .bit = S5P64X0_PWR_CFG_MMC0_DISABLE, }, + { .irq = IRQ_HSMMC1, .bit = S5P64X0_PWR_CFG_MMC1_DISABLE, }, +}; + +static void s5p64x0_pm_prepare(void) +{ + u32 tmp; + + samsung_sync_wakemask(S5P64X0_PWR_CFG, + s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs)); + + /* store the resume address in INFORM0 register */ + __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0); + + /* setup clock gating for FIMGVG block */ + __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \ + (S5P64X0_CLK_GATE_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1); + __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \ + (S5P64X0_CLK_GATE_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1); + + /* Configure the stabilization counter with wait time required */ + __raw_writel(S5P64X0_PWR_STABLE_PWR_CNT_VAL4, S5P64X0_PWR_STABLE); + + /* set WFI to SLEEP mode configuration */ + tmp = __raw_readl(S5P64X0_SLEEP_CFG); + tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN); + __raw_writel(tmp, S5P64X0_SLEEP_CFG); + + tmp = __raw_readl(S5P64X0_PWR_CFG); + tmp &= ~(S5P64X0_PWR_CFG_WFI_MASK); + tmp |= S5P64X0_PWR_CFG_WFI_SLEEP; + __raw_writel(tmp, S5P64X0_PWR_CFG); + + /* + * set OTHERS register to disable interrupt before going to + * sleep. This bit is present only in S5P6450, it is reserved + * in S5P6440. + */ + if (soc_is_s5p6450()) { + tmp = __raw_readl(S5P64X0_OTHERS); + tmp |= S5P6450_OTHERS_DISABLE_INT; + __raw_writel(tmp, S5P64X0_OTHERS); + } + + /* ensure previous wakeup state is cleared before sleeping */ + __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT); + +} + +static int s5p64x0_pm_add(struct sys_device *sysdev) +{ + pm_cpu_prep = s5p64x0_pm_prepare; + pm_cpu_sleep = s5p64x0_cpu_suspend; + pm_uart_udivslot = 1; + + return 0; +} + +static struct sysdev_driver s5p64x0_pm_driver = { + .add = s5p64x0_pm_add, +}; + +static __init int s5p64x0_pm_drvinit(void) +{ + s3c_pm_init(); + + return sysdev_driver_register(&s5p64x0_sysclass, &s5p64x0_pm_driver); +} +arch_initcall(s5p64x0_pm_drvinit); + +static void s5p64x0_pm_resume(void) +{ + u32 tmp; + + tmp = __raw_readl(S5P64X0_OTHERS); + tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \ + S5P64X0_OTHERS_RET_UART); + __raw_writel(tmp , S5P64X0_OTHERS); +} + +static struct syscore_ops s5p64x0_pm_syscore_ops = { + .resume = s5p64x0_pm_resume, +}; + +static __init int s5p64x0_pm_syscore_init(void) +{ + register_syscore_ops(&s5p64x0_pm_syscore_ops); + + return 0; +} +arch_initcall(s5p64x0_pm_syscore_init); diff --git a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c new file mode 100644 index 0000000..f346ee4 --- /dev/null +++ b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c @@ -0,0 +1,29 @@ +/* linux/arch/arm/mach-s5p64x0/setup-fb-24bpp.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base S5P64X0 GPIO setup information for LCD framebuffer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/fb.h> +#include <linux/gpio.h> + +#include <plat/cpu.h> +#include <plat/fb.h> +#include <plat/gpio-cfg.h> + +void s5p64x0_fb_gpio_setup_24bpp(void) +{ + if (soc_is_s5p6440()) { + s3c_gpio_cfgrange_nopull(S5P6440_GPI(0), 16, S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(S5P6440_GPJ(0), 12, S3C_GPIO_SFN(2)); + } else if (soc_is_s5p6450()) { + s3c_gpio_cfgrange_nopull(S5P6450_GPI(0), 16, S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(S5P6450_GPJ(0), 12, S3C_GPIO_SFN(2)); + } +} |