diff options
Diffstat (limited to 'arch/arm/plat-mxc/include')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/board-mx31ads.h | 33 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/devices-common.h | 10 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/eukrea-baseboards.h | 5 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/iomux-mx51.h | 59 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/iram.h | 41 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx25.h | 6 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx35.h | 6 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx51.h | 16 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/system.h | 32 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/uncompress.h | 1 |
10 files changed, 167 insertions, 42 deletions
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h new file mode 100644 index 0000000..94b60dd4 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h @@ -0,0 +1,33 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ +#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ + +#include <mach/hardware.h> + +/* + * These symbols are used by drivers/net/cs89x0.c. + * This is ugly as hell, but we have to provide them until + * someone fixed the driver. + */ + +/* Base address of PBC controller */ +#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT +/* Offsets for the PBC Controller register */ + +/* Ethernet Controller IO base address */ +#define PBC_CS8900A_IOBASE 0x020000 + +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) + +#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) + +#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 0498978..86d7575 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -108,7 +108,11 @@ struct platform_device *__init imx_add_spi_imx( const struct spi_imx_master *pdata); #include <mach/esdhc.h> -struct platform_device *__init imx_add_esdhc(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, +struct imx_esdhc_imx_data { + int id; + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_esdhc( + const struct imx_esdhc_imx_data *data, const struct esdhc_platform_data *pdata); diff --git a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h index 656acb4..a21d331 100644 --- a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h +++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h @@ -28,19 +28,22 @@ * its own devices, it calls baseboard's init function. * TODO: Add your own baseboard init function and call it from * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init() - * eukrea_cpuimx35_init() or eukrea_cpuimx51_init(). + * eukrea_cpuimx35_init() eukrea_cpuimx51_init() + * or eukrea_cpuimx51sd_init(). * * This example here is for the development board. Refer * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51 + * mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd */ extern void eukrea_mbimxsd25_baseboard_init(void); extern void eukrea_mbimx27_baseboard_init(void); extern void eukrea_mbimxsd35_baseboard_init(void); extern void eukrea_mbimx51_baseboard_init(void); +extern void eukrea_mbimxsd51_baseboard_init(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 5160f10..e46b1c2 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -47,6 +47,9 @@ typedef enum iomux_config { PAD_CTL_SRE_FAST) #define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ PAD_CTL_SRE_FAST) +#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \ + PAD_CTL_DVS) #define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) @@ -333,38 +336,50 @@ typedef enum iomux_config { #define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_SDHCI_PAD_CTRL) #define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) -#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) #define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_SDHCI_PAD_CTRL) #define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_SDHCI_PAD_CTRL) #define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_SDHCI_PAD_CTRL) #define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_SDHCI_PAD_CTRL) #define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \ + MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ 0x9b8, 3, MX51_I2C_PAD_CTRL) -#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ 0x9bc, 3, MX51_I2C_PAD_CTRL) #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) #endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iram.h b/arch/arm/plat-mxc/include/mach/iram.h new file mode 100644 index 0000000..022690c --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iram.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#include <linux/errno.h> + +#ifdef CONFIG_IRAM_ALLOC + +int __init iram_init(unsigned long base, unsigned long size); +void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr); +void iram_free(unsigned long dma_addr, unsigned int size); + +#else + +static inline int __init iram_init(unsigned long base, unsigned long size) +{ + return -ENOMEM; +} + +static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr) +{ + return NULL; +} + +static inline void iram_free(unsigned long base, unsigned long size) {} + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 153dd1b..cf46a45 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -54,6 +54,7 @@ #define MX25_ESDHC2_BASE_ADDR 0x53fb8000 #define MX25_LCDC_BASE_ADDR 0x53fbc000 #define MX25_KPP_BASE_ADDR 0x43fa8000 +#define MX25_SDMA_BASE_ADDR 0x53fd4000 #define MX25_OTG_BASE_ADDR 0x53ff4000 #define MX25_CSI_BASE_ADDR 0x53ff8000 @@ -61,8 +62,8 @@ #define MX25_INT_I2C1 3 #define MX25_INT_I2C2 4 #define MX25_INT_UART4 5 -#define MX25_INT_MMC_SDHC2 8 -#define MX25_INT_MMC_SDHC1 9 +#define MX25_INT_ESDHC2 8 +#define MX25_INT_ESDHC1 9 #define MX25_INT_I2C3 10 #define MX25_INT_SSI2 11 #define MX25_INT_SSI1 12 @@ -74,6 +75,7 @@ #define MX25_INT_DRYICE 25 #define MX25_INT_UART2 32 #define MX25_INT_NFC 33 +#define MX25_INT_SDMA 34 #define MX25_INT_LCDC 39 #define MX25_INT_UART5 40 #define MX25_INT_CAN1 43 diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index cb071b7..ff905cb 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -128,9 +128,9 @@ #define MX35_INT_I2C3 3 #define MX35_INT_I2C2 4 #define MX35_INT_RTIC 6 -#define MX35_INT_MMC_SDHC1 7 -#define MX35_INT_MMC_SDHC2 8 -#define MX35_INT_MMC_SDHC3 9 +#define MX35_INT_ESDHC1 7 +#define MX35_INT_ESDHC2 8 +#define MX35_INT_ESDHC3 9 #define MX35_INT_I2C1 10 #define MX35_INT_SSI1 11 #define MX35_INT_SSI2 12 diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index c54b5c3..2af7a10 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -64,13 +64,13 @@ #define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000 #define MX51_SPBA0_SIZE SZ_1M -#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) -#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) +#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) +#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) #define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) #define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) #define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) -#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) -#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) +#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) +#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) #define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000) #define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000) #define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000) @@ -280,10 +280,10 @@ */ #define MX51_MXC_INT_BASE 0 #define MX51_MXC_INT_RESV0 0 -#define MX51_MXC_INT_MMC_SDHC1 1 -#define MX51_MXC_INT_MMC_SDHC2 2 -#define MX51_MXC_INT_MMC_SDHC3 3 -#define MX51_MXC_INT_MMC_SDHC4 4 +#define MX51_INT_ESDHC1 1 +#define MX51_INT_ESDHC2 2 +#define MX51_INT_ESDHC3 3 +#define MX51_INT_ESDHC4 4 #define MX51_MXC_INT_RESV5 5 #define MX51_INT_SDMA 6 #define MX51_MXC_INT_IOMUX 7 diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index 4acd114..95be51b 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -1,7 +1,7 @@ /* * Copyright (C) 1999 ARM Limited * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,8 +28,34 @@ static inline void arch_idle(void) mxc91231_prepare_idle(); } #endif - - cpu_do_idle(); + /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */ + if (cpu_is_mx31() || cpu_is_mx35()) { + unsigned long reg = 0; + __asm__ __volatile__( + /* disable I and D cache */ + "mrc p15, 0, %0, c1, c0, 0\n" + "bic %0, %0, #0x00001000\n" + "bic %0, %0, #0x00000004\n" + "mcr p15, 0, %0, c1, c0, 0\n" + /* invalidate I cache */ + "mov %0, #0\n" + "mcr p15, 0, %0, c7, c5, 0\n" + /* clear and invalidate D cache */ + "mov %0, #0\n" + "mcr p15, 0, %0, c7, c14, 0\n" + /* WFI */ + "mov %0, #0\n" + "mcr p15, 0, %0, c7, c0, 4\n" + "nop\n" "nop\n" "nop\n" "nop\n" + "nop\n" "nop\n" "nop\n" + /* enable I and D cache */ + "mrc p15, 0, %0, c1, c0, 0\n" + "orr %0, %0, #0x00001000\n" + "orr %0, %0, #0x00000004\n" + "mcr p15, 0, %0, c1, c0, 0\n" + : "=r" (reg)); + } else + cpu_do_idle(); } void arch_reset(char mode, const char *cmd); diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index d9bd37e..9dd9c20 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -99,6 +99,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) uart_base = MX3X_UART2_BASE_ADDR; break; case MACH_TYPE_MX51_BABBAGE: + case MACH_TYPE_EUKREA_CPUIMX51SD: uart_base = MX51_UART1_BASE_ADDR; break; default: |