diff options
Diffstat (limited to 'arch/arm/plat-samsung/include')
37 files changed, 1813 insertions, 317 deletions
diff --git a/arch/arm/plat-samsung/include/plat/adc-core.h b/arch/arm/plat-samsung/include/plat/adc-core.h index a927bee..a281568 100644 --- a/arch/arm/plat-samsung/include/plat/adc-core.h +++ b/arch/arm/plat-samsung/include/plat/adc-core.h @@ -20,7 +20,7 @@ /* re-define device name depending on support. */ static inline void s3c_adc_setname(char *name) { -#if defined(CONFIG_SAMSUNG_DEV_ADC) || defined(CONFIG_PLAT_S3C24XX) +#ifdef CONFIG_SAMSUNG_DEV_ADC s3c_device_adc.name = name; #endif } diff --git a/arch/arm/plat-samsung/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h index b258a08..449f409 100644 --- a/arch/arm/plat-samsung/include/plat/adc.h +++ b/arch/arm/plat-samsung/include/plat/adc.h @@ -17,7 +17,8 @@ struct s3c_adc_client; extern int s3c_adc_start(struct s3c_adc_client *client, - unsigned int channel, unsigned int nr_samples); + unsigned int channel, unsigned int nr_samples, + wait_queue_head_t *pwake); extern int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch); diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h index aa9875f..bfee644 100644 --- a/arch/arm/plat-samsung/include/plat/audio.h +++ b/arch/arm/plat-samsung/include/plat/audio.h @@ -36,6 +36,10 @@ struct samsung_i2s { */ #define QUIRK_NO_MUXPSR (1 << 2) #define QUIRK_NEED_RSTCLR (1 << 3) +/* If the idma will be enabled */ +#define QUIRK_ENABLED_IDMA (1 << 4) +/* If the srp will be enabled */ +#define QUIRK_ENABLED_SRP (1 << 5) /* Quirks of the I2S controller */ u32 quirks; @@ -44,7 +48,6 @@ struct samsung_i2s { * Also corresponds to clocks of I2SMOD[10] */ const char **src_clk; - dma_addr_t idma_addr; }; /** @@ -57,3 +60,5 @@ struct s3c_audio_pdata { struct samsung_i2s i2s; } type; }; + +extern void __init exynos4_i2sv3_setup_resource(void); diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index 73c66d4..76198a7 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -84,6 +84,7 @@ extern struct clk clk_h2; extern struct clk clk_27m; extern struct clk clk_48m; extern struct clk clk_xusbxti; +extern struct clk clk_xxti; extern int clk_default_setrate(struct clk *clk, unsigned long rate); extern struct clk_ops clk_ops_def_setrate; diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 40fd7b6..8699823 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -25,11 +25,12 @@ extern unsigned long samsung_cpu_id; #define S3C6400_CPU_ID 0x36400000 #define S3C6410_CPU_ID 0x36410000 -#define S3C64XX_CPU_MASK 0xFFFFF000 +#define S3C64XX_CPU_ID (S3C6400_CPU_ID & S3C6410_CPU_ID) +#define S3C64XX_CPU_MASK 0x1FF40000 #define S5P6440_CPU_ID 0x56440000 #define S5P6450_CPU_ID 0x36450000 -#define S5P64XX_CPU_MASK 0xFFFFF000 +#define S5P64XX_CPU_MASK 0x1FF40000 #define S5PC100_CPU_ID 0x43100000 #define S5PC100_CPU_MASK 0xFFFFF000 @@ -40,7 +41,9 @@ extern unsigned long samsung_cpu_id; #define EXYNOS4210_CPU_ID 0x43210000 #define EXYNOS4212_CPU_ID 0x43220000 #define EXYNOS4412_CPU_ID 0xE4412200 -#define EXYNOS4_CPU_MASK 0xFFFE0000 +#define EXYNOS5210_CPU_ID 0x43510000 +#define EXYNOS5250_CPU_ID 0x43520000 +#define EXYNOS_CPU_MASK 0xFFFE0000 #define IS_SAMSUNG_CPU(name, id, mask) \ static inline int is_samsung_##name(void) \ @@ -49,15 +52,16 @@ static inline int is_samsung_##name(void) \ } IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK) -IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) -IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK) +IS_SAMSUNG_CPU(s3c64xx, S3C64XX_CPU_ID, S3C64XX_CPU_MASK) IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK) IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK) IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK) IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK) -IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) -IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) -IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) +IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS_CPU_MASK) +IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS_CPU_MASK) +IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS_CPU_MASK) +IS_SAMSUNG_CPU(exynos5210, EXYNOS5210_CPU_ID, EXYNOS_CPU_MASK) +IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_CPU_ID, EXYNOS_CPU_MASK) #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ @@ -69,7 +73,7 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) #endif #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) -# define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410()) +# define soc_is_s3c64xx() is_samsung_s3c64xx() #else # define soc_is_s3c64xx() 0 #endif @@ -104,21 +108,49 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) # define soc_is_exynos4210() 0 #endif -#if defined(CONFIG_SOC_EXYNOS4212) +#define EXYNOS4210_REV_0 (0x0) +#define EXYNOS4210_REV_1_0 (0x10) +#define EXYNOS4210_REV_1_1 (0x11) +#define EXYNOS4210_REV_1_2 (0x12) + +#if defined(CONFIG_CPU_EXYNOS4212) # define soc_is_exynos4212() is_samsung_exynos4212() #else # define soc_is_exynos4212() 0 #endif -#if defined(CONFIG_SOC_EXYNOS4412) +#define EXYNOS4212_REV_0 (0x0) +#define EXYNOS4212_REV_1_0 (0x10) + +#if defined(CONFIG_CPU_EXYNOS4412) # define soc_is_exynos4412() is_samsung_exynos4412() #else # define soc_is_exynos4412() 0 #endif -#define EXYNOS4210_REV_0 (0x0) -#define EXYNOS4210_REV_1_0 (0x10) -#define EXYNOS4210_REV_1_1 (0x11) +#define EXYNOS4412_REV_0 (0x0) +#define EXYNOS4412_REV_0_1 (0x01) +#define EXYNOS4412_REV_1_0 (0x10) +#define EXYNOS4412_REV_1_1 (0x11) +#define EXYNOS4412_REV_2_0 (0x20) + +#if defined(CONFIG_CPU_EXYNOS5210) +# define soc_is_exynos5210() is_samsung_exynos5210() +#else +# define soc_is_exynos5210() 0 +#endif + +#if defined(CONFIG_CPU_EXYNOS5250) +# define soc_is_exynos5250() is_samsung_exynos5250() +# define soc_is_exynos5250_rev1 (soc_is_exynos5250() && \ + samsung_rev() >= EXYNOS5250_REV_1_0) +#else +# define soc_is_exynos5250() 0 +# define soc_is_exynos5250_rev1 0 +#endif + +#define EXYNOS5250_REV_0 (0x0) +#define EXYNOS5250_REV_1_0 (0x10) #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } @@ -199,6 +231,7 @@ extern struct sysdev_class s3c64xx_sysclass; extern struct sysdev_class s5p64x0_sysclass; extern struct sysdev_class s5pv210_sysclass; extern struct sysdev_class exynos4_sysclass; +extern struct sysdev_class exynos5_sysclass; extern void (*s5pc1xx_idle)(void); diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S index f3a9cff..207e275 100644 --- a/arch/arm/plat-samsung/include/plat/debug-macro.S +++ b/arch/arm/plat-samsung/include/plat/debug-macro.S @@ -14,12 +14,12 @@ /* The S5PV210/S5PC110 implementations are as belows. */ .macro fifo_level_s5pv210 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] + ldr \rd, [ \rx, # S3C2410_UFSTAT ] and \rd, \rd, #S5PV210_UFSTAT_TXMASK .endm .macro fifo_full_s5pv210 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] + ldr \rd, [ \rx, # S3C2410_UFSTAT ] tst \rd, #S5PV210_UFSTAT_TXFULL .endm @@ -27,7 +27,7 @@ * most widely re-used */ .macro fifo_level_s3c2440 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] + ldr \rd, [ \rx, # S3C2410_UFSTAT ] and \rd, \rd, #S3C2440_UFSTAT_TXMASK .endm @@ -36,7 +36,7 @@ #endif .macro fifo_full_s3c2440 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] + ldr \rd, [ \rx, # S3C2410_UFSTAT ] tst \rd, #S3C2440_UFSTAT_TXFULL .endm @@ -45,11 +45,11 @@ #endif .macro senduart,rd,rx - strb \rd, [\rx, # S3C2410_UTXH] + strb \rd, [\rx, # S3C2410_UTXH ] .endm .macro busyuart, rd, rx - ldr \rd, [\rx, # S3C2410_UFCON] + ldr \rd, [ \rx, # S3C2410_UFCON ] tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? beq 1001f @ @ FIFO enabled... @@ -60,7 +60,7 @@ 1001: @ busy waiting for non fifo - ldr \rd, [\rx, # S3C2410_UTRSTAT] + ldr \rd, [ \rx, # S3C2410_UTRSTAT ] tst \rd, #S3C2410_UTRSTAT_TXFE beq 1001b @@ -68,7 +68,7 @@ .endm .macro waituart,rd,rx - ldr \rd, [\rx, # S3C2410_UFCON] + ldr \rd, [ \rx, # S3C2410_UFCON ] tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? beq 1001f @ @ FIFO enabled... @@ -79,7 +79,7 @@ b 1002f 1001: @ idle waiting for non fifo - ldr \rd, [\rx, # S3C2410_UTRSTAT] + ldr \rd, [ \rx, # S3C2410_UTRSTAT ] tst \rd, #S3C2410_UTRSTAT_TXFE beq 1001b diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index ab633c9..1321d7b 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -17,6 +17,7 @@ #define __PLAT_DEVS_H __FILE__ #include <linux/platform_device.h> +#include <linux/platform_data/exynos_usb3_drd.h> struct s3c24xx_uart_resources { struct resource *resources; @@ -30,24 +31,37 @@ extern struct s3c24xx_uart_resources s5p_uart_resources[]; extern struct platform_device *s3c24xx_uart_devs[]; extern struct platform_device *s3c24xx_uart_src[]; -extern struct platform_device s3c64xx_device_ac97; +extern struct platform_device s3c_device_timer[]; + extern struct platform_device s3c64xx_device_iis0; extern struct platform_device s3c64xx_device_iis1; extern struct platform_device s3c64xx_device_iisv4; -extern struct platform_device s3c64xx_device_onenand1; -extern struct platform_device s3c64xx_device_pcm0; -extern struct platform_device s3c64xx_device_pcm1; + extern struct platform_device s3c64xx_device_spi0; extern struct platform_device s3c64xx_device_spi1; -extern struct platform_device s3c_device_adc; -extern struct platform_device s3c_device_cfcon; +extern struct platform_device samsung_asoc_dma; +extern struct platform_device samsung_asoc_idma; + +extern struct platform_device s3c64xx_device_pcm0; +extern struct platform_device s3c64xx_device_pcm1; + +extern struct platform_device s3c64xx_device_ac97; + +extern struct platform_device s3c_device_ts; +extern struct platform_device s3c_device_ts1; + extern struct platform_device s3c_device_fb; -extern struct platform_device s3c_device_hwmon; -extern struct platform_device s3c_device_hsmmc0; -extern struct platform_device s3c_device_hsmmc1; -extern struct platform_device s3c_device_hsmmc2; -extern struct platform_device s3c_device_hsmmc3; +#ifdef CONFIG_FB_S5P_EXTDSP +extern struct platform_device s3c_device_extdsp; +#endif +extern struct platform_device s5p_device_fimd0; +extern struct platform_device s5p_device_fimd1; +extern struct platform_device s5p_device_mipi_dsim0; +extern struct platform_device s5p_device_mipi_dsim1; +extern struct platform_device s3c_device_ohci; +extern struct platform_device s3c_device_lcd; +extern struct platform_device s3c_device_wdt; extern struct platform_device s3c_device_i2c0; extern struct platform_device s3c_device_i2c1; extern struct platform_device s3c_device_i2c2; @@ -56,89 +70,167 @@ extern struct platform_device s3c_device_i2c4; extern struct platform_device s3c_device_i2c5; extern struct platform_device s3c_device_i2c6; extern struct platform_device s3c_device_i2c7; -extern struct platform_device s3c_device_iis; -extern struct platform_device s3c_device_lcd; -extern struct platform_device s3c_device_nand; -extern struct platform_device s3c_device_ohci; -extern struct platform_device s3c_device_onenand; +extern struct platform_device s5p_device_i2c_hdmiphy; extern struct platform_device s3c_device_rtc; +extern struct platform_device s3c_device_adc; extern struct platform_device s3c_device_sdi; +extern struct platform_device s3c_device_iis; +extern struct platform_device s3c_device_hwmon; +extern struct platform_device s3c_device_hsmmc0; +extern struct platform_device s3c_device_hsmmc1; +extern struct platform_device s3c_device_hsmmc2; +extern struct platform_device s3c_device_hsmmc3; +extern struct platform_device s3c_device_mshci; +extern struct platform_device s3c_device_cfcon; + extern struct platform_device s3c_device_spi0; extern struct platform_device s3c_device_spi1; -extern struct platform_device s3c_device_ts; -extern struct platform_device s3c_device_timer[]; + +extern struct platform_device s5pc100_device_spi0; +extern struct platform_device s5pc100_device_spi1; +extern struct platform_device s5pc100_device_spi2; +extern struct platform_device s5pv210_device_spi0; +extern struct platform_device s5pv210_device_spi1; +extern struct platform_device s5p64x0_device_spi0; +extern struct platform_device s5p64x0_device_spi1; +extern struct platform_device exynos_device_spi0; +extern struct platform_device exynos_device_spi1; +extern struct platform_device exynos_device_spi2; + +extern struct platform_device s3c_device_hwmon; + +extern struct platform_device s3c_device_nand; +extern struct platform_device s3c_device_onenand; +extern struct platform_device s3c64xx_device_onenand1; +extern struct platform_device s5p_device_onenand; + extern struct platform_device s3c_device_usbgadget; +extern struct platform_device s3c_device_usb_hsudc; extern struct platform_device s3c_device_usb_hsotg; extern struct platform_device s3c_device_usb_hsudc; -extern struct platform_device s3c_device_wdt; +extern struct platform_device s3c_device_android_usb; +extern struct platform_device s3c_device_usb_mass_storage; +#ifdef CONFIG_USB_ANDROID_RNDIS +extern struct platform_device s3c_device_rndis; +#endif +extern struct platform_device s5p_device_usbswitch; -extern struct platform_device s5p_device_ehci; -extern struct platform_device s5p_device_fimc0; -extern struct platform_device s5p_device_fimc1; -extern struct platform_device s5p_device_fimc2; -extern struct platform_device s5p_device_fimc3; -extern struct platform_device s5p_device_fimc_md; -extern struct platform_device s5p_device_fimd0; -extern struct platform_device s5p_device_hdmi; -extern struct platform_device s5p_device_i2c_hdmiphy; -extern struct platform_device s5p_device_mfc; -extern struct platform_device s5p_device_mfc_l; -extern struct platform_device s5p_device_mfc_r; -extern struct platform_device s5p_device_mipi_csis0; -extern struct platform_device s5p_device_mipi_csis1; -extern struct platform_device s5p_device_mixer; -extern struct platform_device s5p_device_onenand; -extern struct platform_device s5p_device_sdo; +extern struct platform_device s5pv210_device_ac97; +extern struct platform_device s5pv210_device_pcm0; +extern struct platform_device s5pv210_device_pcm1; +extern struct platform_device s5pv210_device_pcm2; +extern struct platform_device s5pv210_device_iis0; +extern struct platform_device s5pv210_device_iis1; +extern struct platform_device s5pv210_device_iis2; +extern struct platform_device s5pv210_device_spdif; +extern struct platform_device s5pv210_device_cpufreq; +extern struct platform_device s5pv210_device_pdma0; +extern struct platform_device s5pv210_device_pdma1; +extern struct platform_device s5pv210_device_mdma; + +extern struct platform_device exynos_device_ac97; +extern struct platform_device exynos_device_pcm0; +extern struct platform_device exynos_device_pcm1; +extern struct platform_device exynos_device_pcm2; +extern struct platform_device exynos_device_i2s0; +extern struct platform_device exynos_device_i2s1; +extern struct platform_device exynos_device_i2s2; +extern struct platform_device exynos_device_spdif; +extern struct platform_device exynos_device_srp; +extern struct platform_device exynos4_device_pd[]; +extern struct platform_device exynos4_device_ahci; +extern struct platform_device exynos_device_pdma0; +extern struct platform_device exynos_device_pdma1; +extern struct platform_device exynos_device_mdma; +extern struct platform_device exynos_device_dwmci; +extern struct platform_device exynos_device_dwmci0; +extern struct platform_device exynos_device_dwmci1; +extern struct platform_device exynos_device_dwmci2; +extern struct platform_device exynos_device_dwmci3; +extern struct platform_device exynos_device_flite0; +extern struct platform_device exynos_device_flite1; +extern struct platform_device exynos4_device_c2c; +extern struct platform_device exynos_device_flite2; +extern struct platform_device exynos4_device_fimc_is; +extern struct platform_device exynos5_device_fimc_is; +extern struct platform_device exynos5_device_pd[]; +extern struct platform_device exynos5_device_gsc0; +extern struct platform_device exynos5_device_gsc1; +extern struct platform_device exynos5_device_gsc2; +extern struct platform_device exynos5_device_gsc3; +extern struct platform_device exynos5_device_ahci; +extern struct platform_device exynos_device_c2c; +extern struct platform_device exynos_device_ss_udc; +extern struct platform_device exynos_device_xhci; -extern struct platform_device s5p6440_device_iis; extern struct platform_device s5p6440_device_pcm; +extern struct platform_device s5p6440_device_iis; extern struct platform_device s5p6450_device_iis0; extern struct platform_device s5p6450_device_iis1; extern struct platform_device s5p6450_device_iis2; extern struct platform_device s5p6450_device_pcm0; -extern struct platform_device s5p64x0_device_spi0; -extern struct platform_device s5p64x0_device_spi1; - extern struct platform_device s5pc100_device_ac97; +extern struct platform_device s5pc100_device_pcm0; +extern struct platform_device s5pc100_device_pcm1; extern struct platform_device s5pc100_device_iis0; extern struct platform_device s5pc100_device_iis1; extern struct platform_device s5pc100_device_iis2; -extern struct platform_device s5pc100_device_pcm0; -extern struct platform_device s5pc100_device_pcm1; extern struct platform_device s5pc100_device_spdif; -extern struct platform_device s5pc100_device_spi0; -extern struct platform_device s5pc100_device_spi1; -extern struct platform_device s5pc100_device_spi2; -extern struct platform_device s5pv210_device_ac97; -extern struct platform_device s5pv210_device_iis0; -extern struct platform_device s5pv210_device_iis1; -extern struct platform_device s5pv210_device_iis2; -extern struct platform_device s5pv210_device_pcm0; -extern struct platform_device s5pv210_device_pcm1; -extern struct platform_device s5pv210_device_pcm2; -extern struct platform_device s5pv210_device_spdif; -extern struct platform_device s5pv210_device_spi0; -extern struct platform_device s5pv210_device_spi1; +extern struct platform_device samsung_device_keypad; +#ifndef CONFIG_VIDEO_FIMC +extern struct platform_device s5p_device_fimc0; +extern struct platform_device s5p_device_fimc1; +extern struct platform_device s5p_device_fimc2; +extern struct platform_device s5p_device_fimc3; +#else +extern struct platform_device s3c_device_fimc0; +extern struct platform_device s3c_device_fimc1; +extern struct platform_device s3c_device_fimc2; +extern struct platform_device s3c_device_fimc3; +#endif +#ifndef CONFIG_VIDEO_FIMC_MIPI +extern struct platform_device s5p_device_mipi_csis0; +extern struct platform_device s5p_device_mipi_csis1; +#else +extern struct platform_device s3c_device_csis0; +extern struct platform_device s3c_device_csis1; +#endif +extern struct platform_device s5p_device_dp; -extern struct platform_device exynos4_device_ac97; -extern struct platform_device exynos4_device_ahci; -extern struct platform_device exynos4_device_dwmci; -extern struct platform_device exynos4_device_i2s0; -extern struct platform_device exynos4_device_i2s1; -extern struct platform_device exynos4_device_i2s2; -extern struct platform_device exynos4_device_pcm0; -extern struct platform_device exynos4_device_pcm1; -extern struct platform_device exynos4_device_pcm2; -extern struct platform_device exynos4_device_pd[]; -extern struct platform_device exynos4_device_spdif; -extern struct platform_device exynos4_device_sysmmu; +extern struct platform_device s5p_device_jpeg; +extern struct platform_device s5p_device_tvout; +extern struct platform_device s5p_device_cec; +extern struct platform_device s5p_device_hpd; +extern struct platform_device s5p_device_ace; +extern struct platform_device s5p_device_fimg2d; +extern struct platform_device exynos_device_rotator; -extern struct platform_device samsung_asoc_dma; -extern struct platform_device samsung_asoc_idma; -extern struct platform_device samsung_device_keypad; +extern struct platform_device s5p_device_ehci; +extern struct platform_device s5p_device_ohci; +#ifdef CONFIG_USB_HOST_NOTIFY +extern struct platform_device host_notifier_device; +#endif + +extern struct platform_device exynos_device_sysmmu[]; + +extern struct platform_device s5p_device_mfc; +extern struct platform_device s5p_device_mipi_dsim; +extern struct platform_device s5p_device_dsim; + +extern struct platform_device s5p_device_hdmi; +extern struct platform_device s5p_device_mixer; +extern struct platform_device s5p_device_sdo; + +#ifdef CONFIG_FB_S5P_MIPI_DSIM +extern struct platform_device s5p_device_dsim; +#endif + +#ifdef CONFIG_SENSORS_EXYNOS4_TMU +extern struct platform_device exynos4_device_tmu; +#endif /* s3c2440 specific devices */ @@ -149,6 +241,13 @@ extern struct platform_device s3c_device_ac97; #endif +#if defined(CONFIG_VIDEO_TSI) +extern struct platform_device s3c_device_tsi; +#endif + +extern void exynos_ss_udc_set_platdata(struct exynos_usb3_drd_pdata *pd); +extern void exynos_xhci_set_platdata(struct exynos_usb3_drd_pdata *pd); + /** * s3c_set_platdata() - helper for setting platform data * @pd: The default platform data for this device. diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h index 1c1ed54..336d5ac 100644 --- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h +++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h @@ -18,6 +18,11 @@ extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS]; #define DMA_CH_VALID (1<<31) #define DMA_CH_NEVER (1<<30) +struct s3c24xx_dma_addr { + unsigned long from; + unsigned long to; +}; + /* struct s3c24xx_dma_map * * this holds the mapping information for the channel selected @@ -26,6 +31,7 @@ extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS]; struct s3c24xx_dma_map { const char *name; + struct s3c24xx_dma_addr hw_addr; unsigned long channels[S3C_DMA_CHANNELS]; unsigned long channels_rx[S3C_DMA_CHANNELS]; @@ -41,7 +47,7 @@ struct s3c24xx_dma_selection { void (*direction)(struct s3c2410_dma_chan *chan, struct s3c24xx_dma_map *map, - enum dma_data_direction dir); + enum s3c2410_dmasrc dir); }; extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel); diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h index b906112..816d505 100644 --- a/arch/arm/plat-samsung/include/plat/dma.h +++ b/arch/arm/plat-samsung/include/plat/dma.h @@ -10,14 +10,19 @@ * published by the Free Software Foundation. */ -#include <linux/dma-mapping.h> - enum s3c2410_dma_buffresult { S3C2410_RES_OK, S3C2410_RES_ERR, S3C2410_RES_ABORT }; +enum s3c2410_dmasrc { + S3C2410_DMASRC_HW, /* source is memory */ + S3C2410_DMASRC_MEM, /* source is hardware */ + S3C_DMA_MEM2MEM, + S3C_DMA_MEM2MEM_SET, +}; + /* enum s3c2410_chan_op * * operation codes passed to the DMA code by the user, and also used @@ -93,8 +98,18 @@ extern int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *); * drained before the buffer is given to the DMA system. */ -extern int s3c2410_dma_enqueue(enum dma_ch channel, void *id, - dma_addr_t data, int size); +#define s3c2410_dma_enqueue(id, token, addr, size) \ + s3c2410_dma_enqueue_ring(id, token, addr, size, 0) + +/* s3c2410_dma_enqueue_ring + * + * place the given buffer onto the queue of operations for the channel. + * The buffer must be allocated from dma coherent memory, or the Dcache/WB + * drained before the buffer is given to the DMA system. +*/ + +extern int s3c2410_dma_enqueue_ring(enum dma_ch channel, void *id, + dma_addr_t data, int size, int numofblock); /* s3c2410_dma_config * @@ -109,7 +124,7 @@ extern int s3c2410_dma_config(enum dma_ch channel, int xferunit); */ extern int s3c2410_dma_devconfig(enum dma_ch channel, - enum dma_data_direction source, unsigned long devaddr); + enum s3c2410_dmasrc source, unsigned long devaddr); /* s3c2410_dma_getposition * @@ -123,4 +138,3 @@ extern int s3c2410_dma_set_opfn(enum dma_ch, s3c2410_dma_opfn_t rtn); extern int s3c2410_dma_set_buffdone_fn(enum dma_ch, s3c2410_dma_cbfn_t rtn); -#include <plat/dma-ops.h> diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/plat-samsung/include/plat/fb-core.h index 6abcbf1..4335840 100644 --- a/arch/arm/plat-samsung/include/plat/fb-core.h +++ b/arch/arm/plat-samsung/include/plat/fb-core.h @@ -35,6 +35,12 @@ static inline void s5p_fb_setname(int id, char *name) s5p_device_fimd0.name = name; break; #endif + +#ifdef CONFIG_S5P_DEV_FIMD1 + case 1: + s5p_device_fimd1.name = name; + break; +#endif default: printk(KERN_ERR "%s: invalid device id(%d)\n", __func__, id); break; diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index 0fedf47..2e1813f 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h @@ -15,6 +15,8 @@ #ifndef __PLAT_S3C_FB_H #define __PLAT_S3C_FB_H __FILE__ +#include <plat/gpio-cfg.h> + /* S3C_FB_MAX_WIN * Set to the maximum number of windows that any of the supported hardware * can use. Since the platform data uses this for an array size, having it @@ -22,11 +24,28 @@ */ #define S3C_FB_MAX_WIN (5) +#if defined(CONFIG_MACH_P11) || defined(CONFIG_MACH_P10) +/* IOCTL commands */ +#define S3CFB_WIN_POSITION _IOW('F', 203, \ + struct s3c_fb_user_window) +#define S3CFB_WIN_SET_PLANE_ALPHA _IOW('F', 204, \ + struct s3c_fb_user_plane_alpha) +#define S3CFB_WIN_SET_CHROMA _IOW('F', 205, \ + struct s3c_fb_user_chroma) +#define S3CFB_SET_VSYNC_INT _IOW('F', 206, u32) + +#define S3CFB_GET_ION_USER_HANDLE _IOWR('F', 208, \ + struct s3c_fb_user_ion_client) +#define S3CFB_PAN_DISPLAY_INDEX _IOW('F', 209, __u32) + +#endif /** * struct s3c_fb_pd_win - per window setup data * @win_mode: The display parameters to initialise (not for window 0) * @virtual_x: The virtual X size. * @virtual_y: The virtual Y size. + * @width: The width of display in mm + * @height: The height of display in mm */ struct s3c_fb_pd_win { struct fb_videomode win_mode; @@ -35,6 +54,8 @@ struct s3c_fb_pd_win { unsigned short max_bpp; unsigned short virtual_x; unsigned short virtual_y; + unsigned short width; + unsigned short height; }; /** @@ -82,6 +103,14 @@ extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd); /** + * s5p_fimd1_set_platdata() - Setup the FB device with platform data. + * @pd: The platform data to set. The data is copied from the passed structure + * so the machine data can mark the data __initdata so that any unused + * machines will end up dumping their data at runtime. + */ +extern void s5p_fimd1_set_platdata(struct s3c_fb_platdata *pd); + +/** * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD * * Initialise the GPIO for an 24bpp LCD display on the RGB interface. @@ -110,10 +139,22 @@ extern void s5pv210_fb_gpio_setup_24bpp(void); extern void exynos4_fimd0_gpio_setup_24bpp(void); /** - * s5p64x0_fb_gpio_setup_24bpp() - S5P6440/S5P6450 setup function for 24bpp LCD + * exynos4_fimd_cfg_gpios() - Exynos4 setup function for 24bpp LCD * * Initialise the GPIO for an 24bpp LCD display on the RGB interface. */ -extern void s5p64x0_fb_gpio_setup_24bpp(void); +extern void exynos4_fimd_cfg_gpios(unsigned int base, unsigned int nr, + unsigned int cfg, s5p_gpio_drvstr_t drvstr); + +/** + * exynos4_fimd0_setup_clock() = Exynos4 setup function for parent clock. + * @dev: device pointer + * @parent: parent clock used for LCD pixel clock + * @clk_rate: clock rate for parent clock + */ +int __init exynos4_fimd0_setup_clock(struct device *dev, const char *parent, + unsigned long clk_rate); +int __init exynos4_fimd_setup_clock(struct device *dev, const char *bus_clk, + const char *parent, unsigned long clk_rate); #endif /* __PLAT_S3C_FB_H */ diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h index a181d7c..3ad8386 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h @@ -1,11 +1,11 @@ -/* linux/arch/arm/plat-samsung/include/plat/gpio-cfg-helper.h +/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> * - * Samsung Platform - GPIO pin configuration helper definitions + * S3C Platform - GPIO pin configuration helper definitions * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -24,40 +24,130 @@ * by disabling interrupts. */ -static inline int samsung_gpio_do_setcfg(struct samsung_gpio_chip *chip, - unsigned int off, unsigned int config) +static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int config) { return (chip->config->set_config)(chip, off, config); } -static inline unsigned samsung_gpio_do_getcfg(struct samsung_gpio_chip *chip, - unsigned int off) +static inline unsigned s3c_gpio_do_getcfg(struct s3c_gpio_chip *chip, + unsigned int off) { return (chip->config->get_config)(chip, off); } -static inline int samsung_gpio_do_setpull(struct samsung_gpio_chip *chip, - unsigned int off, samsung_gpio_pull_t pull) +static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull) { return (chip->config->set_pull)(chip, off, pull); } -static inline samsung_gpio_pull_t samsung_gpio_do_getpull(struct samsung_gpio_chip *chip, - unsigned int off) +static inline s3c_gpio_pull_t s3c_gpio_do_getpull(struct s3c_gpio_chip *chip, + unsigned int off) { return chip->config->get_pull(chip, off); } +/** + * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @cfg: The configuration value to set. + * + * This helper deal with the GPIO cases where the control register + * has two bits of configuration per gpio, which have the following + * functions: + * 00 = input + * 01 = output + * 1x = special function +*/ +extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int cfg); + +/** + * s3c_gpio_getcfg_s3c24xx - S3C24XX style GPIO configuration read. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * + * The reverse of s3c_gpio_setcfg_s3c24xx(). Will return a value whicg + * could be directly passed back to s3c_gpio_setcfg_s3c24xx(), from the + * S3C_GPIO_SPECIAL() macro. + */ +unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip, + unsigned int off); + +/** + * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A) + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @cfg: The configuration value to set. + * + * This helper deal with the GPIO cases where the control register + * has one bit of configuration for the gpio, where setting the bit + * means the pin is in special function mode and unset means output. +*/ +extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int cfg); + + +/** + * s3c_gpio_getcfg_s3c24xx_a - S3C24XX style GPIO configuration read (Bank A) + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * + * The reverse of s3c_gpio_setcfg_s3c24xx_a() turning an GPIO into a usable + * GPIO configuration value. + * + * @sa s3c_gpio_getcfg_s3c24xx + * @sa s3c_gpio_getcfg_s3c64xx_4bit + */ +extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip, + unsigned int off); + +/** + * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @cfg: The configuration value to set. + * + * This helper deal with the GPIO cases where the control register has 4 bits + * of control per GPIO, generally in the form of: + * 0000 = Input + * 0001 = Output + * others = Special functions (dependent on bank) + * + * Note, since the code to deal with the case where there are two control + * registers instead of one, we do not have a separate set of functions for + * each case. +*/ +extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int cfg); + + +/** + * s3c_gpio_getcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config read. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * + * The reverse of s3c_gpio_setcfg_s3c64xx_4bit(), turning a gpio configuration + * register setting into a value the software can use, such as could be passed + * to s3c_gpio_setcfg_s3c64xx_4bit(). + * + * @sa s3c_gpio_getcfg_s3c24xx + */ +extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, + unsigned int off); + /* Pull-{up,down} resistor controls. * - * S3C2410,S3C2440 = Pull-UP, + * S3C2410,S3C2440,S3C24A0 = Pull-UP, * S3C2412,S3C2413 = Pull-Down * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef] * S3C2443 = Pull-Both [not same as S3C6400] */ /** - * s3c24xx_gpio_setpull_1up() - Pull configuration for choice of up or none. + * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none. * @chip: The gpio chip that is being configured. * @off: The offset for the GPIO being configured. * @param: pull: The pull mode being requested. @@ -65,11 +155,11 @@ static inline samsung_gpio_pull_t samsung_gpio_do_getpull(struct samsung_gpio_ch * This is a helper function for the case where we have GPIOs with one * bit configuring the presence of a pull-up resistor. */ -extern int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip, - unsigned int off, samsung_gpio_pull_t pull); +extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull); /** - * s3c24xx_gpio_setpull_1down() - Pull configuration for choice of down or none + * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none * @chip: The gpio chip that is being configured * @off: The offset for the GPIO being configured * @param: pull: The pull mode being requested @@ -77,13 +167,11 @@ extern int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip, * This is a helper function for the case where we have GPIOs with one * bit configuring the presence of a pull-down resistor. */ -extern int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip, - unsigned int off, samsung_gpio_pull_t pull); +extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull); /** - * samsung_gpio_setpull_upown() - Pull configuration for choice of up, - * down or none - * + * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none * @chip: The gpio chip that is being configured. * @off: The offset for the GPIO being configured. * @param: pull: The pull mode being requested. @@ -95,46 +183,45 @@ extern int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip, * 01 = Pull-up resistor connected * 10 = Pull-down resistor connected */ -extern int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, - unsigned int off, samsung_gpio_pull_t pull); +extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull); + /** - * samsung_gpio_getpull_updown() - Get configuration for choice of up, - * down or none - * + * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none * @chip: The gpio chip that the GPIO pin belongs to * @off: The offset to the pin to get the configuration of. * - * This helper function reads the state of the pull-{up,down} resistor - * for the given GPIO in the same case as samsung_gpio_setpull_upown. + * This helper function reads the state of the pull-{up,down} resistor for the + * given GPIO in the same case as s3c_gpio_setpull_upown. */ -extern samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip, - unsigned int off); +extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, + unsigned int off); /** - * s3c24xx_gpio_getpull_1up() - Get configuration for choice of up or none + * s3c_gpio_getpull_1up() - Get configuration for choice of up or none * @chip: The gpio chip that the GPIO pin belongs to * @off: The offset to the pin to get the configuration of. * * This helper function reads the state of the pull-up resistor for the - * given GPIO in the same case as s3c24xx_gpio_setpull_1up. + * given GPIO in the same case as s3c_gpio_setpull_1up. */ -extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip, - unsigned int off); +extern s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip, + unsigned int off); /** - * s3c24xx_gpio_getpull_1down() - Get configuration for choice of down or none + * s3c_gpio_getpull_1down() - Get configuration for choice of down or none * @chip: The gpio chip that the GPIO pin belongs to * @off: The offset to the pin to get the configuration of. * * This helper function reads the state of the pull-down resistor for the - * given GPIO in the same case as s3c24xx_gpio_setpull_1down. + * given GPIO in the same case as s3c_gpio_setpull_1down. */ -extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip, - unsigned int off); +extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip, + unsigned int off); /** - * s3c2443_gpio_setpull() - Pull configuration for s3c2443. + * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443. * @chip: The gpio chip that is being configured. * @off: The offset for the GPIO being configured. * @param: pull: The pull mode being requested. @@ -146,18 +233,19 @@ extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip * * 10 = Pull-down resistor connected * x1 = No pull up resistor */ -extern int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip, - unsigned int off, samsung_gpio_pull_t pull); +extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull); /** - * s3c2443_gpio_getpull() - Get configuration for s3c2443 pull resistors + * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors * @chip: The gpio chip that the GPIO pin belongs to. * @off: The offset to the pin to get the configuration of. * * This helper function reads the state of the pull-{up,down} resistor for the - * given GPIO in the same case as samsung_gpio_setpull_upown. + * given GPIO in the same case as s3c_gpio_setpull_upown. */ -extern samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip, +extern s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip, unsigned int off); #endif /* __PLAT_GPIO_CFG_HELPERS_H */ + diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index df8155b..943789c 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h @@ -24,16 +24,16 @@ #ifndef __PLAT_GPIO_CFG_H #define __PLAT_GPIO_CFG_H __FILE__ -#include<linux/types.h> - -typedef unsigned int __bitwise__ samsung_gpio_pull_t; +typedef unsigned int __bitwise__ s3c_gpio_pull_t; typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; +typedef unsigned int __bitwise__ s5p_gpio_pd_cfg_t; +typedef unsigned int __bitwise__ s5p_gpio_pd_pull_t; /* forward declaration if gpio-core.h hasn't been included */ -struct samsung_gpio_chip; +struct s3c_gpio_chip; /** - * struct samsung_gpio_cfg GPIO configuration + * struct s3c_gpio_cfg GPIO configuration * @cfg_eint: Configuration setting when used for external interrupt source * @get_pull: Read the current pull configuration for the GPIO * @set_pull: Set the current pull configuraiton for the GPIO @@ -46,20 +46,20 @@ struct samsung_gpio_chip; * per-bank configuration information that other systems such as the * external interrupt code will need. * - * @sa samsung_gpio_cfgpin + * @sa s3c_gpio_cfgpin * @sa s3c_gpio_getcfg * @sa s3c_gpio_setpull * @sa s3c_gpio_getpull */ -struct samsung_gpio_cfg { +struct s3c_gpio_cfg { unsigned int cfg_eint; - samsung_gpio_pull_t (*get_pull)(struct samsung_gpio_chip *chip, unsigned offs); - int (*set_pull)(struct samsung_gpio_chip *chip, unsigned offs, - samsung_gpio_pull_t pull); + s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs); + int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs, + s3c_gpio_pull_t pull); - unsigned (*get_config)(struct samsung_gpio_chip *chip, unsigned offs); - int (*set_config)(struct samsung_gpio_chip *chip, unsigned offs, + unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs); + int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs, unsigned config); }; @@ -71,7 +71,7 @@ struct samsung_gpio_cfg { #define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1)) #define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x)) -#define samsung_gpio_is_cfg_special(_cfg) \ +#define s3c_gpio_is_cfg_special(_cfg) \ (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK) /** @@ -127,12 +127,30 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, * * These values control the state of the weak pull-{up,down} resistors * available on most pins on the S3C series. Not all chips support both - * up or down settings, and it may be dependent on the chip that is being + * up or down settings, and it may be dependant on the chip that is being * used to whether the particular mode is available. */ -#define S3C_GPIO_PULL_NONE ((__force samsung_gpio_pull_t)0x00) -#define S3C_GPIO_PULL_DOWN ((__force samsung_gpio_pull_t)0x01) -#define S3C_GPIO_PULL_UP ((__force samsung_gpio_pull_t)0x02) +#if defined(CONFIG_ARCH_S5PV310) || defined(CONFIG_ARCH_EXYNOS) +#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) +#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01) +#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x03) +#else +#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) +#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01) +#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02) +#endif + +#if defined(CONFIG_ARCH_S5PV310) || defined(CONFIG_ARCH_EXYNOS) +/* need to move to mach/gpio.h */ +#define S3C_GPIO_SLP_OUT0 ((__force s3c_gpio_pull_t)0x00) +#define S3C_GPIO_SLP_OUT1 ((__force s3c_gpio_pull_t)0x01) +#define S3C_GPIO_SLP_INPUT ((__force s3c_gpio_pull_t)0x02) +#define S3C_GPIO_SLP_PREV ((__force s3c_gpio_pull_t)0x03) + +#define S3C_GPIO_SETPIN_ZERO 0 +#define S3C_GPIO_SETPIN_ONE 1 +#define S3C_GPIO_SETPIN_NONE 2 +#endif /** * s3c_gpio_setpull() - set the state of a gpio pin pull resistor @@ -145,7 +163,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, * * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP. */ -extern int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull); +extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); /** * s3c_gpio_getpull() - get the pull resistor state of a gpio pin @@ -153,7 +171,7 @@ extern int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull); * * Read the pull resistor value for the specified pin. */ -extern samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin); +extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); /* configure `all` aspects of an gpio */ @@ -172,7 +190,7 @@ extern samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin); * @sa s3c_gpio_cfgpin_range */ extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, - unsigned int cfg, samsung_gpio_pull_t pull); + unsigned int cfg, s3c_gpio_pull_t pull); static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size, unsigned int cfg) @@ -209,6 +227,65 @@ extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin); */ extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr); +/* Define values for the power down configuration available for each gpio pin. + * + * These values control the state of the power down configuration resistors + * available on most pins on the S5P series. + */ +#define S5P_GPIO_PD_OUTPUT0 ((__force s5p_gpio_pd_cfg_t)0x00) +#define S5P_GPIO_PD_OUTPUT1 ((__force s5p_gpio_pd_cfg_t)0x01) +#define S5P_GPIO_PD_INPUT ((__force s5p_gpio_pd_cfg_t)0x02) +#define S5P_GPIO_PD_PREV_STATE ((__force s5p_gpio_pd_cfg_t)0x03) + +/** + * s5p_gpio_set_pd_cfg() - set the configuration of a gpio power down mode + * @pin: The pin number to configure the pull resistor. + * @pd_cfg: The configuration for the pwer down mode configuration register. + * + * This function sets the configuration of the power down mode resistor for the + * specified pin. It will return 0 if successful, or a negative error + * code if the pin cannot support the requested power down mode. + * +*/ +extern int s5p_gpio_set_pd_cfg(unsigned int pin, s5p_gpio_pd_cfg_t pd_cfg); + +/** + * s5p_gpio_get_pd_cfg() - get the power down mode configuration of a gpio pin + * @pin: The pin number to get the settings for + * + * Read the power down mode resistor value for the specified pin. +*/ +extern s5p_gpio_pd_cfg_t s5p_gpio_get_pd_cfg(unsigned int pin); + +/* Define values for the power down pull-{up,down} available for each gpio pin. + * + * These values control the state of the power down mode pull-{up,down} + * resistors available on most pins on the S5P series. + */ +#define S5P_GPIO_PD_UPDOWN_DISABLE ((__force s5p_gpio_pd_pull_t)0x00) +#define S5P_GPIO_PD_DOWN_ENABLE ((__force s5p_gpio_pd_pull_t)0x01) +#define S5P_GPIO_PD_UP_ENABLE ((__force s5p_gpio_pd_pull_t)0x03) + +/** + * s5p_gpio_set_pd_pull() - set the pull-{up,down} of a gpio pin power down mode + * @pin: The pin number to configure the pull resistor. + * @pd_pull: The configuration for the power down mode pull resistor. + * + * This function sets the configuration of the pull-{up,down} resistor for the + * specified pin. It will return 0 if successful, or a negative error + * code if the pin cannot support the requested pull setting. + * +*/ +extern int s5p_gpio_set_pd_pull(unsigned int pin, s5p_gpio_pd_pull_t pd_pull); + +/** + * s5p_gpio_get_pd_pull() - get the power down pull resistor config of gpio pin + * @pin: The pin number to get the settings for + * + * Read the power mode pull resistor value for the specified pin. +*/ +extern s5p_gpio_pd_pull_t s5p_gpio_get_pd_pull(unsigned int pin); + /** * s5p_register_gpio_interrupt() - register interrupt support for a gpio group * @pin: The pin number from the group to be registered diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 1fe6917..792fdb0 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -25,22 +25,22 @@ * specific code. */ -struct samsung_gpio_chip; +struct s3c_gpio_chip; /** - * struct samsung_gpio_pm - power management (suspend/resume) information + * struct s3c_gpio_pm - power management (suspend/resume) information * @save: Routine to save the state of the GPIO block * @resume: Routine to resume the GPIO block. */ -struct samsung_gpio_pm { - void (*save)(struct samsung_gpio_chip *chip); - void (*resume)(struct samsung_gpio_chip *chip); +struct s3c_gpio_pm { + void (*save)(struct s3c_gpio_chip *chip); + void (*resume)(struct s3c_gpio_chip *chip); }; -struct samsung_gpio_cfg; +struct s3c_gpio_cfg; /** - * struct samsung_gpio_chip - wrapper for specific implementation of gpio + * struct s3c_gpio_chip - wrapper for specific implementation of gpio * @chip: The chip structure to be exported via gpiolib. * @base: The base pointer to the gpio configuration registers. * @group: The group register number for gpio interrupt support. @@ -60,24 +60,74 @@ struct samsung_gpio_cfg; * CPU cores trying to get one lock for different GPIO banks, where each * bank of GPIO has its own register space and configuration registers. */ -struct samsung_gpio_chip { +struct s3c_gpio_chip { struct gpio_chip chip; - struct samsung_gpio_cfg *config; - struct samsung_gpio_pm *pm; + struct s3c_gpio_cfg *config; + struct s3c_gpio_pm *pm; void __iomem *base; int irq_base; int group; - spinlock_t lock; + unsigned int eint_offset; + spinlock_t lock; #ifdef CONFIG_PM u32 pm_save[4]; #endif }; -static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc) +static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) { - return container_of(gpc, struct samsung_gpio_chip, chip); + return container_of(gpc, struct s3c_gpio_chip, chip); } +/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip. + * @chip: The chip to register + * + * This is a wrapper to gpiochip_add() that takes our specific gpio chip + * information and makes the necessary alterations for the platform and + * notes the information for use with the configuration systems and any + * other parts of the system. + */ +extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); + +/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios + * for use with the configuration calls, and other parts of the s3c gpiolib + * support code. + * + * Not all s3c support code will need this, as some configurations of cpu + * may only support one or two different configuration options and have an + * easy gpio to s3c_gpio_chip mapping function. If this is the case, then + * the machine support file should provide its own s3c_gpiolib_getchip() + * and any other necessary functions. + */ + +/** + * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config. + * @chip: The gpio chip that is being configured. + * @nr_chips: The no of chips (gpio ports) for the GPIO being configured. + * + * This helper deal with the GPIO cases where the control register has 4 bits + * of control per GPIO, generally in the form of: + * 0000 = Input + * 0001 = Output + * others = Special functions (dependent on bank) + * + * Note, since the code to deal with the case where there are two control + * registers instead of one, we do not have a separate set of function + * (samsung_gpiolib_add_4bit2_chips)for each case. + */ +extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, + int nr_chips); +extern void samsung_gpiolib_add_4bit_chips_no_pm(struct s3c_gpio_chip *chip, + int nr_chips); +extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, + int nr_chips); +extern void samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip, + int nr_chips); + +extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); +extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); + + /** * samsung_gpiolib_to_irq - convert gpio pin to irq number * @chip: The gpio chip that the pin belongs to. @@ -89,36 +139,36 @@ static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc) extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset); /* exported for core SoC support to change */ -extern struct samsung_gpio_cfg s3c24xx_gpiocfg_default; +extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default; #ifdef CONFIG_S3C_GPIO_TRACK -extern struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END]; +extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; -static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int chip) +static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) { - return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; + return (pin < S3C_GPIO_END) ? s3c_gpios[pin] : NULL; } #else -/* machine specific code should provide samsung_gpiolib_getchip */ +/* machine specific code should provide s3c_gpiolib_getchip */ #include <mach/gpio-track.h> -static inline void s3c_gpiolib_track(struct samsung_gpio_chip *chip) { } +static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } #endif #ifdef CONFIG_PM -extern struct samsung_gpio_pm samsung_gpio_pm_1bit; -extern struct samsung_gpio_pm samsung_gpio_pm_2bit; -extern struct samsung_gpio_pm samsung_gpio_pm_4bit; +extern struct s3c_gpio_pm s3c_gpio_pm_1bit; +extern struct s3c_gpio_pm s3c_gpio_pm_2bit; +extern struct s3c_gpio_pm s3c_gpio_pm_4bit; #define __gpio_pm(x) x #else -#define samsung_gpio_pm_1bit NULL -#define samsung_gpio_pm_2bit NULL -#define samsung_gpio_pm_4bit NULL +#define s3c_gpio_pm_1bit NULL +#define s3c_gpio_pm_2bit NULL +#define s3c_gpio_pm_4bit NULL #define __gpio_pm(x) NULL #endif /* CONFIG_PM */ /* locking wrappers to deal with multiple access to the same gpio bank */ -#define samsung_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) -#define samsung_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) +#define s3c_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) +#define s3c_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) diff --git a/arch/arm/plat-samsung/include/plat/iovmm.h b/arch/arm/plat-samsung/include/plat/iovmm.h new file mode 100644 index 0000000..53d2e77 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/iovmm.h @@ -0,0 +1,76 @@ +/* linux/arch/arm/plat-s5p/include/plat/iovmm.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_PLAT_IOVMM_H +#define __ASM_PLAT_IOVMM_H + +#ifdef CONFIG_EXYNOS_IOVMM + +struct scatterlist; + +int iovmm_setup(struct device *dev); +void iovmm_cleanup(struct device *dev); +int iovmm_activate(struct device *dev); +void iovmm_deactivate(struct device *dev); + +/* iovmm_map() - Maps a list of physical memory chunks + * @dev: the owner of the IO address space where the mapping is created + * @sg: list of physical memory chunks to map + * @offset: length in bytes where the mapping starts + * @size: how much memory to map in bytes. @offset + @size must not exceed + * total size of @sg + * + * This function returns mapped IO address in the address space of @dev. + * Returns 0 if mapping fails. + * + * The caller of this function must ensure that iovmm_cleanup() is not called + * while this function is called. + * + */ +dma_addr_t iovmm_map(struct device *dev, struct scatterlist *sg, off_t offset, + size_t size); + +/* iovmm_map() - unmaps the given IO address + * @dev: the owner of the IO address space where @iova belongs + * @iova: IO address that needs to be unmapped and freed. + * + * The caller of this function must ensure that iovmm_cleanup() is not called + * while this function is called. + */ +void iovmm_unmap(struct device *dev, dma_addr_t iova); + +/* iovmm_map_oto - create one to one mapping for the given physical address + * @dev: the owner of the IO address space to map + * @phys: physical address to map + * @size: size of the mapping to create + * + * This function return 0 if mapping is successful. Otherwise, minus error + * value. + */ +int iovmm_map_oto(struct device *dev, phys_addr_t phys, size_t size); + +/* iovmm_unmap_oto - remove one to one mapping + * @dev: the owner ofthe IO address space + * @phys: physical address to remove mapping + */ +void iovmm_unmap_oto(struct device *dev, phys_addr_t phys); + +#else +#define iovmm_setup(dev) (-ENOSYS) +#define iovmm_cleanup(dev) do { } while (0) +#define iovmm_activate(dev) (-ENOSYS) +#define iovmm_deactivate(dev) do { } while (0) +#define iovmm_map(dev, sg) (0) +#define iovmm_unmap(dev, iova) do { } while (0) +#define iovmm_map_oto(dev, phys, size) (0) +#define iovmm_unmap_oto(dev, phys) do { } while (0) +#endif /* CONFIG_EXYNOS_IOVMM */ + +#endif /*__ASM_PLAT_IOVMM_H*/ diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/plat-samsung/include/plat/keypad.h index b59a648..997220f 100644 --- a/arch/arm/plat-samsung/include/plat/keypad.h +++ b/arch/arm/plat-samsung/include/plat/keypad.h @@ -14,9 +14,13 @@ #define __PLAT_SAMSUNG_KEYPAD_H #include <linux/input/matrix_keypad.h> - +#if defined(CONFIG_MACH_M0_GRANDECTC) || defined(CONFIG_MACH_IRON) +#define SAMSUNG_MAX_ROWS 14 +#define SAMSUNG_MAX_COLS 8 +#else #define SAMSUNG_MAX_ROWS 8 #define SAMSUNG_MAX_COLS 8 +#endif /** * struct samsung_keypad_platdata - Platform device data for Samsung Keypad. diff --git a/arch/arm/plat-samsung/include/plat/map-base.h b/arch/arm/plat-samsung/include/plat/map-base.h index 3ffac4d..ec28c99 100644 --- a/arch/arm/plat-samsung/include/plat/map-base.h +++ b/arch/arm/plat-samsung/include/plat/map-base.h @@ -14,15 +14,15 @@ #ifndef __ASM_PLAT_MAP_H #define __ASM_PLAT_MAP_H __FILE__ -/* Fit all our registers in at 0xF6000000 upwards, trying to use as - * little of the VA space as possible so vmalloc and friends have a - * better chance of getting memory. +/* Fit all our registers in at CONFIG_S3C_BASE_ADDR upwards, trying to + * use as little of the VA space as possible so vmalloc and friends + * have a better chance of getting memory. * * we try to ensure stuff like the IRQ registers are available for * an single MOVS instruction (ie, only 8 bits of set data) */ -#define S3C_ADDR_BASE 0xF6000000 +#define S3C_ADDR_BASE CONFIG_S3C_ADDR_BASE #ifndef __ASSEMBLY__ #define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) @@ -35,8 +35,14 @@ #define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ #define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ +#define S3C_VA_HSOTG S3C_ADDR(0x00E00000) /* OTG */ +#define S3C_VA_HSPHY S3C_ADDR(0x00F00000) /* OTG PHY */ #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ +#define S3C_VA_KLOG_BUF S3C_ADDR(0x01100000) /* non-cached log buf */ +#define S3C_VA_SLOG_BUF S3C_ADDR(0x01400000) /* non-cached sched log buf */ +#define S3C_VA_AUXLOG_BUF S3C_ADDR(0x01600000) /* auxiliary log buf */ + /* This is used for the CPU specific mappings that may be needed, so that * they do not need to directly used S3C_ADDR() and thus make it easier to * modify the space for mapping. diff --git a/arch/arm/plat-samsung/include/plat/mshci.h b/arch/arm/plat-samsung/include/plat/mshci.h new file mode 100644 index 0000000..0333500 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/mshci.h @@ -0,0 +1,161 @@ +/* linux/arch/arm/plat-samsung/include/plat/mshci.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * EXYNOS4 - MSHCI (HSMMC) platform data definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S3C_MSHCI_H +#define __PLAT_S3C_MSHCI_H __FILE__ + +struct platform_device; +struct mmc_host; +struct mmc_card; +struct mmc_ios; + +enum ms_cd_types { + S3C_MSHCI_CD_INTERNAL, /* use mmc internal CD line */ + S3C_MSHCI_CD_EXTERNAL, /* use external callback */ + S3C_MSHCI_CD_GPIO, /* use external gpio pin for CD line */ + S3C_MSHCI_CD_NONE, /* no CD line, use polling to detect card */ + S3C_MSHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */ +}; + +/** + * struct s3c_mshci_platdata() - Platform device data for Samsung MSHCI + * @max_width: The maximum number of data bits supported. + * @host_caps: Standard MMC host capabilities bit field. + * @cd_type: Type of Card Detection method (see cd_types enum above) + * @wp_gpio: The gpio number using for WP. + * @has_wp_gpio: Check using wp_gpio or not. + * @ext_cd_init: Initialize external card detect subsystem. Called on + * mshci-s3c driver probe when cd_type == S3C_MSHCI_CD_EXTERNAL. + * notify_func argument is a callback to the mshci-s3c driver + * that triggers the card detection event. Callback arguments: + * dev is pointer to platform device of the host controller, + * state is new state of the card (0 - removed, 1 - inserted). + * @ext_cd_cleanup: Cleanup external card detect subsystem. Called on + * mshci-s3c driver remove when cd_type == S3C_MSHCI_CD_EXTERNAL. + * notify_func argument is the same callback as for ext_cd_init. + * @ext_cd_gpio: gpio pin used for external CD line, valid only if + * cd_type == S3C_MSHCI_CD_GPIO + * @ext_cd_gpio_invert: invert values for external CD gpio line + * @cfg_gpio: Configure the GPIO for a specific card bit-width + * @cfg_card: Configure the interface for a specific card and speed. This + * is necessary the controllers and/or GPIO blocks require the + * changing of driver-strength and other controls dependant on + * the card and speed of operation. + * + * Initialisation data specific to either the machine or the platform + * for the device driver to use or call-back when configuring gpio or + * card speed information. +*/ +struct s3c_mshci_platdata { + unsigned int max_width; + unsigned int host_caps; + unsigned int host_caps2; + enum ms_cd_types cd_type; + + char **clocks; /* set of clock sources */ + + int wp_gpio; + int ext_cd_gpio; + int int_power_gpio; + int fifo_depth; + bool ext_cd_gpio_invert; + bool has_wp_gpio; + int (*ext_cd_init)(void (*notify_func)(struct platform_device *, + int state)); + int (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *, + int state)); + + void (*cfg_gpio)(struct platform_device *dev, int width); + void (*cfg_ddr)(struct platform_device *dev, int ddr); + void (*init_card)(struct platform_device *dev); + void (*set_power)(struct platform_device *dev, int en); + void (*cfg_card)(struct platform_device *dev, + void __iomem *regbase, + struct mmc_ios *ios, + struct mmc_card *card); + void (*shutdown)(void); +}; + +/** + * s3c_mshci_set_platdata - Set platform data for S3C MSHCI device. + * @pd: Platform data to register to device. + * + * Register the given platform data for use withe S3C MSHCI device. + * The call will copy the platform data, so the board definitions can + * make the structure itself __initdata. + */ +extern void s3c_mshci_set_platdata(struct s3c_mshci_platdata *pd); + +/* Default platform data, exported so that per-cpu initialisation can + * set the correct one when there are more than one cpu type selected. +*/ + +extern struct s3c_mshci_platdata s3c_mshci_def_platdata; + +/* Helper function availablity */ + +extern void s5p6450_setup_mshci_cfg_gpio(struct platform_device *, int w); + +/* S5P6450 MSHCI setup */ +extern char *s5p6450_mshc_clksrcs[1]; + +extern void s5p6450_setup_mshci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + +static inline void s5p6450_default_mshci(void) +{ +#ifdef CONFIG_EXYNOS4_DEV_MSHC + s3c_mshci_def_platdata.clocks = s5p6450_mshc_clksrcs; + s3c_mshci_def_platdata.cfg_gpio = s5p6450_setup_mshci_cfg_gpio; + s3c_mshci_def_platdata.cfg_card = s5p6450_setup_mshci_cfg_card; +#endif /* CONFIG_EXYNOS4_DEV_MSHC */ +} + +extern void exynos4_setup_mshci_cfg_gpio(struct platform_device *, int w); + +/* EXYNOS4 MSHCI setup */ +#ifdef CONFIG_EXYNOS4_SETUP_MSHCI +extern char *exynos4_mshci_clksrcs[1]; +#endif + +extern void exynos4_setup_mshci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + +extern void exynos4_setup_mshci_cfg_ddr(struct platform_device *dev, + int ddr); +extern void exynos4_setup_mshci_init_card(struct platform_device *dev); +extern void exynos4_setup_mshci_shutdown(void); + +extern void exynos4_setup_mshci_set_power(struct platform_device *dev, int en); + +#ifdef CONFIG_EXYNOS4_DEV_MSHC +static inline void exynos4_default_mshci(void) +{ + s3c_mshci_def_platdata.clocks = exynos4_mshci_clksrcs; + s3c_mshci_def_platdata.cfg_gpio = exynos4_setup_mshci_cfg_gpio; + s3c_mshci_def_platdata.cfg_card = exynos4_setup_mshci_cfg_card; + s3c_mshci_def_platdata.cfg_ddr = exynos4_setup_mshci_cfg_ddr; + s3c_mshci_def_platdata.init_card = exynos4_setup_mshci_init_card; + s3c_mshci_def_platdata.set_power = exynos4_setup_mshci_set_power; + s3c_mshci_def_platdata.shutdown = exynos4_setup_mshci_shutdown; +} +#else +static inline void exynos4_default_mshci(void) { } +#endif /* CONFIG_EXYNOS4_DEV_MSHC */ + +#endif /* __PLAT_S3C_MSHCI_H */ diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h index abb4bc3..832a403 100644 --- a/arch/arm/plat-samsung/include/plat/pd.h +++ b/arch/arm/plat-samsung/include/plat/pd.h @@ -11,20 +11,41 @@ #ifndef __ASM_PLAT_SAMSUNG_PD_H #define __ASM_PLAT_SAMSUNG_PD_H __FILE__ -struct samsung_pd_info { - int (*enable)(struct device *dev); - int (*disable)(struct device *dev); - void __iomem *base; -}; - -enum exynos4_pd_block { +enum exynos_pd_block { PD_MFC, PD_G3D, PD_LCD0, PD_LCD1, PD_TV, PD_CAM, - PD_GPS + PD_GPS, + PD_GPS_ALIVE, + PD_ISP, + PD_MAUDIO, + PD_GSCL, + PD_DISP1, + PD_TOP, +}; + +struct samsung_pd_info { + int (*init)(struct device *dev); + int (*enable)(struct device *dev); + int (*disable)(struct device *dev); + int (*save)(struct device *dev); + int (*restore)(struct device *dev); + void __iomem *base; + void *data; + enum exynos_pd_block id; +}; + +struct exynos_pd_data { + void __iomem *clk_base; + void __iomem *clksrc_base; + void __iomem *read_base; + unsigned long read_phy_addr; }; +int exynos_pd_init(struct device *dev); +int exynos_pd_enable(struct device *dev); +int exynos_pd_disable(struct device *dev); #endif /* __ASM_PLAT_SAMSUNG_PD_H */ diff --git a/arch/arm/plat-samsung/include/plat/pll6553x.h b/arch/arm/plat-samsung/include/plat/pll6553x.h new file mode 100644 index 0000000..b8b7e1d --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/pll6553x.h @@ -0,0 +1,51 @@ +/* arch/arm/plat-samsung/include/plat/pll6553x.h + * partially from arch/arm/mach-s3c64xx/include/mach/pll.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Samsung PLL6553x PLL code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* S3C6400 and compatible (S3C2416, etc.) EPLL code */ + +#define PLL6553X_MDIV_MASK ((1 << (23-16)) - 1) +#define PLL6553X_PDIV_MASK ((1 << (13-8)) - 1) +#define PLL6553X_SDIV_MASK ((1 << (2-0)) - 1) +#define PLL6553X_MDIV_SHIFT (16) +#define PLL6553X_PDIV_SHIFT (8) +#define PLL6553X_SDIV_SHIFT (0) +#define PLL6553X_KDIV_MASK (0xffff) + +static inline unsigned long s3c_get_pll6553x(unsigned long baseclk, + u32 pll0, u32 pll1) +{ + unsigned long result; + u32 mdiv, pdiv, sdiv, kdiv; + u64 tmp; + + mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK; + pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK; + sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK; + kdiv = pll1 & PLL6553X_KDIV_MASK; + + /* We need to multiple baseclk by mdiv (the integer part) and kdiv + * which is in 2^16ths, so shift mdiv up (does not overflow) and + * add kdiv before multiplying. The use of tmp is to avoid any + * overflows before shifting bac down into result when multipling + * by the mdiv and kdiv pair. + */ + + tmp = baseclk; + tmp *= (mdiv << 16) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 16; + + return result; +} diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index dcf6870..5a8aa39 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -42,7 +42,11 @@ extern unsigned long s3c_irqwake_eintallow; /* per-cpu sleep functions */ extern void (*pm_cpu_prep)(void); -extern int (*pm_cpu_sleep)(unsigned long); +extern void (*pm_cpu_sleep)(void); +extern void (*pm_cpu_restore)(void); +extern int (*pm_prepare)(void); +extern void (*pm_finish)(void); +extern unsigned int (*pm_check_eint_pend)(void); /* Flags for PM Control */ @@ -52,9 +56,10 @@ extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */ /* from sleep.S */ +extern int s3c_cpu_save(unsigned long *saveblk, long); extern void s3c_cpu_resume(void); -extern int s3c2410_cpu_suspend(unsigned long); +extern void s3c2410_cpu_suspend(void); /* sleep save info */ @@ -101,10 +106,12 @@ extern void s3c_pm_do_restore(struct sleep_save *ptr, int count); extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); #ifdef CONFIG_PM +extern int s3c_irq_wake(struct irq_data *data, unsigned int state); extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); extern int s3c24xx_irq_suspend(void); extern void s3c24xx_irq_resume(void); #else +#define s3c_irq_wake NULL #define s3c_irqext_wake NULL #define s3c24xx_irq_suspend NULL #define s3c24xx_irq_resume NULL @@ -127,7 +134,7 @@ extern void s3c_pm_dbg(const char *msg, ...); #define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt) #else -#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt) +#define S3C_PMDBG(fmt...) pr_debug(fmt) #endif #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK @@ -150,10 +157,10 @@ extern void s3c_pm_check_restore(void); extern void s3c_pm_check_cleanup(void); extern void s3c_pm_check_store(void); #else -#define s3c_pm_check_prepare() do { } while(0) -#define s3c_pm_check_restore() do { } while(0) -#define s3c_pm_check_cleanup() do { } while(0) -#define s3c_pm_check_store() do { } while(0) +#define s3c_pm_check_prepare() do { } while (0) +#define s3c_pm_check_restore() do { } while (0) +#define s3c_pm_check_cleanup() do { } while (0) +#define s3c_pm_check_store() do { } while (0) #endif /** @@ -165,20 +172,22 @@ extern void s3c_pm_check_store(void); extern void s3c_pm_configure_extint(void); /** - * samsung_pm_restore_gpios() - restore the state of the gpios after sleep. + * s3c_pm_restore_gpios() - restore the state of the gpios after sleep. * * Restore the state of the GPIO pins after sleep, which may involve ensuring * that we do not glitch the state of the pins from that the bootloader's * resume code has done. */ -extern void samsung_pm_restore_gpios(void); +extern void s3c_pm_restore_gpios(void); /** - * samsung_pm_save_gpios() - save the state of the GPIOs for restoring after sleep. + * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep. * - * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios(). + * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios(). */ -extern void samsung_pm_save_gpios(void); +extern void s3c_pm_save_gpios(void); extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); + +extern unsigned long s3c_suspend_wakeup_stat; diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h index 7061210..b0759b1 100644 --- a/arch/arm/plat-samsung/include/plat/regs-adc.h +++ b/arch/arm/plat-samsung/include/plat/regs-adc.h @@ -20,21 +20,21 @@ #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) #define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) -#define S3C2443_ADCMUX S3C2410_ADCREG(0x18) #define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) #define S5P_ADCMUX S3C2410_ADCREG(0x1C) #define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) /* ADCCON Register Bits */ +#define S3C64XX_ADCCON_TSSEL (1<<17) #define S3C64XX_ADCCON_RESSEL (1<<16) #define S3C2410_ADCCON_ECFLG (1<<15) #define S3C2410_ADCCON_PRSCEN (1<<14) #define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) #define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) #define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) +#define S5PV210_ADCCON_SELMUX(x) (((x)&0xF)<<0) #define S3C2410_ADCCON_MUXMASK (0x7<<3) -#define S3C2416_ADCCON_RESSEL (1 << 3) #define S3C2410_ADCCON_STDBM (1<<2) #define S3C2410_ADCCON_READ_START (1<<1) #define S3C2410_ADCCON_ENABLE_START (1<<0) @@ -42,7 +42,6 @@ /* ADCTSC Register Bits */ -#define S3C2443_ADCTSC_UD_SEN (1 << 8) #define S3C2410_ADCTSC_YM_SEN (1<<7) #define S3C2410_ADCTSC_YP_SEN (1<<6) #define S3C2410_ADCTSC_XM_SEN (1<<5) diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index 4c3647f..9c5534e 100644 --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h @@ -30,9 +30,17 @@ #define VIDCON1_FSTATUS_EVEN (1 << 15) /* Video timing controls */ +#ifdef CONFIG_FB_EXYNOS_FIMD_V8 +#define VIDTCON0 (0x20010) +#define VIDTCON1 (0x20014) +#define VIDTCON2 (0x20018) +#define VIDTCON3 (0x2001C) +#else #define VIDTCON0 (0x10) #define VIDTCON1 (0x14) #define VIDTCON2 (0x18) +#define VIDTCON3 (0x1C) +#endif /* Window position controls */ @@ -43,9 +51,12 @@ #define VIDOSD_BASE (0x40) #define VIDINTCON0 (0x130) +#define VIDINTCON1 (0x134) /* WINCONx */ +#define WINCONx_CSC_CON_EQ709 (1 << 28) +#define WINCONx_CSC_CON_EQ601 (0 << 28) #define WINCONx_CSCWIDTH_MASK (0x3 << 26) #define WINCONx_CSCWIDTH_SHIFT (26) #define WINCONx_CSCWIDTH_WIDE (0x0 << 26) diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h index 8f39aa5..f6c450b 100644 --- a/arch/arm/plat-samsung/include/plat/regs-fb.h +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h @@ -32,12 +32,27 @@ #define VIDCON0 (0x00) #define VIDCON0_INTERLACE (1 << 29) -#define VIDCON0_VIDOUT_MASK (0x3 << 26) + +#ifdef CONFIG_FB_EXYNOS_FIMD_V8 +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16) +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16) +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16) +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16) +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8) +#define VIDOUT_CON_VIDOUT_F_SHIFT (8) +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8) +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8) +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8) +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8) +#endif + +#define VIDCON0_VIDOUT_MASK (0x7 << 26) #define VIDCON0_VIDOUT_SHIFT (26) #define VIDCON0_VIDOUT_RGB (0x0 << 26) #define VIDCON0_VIDOUT_TV (0x1 << 26) #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) +#define VIDCON0_VIDOUT_WB (0x4 << 26) #define VIDCON0_L1_DATA_MASK (0x7 << 23) #define VIDCON0_L1_DATA_SHIFT (23) @@ -81,7 +96,17 @@ #define VIDCON0_ENVID (1 << 1) #define VIDCON0_ENVID_F (1 << 0) +#ifdef CONFIG_FB_EXYNOS_FIMD_V8 +#define VIDOUT_CON (0x20000) +#define VIDCON1 (0x20004) +#define REG_TIME2INIT (0x01b4) +#define REG_TIME2SNP (0x01b8) +#define DP_MIE_CLKCON (0x027c) +#define FREERUNCON (0x005c) +#else #define VIDCON1 (0x04) +#endif + #define VIDCON1_LINECNT_MASK (0x7ff << 16) #define VIDCON1_LINECNT_SHIFT (16) #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) @@ -90,7 +115,11 @@ #define VIDCON1_VSTATUS_VSYNC (0x0 << 13) #define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) #define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) -#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) +#define VIDCON1_VSTATUS_FRONTPORCH (0x3 << 13) +#define VIDCON1_VSTATUS_MASK (0x3 << 13) +#define VIDCON1_VCLK_MASK (0x3 << 9) +#define VIDCON1_VCLK_HOLD (0x0 << 9) +#define VIDCON1_VCLK_RUN (0x1 << 9) #define VIDCON1_INV_VCLK (1 << 7) #define VIDCON1_INV_HSYNC (1 << 6) @@ -99,18 +128,27 @@ /* VIDCON2 */ -#define VIDCON2 (0x08) -#define VIDCON2_EN601 (1 << 23) -#define VIDCON2_TVFMTSEL_SW (1 << 14) - -#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) -#define VIDCON2_TVFMTSEL1_SHIFT (12) -#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) -#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) -#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) - -#define VIDCON2_ORGYCbCr (1 << 8) -#define VIDCON2_YUVORDCrCb (1 << 7) +#define VIDCON2 (0x08) +#define VIDCON2_WB_SKIP_1_2 (1 << 0) +#define VIDCON2_WB_SKIP_1_3 (1 << 1) +#define VIDCON2_WB_SKIP_1_4 (3 << 0) +#define VIDCON2_WB_SKIP_1_5 (1 << 2) +#define VIDCON2_WB_SKIP_MASK (0x1f << 0) +#define VIDCON2_EN601 (1 << 23) +#define VIDCON2_WB_DISABLE (0 << 15) +#define VIDCON2_WB_ENABLE (1 << 15) +#define VIDCON2_WB_MASK (1 << 15) +#define VIDCON2_TVFORMATSEL_HW (0 << 14) +#define VIDCON2_TVFORMATSEL_SW (1 << 14) +#define VIDCON2_TVFORMATSEL_HW_SW_MASK (1 << 14) +#define VIDCON2_TVFORMATSEL_MASK (0x3 << 12) +#define VIDCON2_TVFORMATSEL_SHIFT (12) +#define VIDCON2_TVFORMATSEL_RGB (0x0 << 12) +#define VIDCON2_TVFORMATSEL_YUV422 (0x1 << 12) +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12) + +#define VIDCON2_ORGYCbCr (1 << 8) +#define VIDCON2_YUVORDCrCb (1 << 7) /* PRTCON (S3C6410, S5PC100) * Might not be present in the S3C6410 documentation, @@ -163,24 +201,29 @@ #define VIDTCON1_HSPW_LIMIT (0xff) #define VIDTCON1_HSPW(_x) ((_x) << 0) -#define VIDTCON2 (0x18) +/* VIDTCON2 */ + +#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) #define VIDTCON2_LINEVAL_SHIFT (11) #define VIDTCON2_LINEVAL_LIMIT (0x7ff) -#define VIDTCON2_LINEVAL(_x) ((_x) << 11) +#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11) +#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22) #define VIDTCON2_HOZVAL_MASK (0x7ff << 0) #define VIDTCON2_HOZVAL_SHIFT (0) #define VIDTCON2_HOZVAL_LIMIT (0x7ff) -#define VIDTCON2_HOZVAL(_x) ((_x) << 0) +#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0) /* WINCONx */ - #define WINCONx_BITSWP (1 << 18) #define WINCONx_BYTSWP (1 << 17) #define WINCONx_HAWSWP (1 << 16) #define WINCONx_WSWP (1 << 15) +#define WINCONx_ENLOCAL_MASK (0xf << 15) +#define WINCONx_INRGB_RGB (0 << 13) +#define WINCONx_INRGB_YCBCR (1 << 13) #define WINCONx_BURSTLEN_MASK (0x3 << 9) #define WINCONx_BURSTLEN_SHIFT (9) #define WINCONx_BURSTLEN_16WORD (0x0 << 9) @@ -200,6 +243,7 @@ #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) #define WINCON1_BLD_PIX (1 << 6) +#define WINCON1_BLD_PLANE (0 << 6) #define WINCON1_ALPHA_SEL (1 << 1) #define WINCON1_BPPMODE_MASK (0xf << 2) @@ -228,25 +272,29 @@ /* Local input channels (windows 0-2) */ #define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win))) +#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) #define VIDOSDxA_TOPLEFT_X_SHIFT (11) #define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) -#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11) +#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11) +#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22) #define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) #define VIDOSDxA_TOPLEFT_Y_SHIFT (0) #define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) -#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0) +#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0) +#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) #define VIDOSDxB_BOTRIGHT_X_SHIFT (11) #define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) -#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11) +#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11) +#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22) #define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) #define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) #define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) -#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0) +#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0) /* For VIDOSD[1..4]C */ #define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) @@ -278,15 +326,17 @@ #define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) #define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) +#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27) #define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) #define VIDW_BUF_SIZE_OFFSET_SHIFT (13) #define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) -#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13) +#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13) +#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26) #define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) #define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) #define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) -#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0) +#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0) /* Interrupt controls and status */ @@ -384,3 +434,22 @@ #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0) #define WPALCON_W0PAL_16BPP_565 (0x6 << 0) +/* Clock gate mode control */ +#define REG_CLKGATE_MODE (0x1b0) +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0) +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0) + +/* Blending equation control */ +#define BLENDCON (0x260) +#define BLENDCON_NEW_MASK (1 << 0) +#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) +#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) + +/* DP clock control */ +#define DPCLKCON (0x27c) +#define DPCLKCON_ENABLE (1 << 1) + +/* Window alpha control */ +#define VIDW0ALPHA0 (0x200) +#define VIDW0ALPHA1 (0x204) +#define DUALRGB (0x27c) diff --git a/arch/arm/plat-samsung/include/plat/regs-otg.h b/arch/arm/plat-samsung/include/plat/regs-otg.h new file mode 100644 index 0000000..baeda10 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-otg.h @@ -0,0 +1,260 @@ +/* linux/arch/arm/plat-samsung/include/plat/regs-otg.h + * + * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at> + * + * This include file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. +*/ + +#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H +#define __ASM_ARCH_REGS_USB_OTG_HS_H + +/* USB2.0 OTG Controller register */ +#define S3C_USBOTG_PHYREG(x) ((x) + S3C_VA_HSPHY) +#define S3C_USBOTG_PHYPWR S3C_USBOTG_PHYREG(0x0) +#define S3C_USBOTG_PHYCLK S3C_USBOTG_PHYREG(0x4) +#define S3C_USBOTG_RSTCON S3C_USBOTG_PHYREG(0x8) +#define S3C_USBOTG_PHYTUNE S3C_USBOTG_PHYREG(0x24) +#define S3C_USBOTG_PHY1CON S3C_USBOTG_PHYREG(0x34) + +/* USB2.0 OTG Controller register */ +#define S3C_USBOTGREG(x) (x) +/*============================================================================================== */ + /* Core Global Registers */ +#define S3C_UDC_OTG_GOTGCTL S3C_USBOTGREG(0x000) /* OTG Control & Status */ +#define S3C_UDC_OTG_GOTGINT S3C_USBOTGREG(0x004) /* OTG Interrupt */ +#define S3C_UDC_OTG_GAHBCFG S3C_USBOTGREG(0x008) /* Core AHB Configuration */ +#define S3C_UDC_OTG_GUSBCFG S3C_USBOTGREG(0x00C) /* Core USB Configuration */ +#define S3C_UDC_OTG_GRSTCTL S3C_USBOTGREG(0x010) /* Core Reset */ +#define S3C_UDC_OTG_GINTSTS S3C_USBOTGREG(0x014) /* Core Interrupt */ +#define S3C_UDC_OTG_GINTMSK S3C_USBOTGREG(0x018) /* Core Interrupt Mask */ +#define S3C_UDC_OTG_GRXSTSR S3C_USBOTGREG(0x01C) /* Receive Status Debug Read/Status Read */ +#define S3C_UDC_OTG_GRXSTSP S3C_USBOTGREG(0x020) /* Receive Status Debug Pop/Status Pop */ +#define S3C_UDC_OTG_GRXFSIZ S3C_USBOTGREG(0x024) /* Receive FIFO Size */ +#define S3C_UDC_OTG_GNPTXFSIZ S3C_USBOTGREG(0x028) /* Non-Periodic Transmit FIFO Size */ +#define S3C_UDC_OTG_GNPTXSTS S3C_USBOTGREG(0x02C) /* Non-Periodic Transmit FIFO/Queue Status */ + +#define S3C_UDC_OTG_HPTXFSIZ S3C_USBOTGREG(0x100) /* Host Periodic Transmit FIFO Size */ +#define S3C_UDC_OTG_DIEPTXF(n) S3C_USBOTGREG(0x104 + (n-1)*0x4)/* Device IN EP Transmit FIFO Size Register */ + +/*============================================================================================== */ +/* Host Mode Registers */ +/*------------------------------------------------ */ +/* Host Global Registers */ +#define S3C_UDC_OTG_HCFG S3C_USBOTGREG(0x400) /* Host Configuration */ +#define S3C_UDC_OTG_HFIR S3C_USBOTGREG(0x404) /* Host Frame Interval */ +#define S3C_UDC_OTG_HFNUM S3C_USBOTGREG(0x408) /* Host Frame Number/Frame Time Remaining */ +#define S3C_UDC_OTG_HPTXSTS S3C_USBOTGREG(0x410) /* Host Periodic Transmit FIFO/Queue Status */ +#define S3C_UDC_OTG_HAINT S3C_USBOTGREG(0x414) /* Host All Channels Interrupt */ +#define S3C_UDC_OTG_HAINTMSK S3C_USBOTGREG(0x418) /* Host All Channels Interrupt Mask */ + +/*------------------------------------------------ */ +/* Host Port Control & Status Registers */ +#define S3C_UDC_OTG_HPRT S3C_USBOTGREG(0x440) /* Host Port Control & Status */ + +/*------------------------------------------------ */ +/* Host Channel-Specific Registers */ +#define S3C_UDC_OTG_HCCHAR0 S3C_USBOTGREG(0x500) /* Host Channel-0 Characteristics */ +#define S3C_UDC_OTG_HCSPLT0 S3C_USBOTGREG(0x504) /* Host Channel-0 Split Control */ +#define S3C_UDC_OTG_HCINT0 S3C_USBOTGREG(0x508) /* Host Channel-0 Interrupt */ +#define S3C_UDC_OTG_HCINTMSK0 S3C_USBOTGREG(0x50C) /* Host Channel-0 Interrupt Mask */ +#define S3C_UDC_OTG_HCTSIZ0 S3C_USBOTGREG(0x510) /* Host Channel-0 Transfer Size */ +#define S3C_UDC_OTG_HCDMA0 S3C_USBOTGREG(0x514) /* Host Channel-0 DMA Address */ + +/*============================================================================================== */ +/* Device Mode Registers */ +/*------------------------------------------------ */ +/* Device Global Registers */ +#define S3C_UDC_OTG_DCFG S3C_USBOTGREG(0x800) /* Device Configuration */ +#define S3C_UDC_OTG_DCTL S3C_USBOTGREG(0x804) /* Device Control */ +#define S3C_UDC_OTG_DSTS S3C_USBOTGREG(0x808) /* Device Status */ +#define S3C_UDC_OTG_DIEPMSK S3C_USBOTGREG(0x810) /* Device IN Endpoint Common Interrupt Mask */ +#define S3C_UDC_OTG_DOEPMSK S3C_USBOTGREG(0x814) /* Device OUT Endpoint Common Interrupt Mask */ +#define S3C_UDC_OTG_DAINT S3C_USBOTGREG(0x818) /* Device All Endpoints Interrupt */ +#define S3C_UDC_OTG_DAINTMSK S3C_USBOTGREG(0x81C) /* Device All Endpoints Interrupt Mask */ +#define S3C_UDC_OTG_DTKNQR1 S3C_USBOTGREG(0x820) /* Device IN Token Sequence Learning Queue Read 1 */ +#define S3C_UDC_OTG_DTKNQR2 S3C_USBOTGREG(0x824) /* Device IN Token Sequence Learning Queue Read 2 */ +#define S3C_UDC_OTG_DVBUSDIS S3C_USBOTGREG(0x828) /* Device VBUS Discharge Time */ +#define S3C_UDC_OTG_DVBUSPULSE S3C_USBOTGREG(0x82C) /* Device VBUS Pulsing Time */ +#define S3C_UDC_OTG_DTKNQR3 S3C_USBOTGREG(0x830) /* Device IN Token Sequence Learning Queue Read 3 */ +#define S3C_UDC_OTG_DTKNQR4 S3C_USBOTGREG(0x834) /* Device IN Token Sequence Learning Queue Read 4 */ + +/*------------------------------------------------ */ +/* Device Logical IN Endpoint-Specific Registers */ +#define S3C_UDC_OTG_DIEPCTL(n) S3C_USBOTGREG(0x900 + n*0x20) /* Device IN Endpoint n Control */ +#define S3C_UDC_OTG_DIEPINT(n) S3C_USBOTGREG(0x908 + n*0x20) /* Device IN Endpoint n Interrupt */ +#define S3C_UDC_OTG_DIEPTSIZ(n) S3C_USBOTGREG(0x910 + n*0x20) /* Device IN Endpoint n Transfer Size */ +#define S3C_UDC_OTG_DIEPDMA(n) S3C_USBOTGREG(0x914 + n*0x20) /* Device IN Endpoint n DMA Address */ + +/*------------------------------------------------ */ +/* Device Logical OUT Endpoint-Specific Registers */ +#define S3C_UDC_OTG_DOEPCTL(n) S3C_USBOTGREG(0xB00 + n*0x20) /* Device OUT Endpoint n Control */ +#define S3C_UDC_OTG_DOEPINT(n) S3C_USBOTGREG(0xB08 + n*0x20) /* Device OUT Endpoint n Interrupt */ +#define S3C_UDC_OTG_DOEPTSIZ(n) S3C_USBOTGREG(0xB10 + n*0x20) /* Device OUT Endpoint n Transfer Size */ +#define S3C_UDC_OTG_DOEPDMA(n) S3C_USBOTGREG(0xB14 + n*0x20) /* Device OUT Endpoint n DMA Address */ + +/*------------------------------------------------ */ +/* Endpoint FIFO address */ +#define S3C_UDC_OTG_EP0_FIFO S3C_USBOTGREG(0x1000) +#define S3C_UDC_OTG_EP1_FIFO S3C_USBOTGREG(0x2000) +#define S3C_UDC_OTG_EP2_FIFO S3C_USBOTGREG(0x3000) +#define S3C_UDC_OTG_EP3_FIFO S3C_USBOTGREG(0x4000) +#define S3C_UDC_OTG_EP4_FIFO S3C_USBOTGREG(0x5000) +#define S3C_UDC_OTG_EP5_FIFO S3C_USBOTGREG(0x6000) +#define S3C_UDC_OTG_EP6_FIFO S3C_USBOTGREG(0x7000) +#define S3C_UDC_OTG_EP7_FIFO S3C_USBOTGREG(0x8000) +#define S3C_UDC_OTG_EP8_FIFO S3C_USBOTGREG(0x9000) +#define S3C_UDC_OTG_EP9_FIFO S3C_USBOTGREG(0xA000) +#define S3C_UDC_OTG_EP10_FIFO S3C_USBOTGREG(0xB000) +#define S3C_UDC_OTG_EP11_FIFO S3C_USBOTGREG(0xC000) +#define S3C_UDC_OTG_EP12_FIFO S3C_USBOTGREG(0xD000) +#define S3C_UDC_OTG_EP13_FIFO S3C_USBOTGREG(0xE000) +#define S3C_UDC_OTG_EP14_FIFO S3C_USBOTGREG(0xF000) +#define S3C_UDC_OTG_EP15_FIFO S3C_USBOTGREG(0x10000) + +/*===================================================================== */ +/*definitions related to CSR setting */ + +/* S3C_UDC_OTG_GOTGCTL */ +#define B_SESSION_VALID (0x1<<19) +#define A_SESSION_VALID (0x1<<18) + +/* S3C_UDC_OTG_GAHBCFG */ +#define PTXFE_HALF (0<<8) +#define PTXFE_ZERO (1<<8) +#define NPTXFE_HALF (0<<7) +#define NPTXFE_ZERO (1<<7) +#define MODE_SLAVE (0<<5) +#define MODE_DMA (1<<5) +#define BURST_SINGLE (0<<1) +#define BURST_INCR (1<<1) +#define BURST_INCR4 (3<<1) +#define BURST_INCR8 (5<<1) +#define BURST_INCR16 (7<<1) +#define GBL_INT_UNMASK (1<<0) +#define GBL_INT_MASK (0<<0) + +/* S3C_UDC_OTG_GRSTCTL */ +#define AHB_MASTER_IDLE (1u<<31) +#define CORE_SOFT_RESET (0x1<<0) + +/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */ +#define INT_RESUME (1u<<31) +#define INT_DISCONN (0x1<<29) +#define INT_CONN_ID_STS_CNG (0x1<<28) +#define INT_OUT_EP (0x1<<19) +#define INT_IN_EP (0x1<<18) +#define INT_ENUMDONE (0x1<<13) +#define INT_RESET (0x1<<12) +#define INT_SUSPEND (0x1<<11) +#define INT_EARLY_SUSPEND (0x1<<10) +#define INT_NP_TX_FIFO_EMPTY (0x1<<5) +#define INT_RX_FIFO_NOT_EMPTY (0x1<<4) +#define INT_SOF (0x1<<3) +#define INT_DEV_MODE (0x0<<0) +#define INT_HOST_MODE (0x1<<1) +#define INT_GOUTNakEff (0x01<<7) +#define INT_GINNakEff (0x01<<6) + +#define FULL_SPEED_CONTROL_PKT_SIZE 8 +#define FULL_SPEED_BULK_PKT_SIZE 64 + +#define HIGH_SPEED_CONTROL_PKT_SIZE 64 +#define HIGH_SPEED_BULK_PKT_SIZE 512 + +#ifdef CONFIG_CPU_S5P6450 +#define RX_FIFO_SIZE (4096>>2) +#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE +#define NPTX_FIFO_SIZE (4096>>2) +#define PTX_FIFO_SIZE (1520>>2) +#else +#define RX_FIFO_SIZE (4096>>2) +#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE +#define NPTX_FIFO_SIZE (4096>>2) +#define PTX_FIFO_SIZE (1024>>2) +#endif + +/* Enumeration speed */ +#define USB_HIGH_30_60MHZ (0x0<<1) +#define USB_FULL_30_60MHZ (0x1<<1) +#define USB_LOW_6MHZ (0x2<<1) +#define USB_FULL_48MHZ (0x3<<1) + +/* S3C_UDC_OTG_GRXSTSP STATUS */ +#define OUT_PKT_RECEIVED (0x2<<17) +#define OUT_TRANSFER_COMPLELTED (0x3<<17) +#define SETUP_TRANSACTION_COMPLETED (0x4<<17) +#define SETUP_PKT_RECEIVED (0x6<<17) +#define GLOBAL_OUT_NAK (0x1<<17) + +/* S3C_UDC_OTG_DCTL device control register */ +#define NORMAL_OPERATION (0x1<<0) +#define SOFT_DISCONNECT (0x1<<1) +#define TEST_CONTROL_MASK (0x7<<4) +#define TEST_J_MODE (0x1<<4) +#define TEST_K_MODE (0x2<<4) +#define TEST_SE0_NAK_MODE (0x3<<4) +#define TEST_PACKET_MODE (0x4<<4) +#define TEST_FORCE_ENABLE_MODE (0x5<<4) + +/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */ +#define DAINT_OUT_BIT (16) +#define DAINT_MASK (0xFFFF) + +/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device control IN/OUT endpoint 0 control register */ +#define DEPCTL_EPENA (0x1<<31) +#define DEPCTL_EPDIS (0x1<<30) +#define DEPCTL_SETD1PID (0x1<<29) +#define DEPCTL_SETD0PID (0x1<<28) +#define DEPCTL_SNAK (0x1<<27) +#define DEPCTL_CNAK (0x1<<26) +#define DEPCTL_STALL (0x1<<21) +#define DEPCTL_TYPE_BIT (18) +#define DEPCTL_TXFNUM_BIT (22) +#define DEPCTL_TXFNUM_MASK (0xF<<22) +#define DEPCTL_TYPE_MASK (0x3<<18) +#define DEPCTL_CTRL_TYPE (0x0<<18) +#define DEPCTL_ISO_TYPE (0x1<<18) +#define DEPCTL_BULK_TYPE (0x2<<18) +#define DEPCTL_INTR_TYPE (0x3<<18) +#define DEPCTL_NAKSTS (0x1<<17) +#define DEPCTL_USBACTEP (0x1<<15) +#define DEPCTL_NEXT_EP_BIT (11) +#define DEPCTL_MPS_BIT (0) +#define DEPCTL_MPS_MASK (0x7FF) + +#define DEPCTL0_MPS_64 (0x0<<0) +#define DEPCTL0_MPS_32 (0x1<<0) +#define DEPCTL0_MPS_16 (0x2<<0) +#define DEPCTL0_MPS_8 (0x3<<0) +#define DEPCTL_MPS_BULK_512 (512<<0) +#define DEPCTL_MPS_INT_MPS_16 (16<<0) + +#define DIEPCTL0_NEXT_EP_BIT (11) + +/* S3C_UDC_OTG_DIEPCTLn/DOEPCTLn device control IN/OUT endpoint n control register */ + +/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint common interrupt mask register */ +/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */ +#define BACK2BACK_SETUP_RECEIVED (0x1<<6) +#define INTKNEPMIS (0x1<<5) +#define INTKN_TXFEMP (0x1<<4) +#define NON_ISO_IN_EP_TIMEOUT (0x1<<3) +#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3) +#define AHB_ERROR (0x1<<2) +#define EPDISBLD (0x1<<1) +#define TRANSFER_DONE (0x1<<0) + +/*DIEPTSIZ0 / DOEPTSIZ0 */ + +/* DEPTSIZ common bit */ +#define DEPTSIZ_PKT_CNT_BIT (19) +#define DEPTSIZ_XFER_SIZE_BIT (0) + +#define DEPTSIZ_SETUP_PKCNT_1 (1<<29) +#define DEPTSIZ_SETUP_PKCNT_2 (2<<29) +#define DEPTSIZ_SETUP_PKCNT_3 (3<<29) + +#endif diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h index 7207348..5adf78f 100644 --- a/arch/arm/plat-samsung/include/plat/regs-serial.h +++ b/arch/arm/plat-samsung/include/plat/regs-serial.h @@ -155,6 +155,14 @@ #define S3C2410_UFSTAT_RXMASK (15<<0) #define S3C2410_UFSTAT_RXSHIFT (0) +/* UFSTAT S3C24A0 */ +#define S3C24A0_UFSTAT_TXFULL (1 << 14) +#define S3C24A0_UFSTAT_RXFULL (1 << 6) +#define S3C24A0_UFSTAT_TXMASK (63 << 8) +#define S3C24A0_UFSTAT_TXSHIFT (8) +#define S3C24A0_UFSTAT_RXMASK (63) +#define S3C24A0_UFSTAT_RXSHIFT (0) + /* UFSTAT S3C2443 same as S3C2440 */ #define S3C2440_UFSTAT_TXFULL (1<<14) #define S3C2440_UFSTAT_RXFULL (1<<6) @@ -186,11 +194,6 @@ #define S3C64XX_UINTSP 0x34 #define S3C64XX_UINTM 0x38 -#define S3C64XX_UINTM_RXD (0) -#define S3C64XX_UINTM_TXD (2) -#define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD) -#define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD) - /* Following are specific to S5PV210 */ #define S5PV210_UCON_CLKMASK (1<<10) #define S5PV210_UCON_PCLK (0<<10) @@ -252,6 +255,8 @@ struct s3c24xx_uart_clksrc { * arch/arm/mach-s3c2410/ directory. */ +struct uart_port; + struct s3c2410_uartcfg { unsigned char hwport; /* hardware port number */ unsigned char unused; @@ -266,6 +271,9 @@ struct s3c2410_uartcfg { struct s3c24xx_uart_clksrc *clocks; unsigned int clocks_size; + + void (*wake_peer)(struct uart_port *); + void (*set_runstate)(int onoff); }; /* s3c24xx_uart_devs @@ -279,4 +287,3 @@ extern struct platform_device *s3c24xx_uart_devs[4]; #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_REGS_SERIAL_H */ - diff --git a/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h new file mode 100644 index 0000000..50d2954 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h @@ -0,0 +1,75 @@ +/* arch/arm/plat-samsung/include/plat/regs-usb3-exynos-udc-drd.h + * + * Copyright (c) 2011 Samsung Electronics Co. Ltd + * Author: Anton Tikhomirov <av.tikhomirov@samsung.com> + * + * Exynos SuperSpeed USB 3.0 DRD Controller PHY registers + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_SAMSUNG_REGS_USB3_EXYNOS_DRD_PHY_H +#define __PLAT_SAMSUNG_REGS_USB3_EXYNOS_DRD_PHY_H __FILE__ + +#define EXYNOS_USB3_PHYREG(x) ((x) + S5P_VA_SS_PHY) + + +#define EXYNOS_USB3_LINKSYSTEM EXYNOS_USB3_PHYREG(0x04) +#define EXYNOS_USB3_PHYUTMI EXYNOS_USB3_PHYREG(0x08) + +#define EXYNOS_USB3_PHYUTMI_OTGDISABLE (1 << 6) +#define EXYNOS_USB3_PHYUTMI_FORCESUSPEND (1 << 1) +#define EXYNOS_USB3_PHYUTMI_FORCESLEEP (1 << 0) + +#define EXYNOS_USB3_PHYPIPE EXYNOS_USB3_PHYREG(0x0C) + + +#define EXYNOS_USB3_PHYCLKRST EXYNOS_USB3_PHYREG(0x10) + +#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL_MASK (0xff << 23) +#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL_SHIFT (23) +#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL_LIMIT (0xff) +#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(_x) ((_x) << 23) + +#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) +#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE_SHIFT (21) +#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE_LIMIT (0x03) +#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) + +#define EXYNOS_USB3_PHYCLKRST_SSC_EN (1 << 20) +#define EXYNOS_USB3_PHYCLKRST_REF_SSP_EN (1 << 19) +#define EXYNOS_USB3_PHYCLKRST_REF_CLKDIV2 (1 << 18) + +#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) +#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER_SHIFT (11) +#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER_LIMIT (0x7f) +#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(_x) ((_x) << 11) + +#define EXYNOS_USB3_PHYCLKRST_FSEL_MASK (0x3f << 5) +#define EXYNOS_USB3_PHYCLKRST_FSEL_SHIFT (5) +#define EXYNOS_USB3_PHYCLKRST_FSEL_LIMIT (0x3f) +#define EXYNOS_USB3_PHYCLKRST_FSEL(_x) ((_x) << 5) + +#define EXYNOS_USB3_PHYCLKRST_RETENABLEN (1 << 4) + +#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) +#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL_SHIFT (2) +#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL_LIMIT (0x03) +#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL(_x) ((_x) << 2) + +#define EXYNOS_USB3_PHYCLKRST_PORTRESET (1 << 1) +#define EXYNOS_USB3_PHYCLKRST_COMMONONN (1 << 0) + +#define EXYNOS_USB3_PHYREG0 EXYNOS_USB3_PHYREG(0x14) +#define EXYNOS_USB3_PHYREG1 EXYNOS_USB3_PHYREG(0x18) +#define EXYNOS_USB3_PHYPARAM0 EXYNOS_USB3_PHYREG(0x1C) +#define EXYNOS_USB3_PHYPARAM1 EXYNOS_USB3_PHYREG(0x20) +#define EXYNOS_USB3_PHYTERM EXYNOS_USB3_PHYREG(0x24) +#define EXYNOS_USB3_PHYTEST EXYNOS_USB3_PHYREG(0x28) +#define EXYNOS_USB3_PHYADP EXYNOS_USB3_PHYREG(0x2C) +#define EXYNOS_USB3_PHYBATCHG EXYNOS_USB3_PHYREG(0x30) +#define EXYNOS_USB3_PHYRESUME EXYNOS_USB3_PHYREG(0x34) +#define EXYNOS_USB3_LINKPORT EXYNOS_USB3_PHYREG(0x44) +#endif /* __PLAT_SAMSUNG_REGS_USB3_EXYNOS_DRD_PHY_H */ diff --git a/arch/arm/plat-samsung/include/plat/rtc-core.h b/arch/arm/plat-samsung/include/plat/rtc-core.h new file mode 100644 index 0000000..65967ca --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/rtc-core.h @@ -0,0 +1,28 @@ +/* linux/arch/arm/plat-samsung/include/plat/rtc-core.h + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Samsung RTC Device core function + * + * This program is free software; you can redistribute it and/or modify + * it under the term of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_PLAT_RTC_CORE_H +#define __ASM_PLAT_RTC_CORE_H __FILE__ + +/* These function are only for use with the core support code, such as + * the cpu specific initialization code + */ + +/* re-define device name depending on support. */ +static inline void s3c_rtc_setname(char *name) +{ +#ifdef CONFIG_S3C_DEV_RTC + s3c_device_rtc.name = name; +#endif +} + +#endif /* __ASM_PLAT_RTC_CORE_H */ diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h new file mode 100644 index 0000000..ee155ad --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __S3C_DMA_PL330_H_ +#define __S3C_DMA_PL330_H_ + +#define S3C2410_DMAF_AUTOSTART (1 << 0) +#define S3C2410_DMAF_CIRCULAR (1 << 1) + +/* + * PL330 can assign any channel to communicate with + * any of the peripherals attched to the DMAC. + * For the sake of consistency across client drivers, + * We keep the channel names unchanged and only add + * missing peripherals are added. + * Order is not important since S3C PL330 API driver + * use these just as IDs. + */ +enum dma_ch { + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART1_RX, + DMACH_UART1_TX, + DMACH_UART2_RX, + DMACH_UART2_TX, + DMACH_UART3_RX, + DMACH_UART3_TX, + DMACH_UART4_RX, + DMACH_UART4_TX, + DMACH_UART5_RX, + DMACH_UART5_TX, + DMACH_USI_RX, + DMACH_USI_TX, + DMACH_IRDA, + DMACH_I2S0_RX, + DMACH_I2S0_TX, + DMACH_I2S0S_TX, + DMACH_I2S1_RX, + DMACH_I2S1_TX, + DMACH_I2S2_RX, + DMACH_I2S2_TX, + DMACH_SPI0_RX, + DMACH_SPI0_TX, + DMACH_SPI1_RX, + DMACH_SPI1_TX, + DMACH_SPI2_RX, + DMACH_SPI2_TX, + DMACH_AC97_MICIN, + DMACH_AC97_PCMIN, + DMACH_AC97_PCMOUT, + DMACH_EXTERNAL, + DMACH_PWM, + DMACH_SPDIF, + DMACH_HSI_RX, + DMACH_HSI_TX, + DMACH_PCM0_TX, + DMACH_PCM0_RX, + DMACH_PCM1_TX, + DMACH_PCM1_RX, + DMACH_PCM2_TX, + DMACH_PCM2_RX, + DMACH_MSM_REQ3, + DMACH_MSM_REQ2, + DMACH_MSM_REQ1, + DMACH_MSM_REQ0, + DMACH_SLIMBUS0_RX, + DMACH_SLIMBUS0_TX, + DMACH_SLIMBUS0AUX_RX, + DMACH_SLIMBUS0AUX_TX, + DMACH_SLIMBUS1_RX, + DMACH_SLIMBUS1_TX, + DMACH_SLIMBUS2_RX, + DMACH_SLIMBUS2_TX, + DMACH_SLIMBUS3_RX, + DMACH_SLIMBUS3_TX, + DMACH_SLIMBUS4_RX, + DMACH_SLIMBUS4_TX, + DMACH_SLIMBUS5_RX, + DMACH_SLIMBUS5_TX, + DMACH_MIPI_HSI0, + DMACH_MIPI_HSI1, + DMACH_MIPI_HSI2, + DMACH_MIPI_HSI3, + DMACH_MIPI_HSI4, + DMACH_MIPI_HSI5, + DMACH_MIPI_HSI6, + DMACH_MIPI_HSI7, + DMACH_DISP1, + DMACH_MTOM_0, + DMACH_MTOM_1, + DMACH_MTOM_2, + DMACH_MTOM_3, + DMACH_MTOM_4, + DMACH_MTOM_5, + DMACH_MTOM_6, + DMACH_MTOM_7, + /* END Marker, also used to denote a reserved channel */ + DMACH_MAX, +}; + +static inline bool s3c_dma_has_circular(void) +{ + return true; +} + +static inline bool s3c_dma_has_infiniteloop(void) +{ + return true; +} + +#include <plat/dma.h> + +#endif /* __S3C_DMA_PL330_H_ */ diff --git a/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h b/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h new file mode 100644 index 0000000..bf5e2a9 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h @@ -0,0 +1,32 @@ +/* linux/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __S3C_PL330_PDATA_H +#define __S3C_PL330_PDATA_H + +#include <plat/s3c-dma-pl330.h> + +/* + * Every PL330 DMAC has max 32 peripheral interfaces, + * of which some may be not be really used in your + * DMAC's configuration. + * Populate this array of 32 peri i/fs with relevant + * channel IDs for used peri i/f and DMACH_MAX for + * those unused. + * + * The platforms just need to provide this info + * to the S3C DMA API driver for PL330. + */ +struct s3c_pl330_platdata { + enum dma_ch peri[32]; +}; + +#endif /* __S3C_PL330_PDATA_H */ diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index 4c16fa3..353ceb6 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -71,5 +71,6 @@ extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); +extern void exynos_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); #endif /* __S3C64XX_PLAT_SPI_H */ diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index e7b3c75..2b7fe51 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -18,6 +18,8 @@ #ifndef __PLAT_S3C_SDHCI_H #define __PLAT_S3C_SDHCI_H __FILE__ +/* ignore mmc suspend/resume for BCM WIFI */ +#define S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME (1 << 30) struct platform_device; struct mmc_host; struct mmc_card; @@ -55,6 +57,10 @@ enum clk_types { * cd_type == S3C_SDHCI_CD_GPIO * @ext_cd_gpio_invert: invert values for external CD gpio line * @cfg_gpio: Configure the GPIO for a specific card bit-width + * @cfg_card: Configure the interface for a specific card and speed. This + * is necessary the controllers and/or GPIO blocks require the + * changing of driver-strength and other controls dependent on + * the card and speed of operation. * * Initialisation data specific to either the machine or the platform * for the device driver to use or call-back when configuring gpio or @@ -68,22 +74,29 @@ struct s3c_sdhci_platdata { char **clocks; /* set of clock sources */ + char *vmmc_name; /* name for regulator */ int ext_cd_gpio; bool ext_cd_gpio_invert; + unsigned int pm_flags; + int (*ext_cd_init)(void (*notify_func)(struct platform_device *, int state)); int (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *, int state)); void (*cfg_gpio)(struct platform_device *dev, int width); -}; + void (*cfg_card)(struct platform_device *dev, + void __iomem *regbase, + struct mmc_ios *ios, + struct mmc_card *card); +#ifdef CONFIG_WIMAX_CMC + int enable_intr_on_resume; +#endif +#ifdef CONFIG_MACH_PX + int (*ext_pdev)(struct platform_device *dev_id); +#endif -/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data - * @pd: The default platform data for this device. - * @set: Pointer to the platform data to fill in. - */ -extern void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd, - struct s3c_sdhci_platdata *set); +}; /** * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device. @@ -125,17 +138,27 @@ extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w); extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w); extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w); extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); +extern void exynos5_setup_sdhci0_cfg_gpio(struct platform_device *, int w); +extern void exynos5_setup_sdhci1_cfg_gpio(struct platform_device *, int w); +extern void exynos5_setup_sdhci2_cfg_gpio(struct platform_device *, int w); +extern void exynos5_setup_sdhci3_cfg_gpio(struct platform_device *, int w); /* S3C2416 SDHCI setup */ #ifdef CONFIG_S3C2416_SETUP_SDHCI extern char *s3c2416_hsmmc_clksrcs[4]; +extern void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + static inline void s3c2416_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card; #endif /* CONFIG_S3C_DEV_HSMMC */ } @@ -144,6 +167,7 @@ static inline void s3c2416_default_sdhci1(void) #ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card; #endif /* CONFIG_S3C_DEV_HSMMC1 */ } @@ -157,11 +181,17 @@ static inline void s3c2416_default_sdhci1(void) { } #ifdef CONFIG_S3C64XX_SETUP_SDHCI extern char *s3c64xx_hsmmc_clksrcs[4]; +extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + static inline void s3c6400_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; #endif } @@ -170,6 +200,7 @@ static inline void s3c6400_default_sdhci1(void) #ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; #endif } @@ -178,14 +209,21 @@ static inline void s3c6400_default_sdhci2(void) #ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; + s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; #endif } +extern void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + static inline void s3c6410_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; #endif } @@ -194,6 +232,7 @@ static inline void s3c6410_default_sdhci1(void) #ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; #endif } @@ -202,6 +241,7 @@ static inline void s3c6410_default_sdhci2(void) #ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; + s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; #endif } @@ -220,11 +260,17 @@ static inline void s3c6400_default_sdhci2(void) { } #ifdef CONFIG_S5PC100_SETUP_SDHCI extern char *s5pc100_hsmmc_clksrcs[4]; +extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + static inline void s5pc100_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card; #endif } @@ -233,6 +279,7 @@ static inline void s5pc100_default_sdhci1(void) #ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card; #endif } @@ -241,6 +288,7 @@ static inline void s5pc100_default_sdhci2(void) #ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; + s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card; #endif } @@ -256,11 +304,17 @@ static inline void s5pc100_default_sdhci2(void) { } #ifdef CONFIG_S5PV210_SETUP_SDHCI extern char *s5pv210_hsmmc_clksrcs[4]; +extern void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + static inline void s5pv210_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; #endif } @@ -269,6 +323,7 @@ static inline void s5pv210_default_sdhci1(void) #ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; #endif } @@ -277,6 +332,7 @@ static inline void s5pv210_default_sdhci2(void) #ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; + s3c_hsmmc2_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; #endif } @@ -285,6 +341,7 @@ static inline void s5pv210_default_sdhci3(void) #ifdef CONFIG_S3C_DEV_HSMMC3 s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; + s3c_hsmmc3_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; #endif } @@ -300,11 +357,17 @@ static inline void s5pv210_default_sdhci3(void) { } #ifdef CONFIG_EXYNOS4_SETUP_SDHCI extern char *exynos4_hsmmc_clksrcs[4]; +extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + static inline void exynos4_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } @@ -313,6 +376,7 @@ static inline void exynos4_default_sdhci1(void) #ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } @@ -321,6 +385,7 @@ static inline void exynos4_default_sdhci2(void) #ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; + s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } @@ -329,6 +394,7 @@ static inline void exynos4_default_sdhci3(void) #ifdef CONFIG_S3C_DEV_HSMMC3 s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; + s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } @@ -340,4 +406,59 @@ static inline void exynos4_default_sdhci3(void) { } #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ +extern void mmc_force_presence_change(struct platform_device *pdev); +extern void mmc_force_presence_change_onoff(struct platform_device *pdev, int val); + +/* EXYNOS5 SDHCI setup */ +#ifdef CONFIG_EXYNOS4_SETUP_SDHCI +extern char *exynos4_hsmmc_clksrcs[4]; + +extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + +static inline void exynos5_default_sdhci0(void) +{ +#ifdef CONFIG_S3C_DEV_HSMMC + s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs; + s3c_hsmmc0_def_platdata.cfg_gpio = exynos5_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; +#endif +} + +static inline void exynos5_default_sdhci1(void) +{ +#ifdef CONFIG_S3C_DEV_HSMMC1 + s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs; + s3c_hsmmc1_def_platdata.cfg_gpio = exynos5_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; +#endif +} + +static inline void exynos5_default_sdhci2(void) +{ +#ifdef CONFIG_S3C_DEV_HSMMC2 + s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs; + s3c_hsmmc2_def_platdata.cfg_gpio = exynos5_setup_sdhci2_cfg_gpio; + s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; +#endif +} + +static inline void exynos5_default_sdhci3(void) +{ +#ifdef CONFIG_S3C_DEV_HSMMC3 + s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs; + s3c_hsmmc3_def_platdata.cfg_gpio = exynos5_setup_sdhci3_cfg_gpio; + s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; +#endif +} + +#else +static inline void exynos5_default_sdhci0(void) { } +static inline void exynos5_default_sdhci1(void) { } +static inline void exynos5_default_sdhci2(void) { } +static inline void exynos5_default_sdhci3(void) { } + +#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ #endif /* __PLAT_S3C_SDHCI_H */ diff --git a/arch/arm/plat-samsung/include/plat/sysmmu.h b/arch/arm/plat-samsung/include/plat/sysmmu.h index 5fe8ee0..bbe2091 100644 --- a/arch/arm/plat-samsung/include/plat/sysmmu.h +++ b/arch/arm/plat-samsung/include/plat/sysmmu.h @@ -1,19 +1,22 @@ -/* linux/arch/arm/plat-samsung/include/plat/sysmmu.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. +/* + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Samsung System MMU driver for S5P platform + * Samsung System MMU driver for Exynos platforms * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#ifndef __PLAT_SAMSUNG_SYSMMU_H -#define __PLAT_SAMSUNG_SYSMMU_H __FILE__ +#ifndef __ASM__PLAT_SYSMMU_H +#define __ASM__PLAT_SYSMMU_H __FILE__ + +#include <linux/list.h> +#include <linux/atomic.h> +#include <linux/spinlock.h> -enum S5P_SYSMMU_INTERRUPT_TYPE { +enum exynos_sysmmu_inttype { SYSMMU_PAGEFAULT, SYSMMU_AR_MULTIHIT, SYSMMU_AW_MULTIHIT, @@ -22,74 +25,83 @@ enum S5P_SYSMMU_INTERRUPT_TYPE { SYSMMU_AR_ACCESS, SYSMMU_AW_SECURITY, SYSMMU_AW_PROTECTION, /* 7 */ + SYSMMU_FAULT_UNKNOWN, SYSMMU_FAULTS_NUM }; -#ifdef CONFIG_S5P_SYSTEM_MMU - -#include <mach/sysmmu.h> +/* + * @itype: type of fault. + * @pgtable_base: the physical address of page table base. This is 0 if @itype + * is SYSMMU_BUSERROR. + * @fault_addr: the device (virtual) address that the System MMU tried to + * translated. This is 0 if @itype is SYSMMU_BUSERROR. + */ +typedef int (*sysmmu_fault_handler_t)(enum exynos_sysmmu_inttype itype, + unsigned long pgtable_base, unsigned long fault_addr); +#ifdef CONFIG_EXYNOS_IOMMU /** - * s5p_sysmmu_enable() - enable system mmu of ip - * @ips: The ip connected system mmu. - * #pgd: Base physical address of the 1st level page table + * exynos_sysmmu_enable() - enable system mmu + * @owner: The device whose System MMU is about to be enabled. + * @pgd: Base physical address of the 1st level page table * * This function enable system mmu to transfer address - * from virtual address to physical address + * from virtual address to physical address. + * Return non-zero if it fails to enable System MMU. */ -void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd); +int exynos_sysmmu_enable(struct device *owner, unsigned long pgd); /** - * s5p_sysmmu_disable() - disable sysmmu mmu of ip - * @ips: The ip connected system mmu. + * exynos_sysmmu_disable() - disable sysmmu mmu of ip + * @owner: The device whose System MMU is about to be disabled. * * This function disable system mmu to transfer address * from virtual address to physical address */ -void s5p_sysmmu_disable(sysmmu_ips ips); +bool exynos_sysmmu_disable(struct device *owner); /** - * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table - * @ips: The ip connected system mmu. - * @pgd: The page table base address. - * - * This function set page table base address - * When system mmu transfer address from virtaul address to physical address, - * system mmu refer address information from page table - */ -void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd); - -/** - * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu - * @ips: The ip connected system mmu. + * exynos_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu + * @owner: The device whose System MMU. * * This function flush all TLB entry in system mmu */ -void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips); +void exynos_sysmmu_tlb_invalidate(struct device *owner); -/** s5p_sysmmu_set_fault_handler() - Fault handler for System MMUs - * @itype: type of fault. - * @pgtable_base: the physical address of page table base. This is 0 if @ips is - * SYSMMU_BUSERROR. - * @fault_addr: the device (virtual) address that the System MMU tried to - * translated. This is 0 if @ips is SYSMMU_BUSERROR. +/** exynos_sysmmu_set_fault_handler() - Fault handler for System MMUs * Called when interrupt occurred by the System MMUs * The device drivers of peripheral devices that has a System MMU can implement * a fault handler to resolve address translation fault by System MMU. * The meanings of return value and parameters are described below. - + * * return value: non-zero if the fault is correctly resolved. * zero if the fault is not handled. */ -void s5p_sysmmu_set_fault_handler(sysmmu_ips ips, - int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype, - unsigned long pgtable_base, - unsigned long fault_addr)); -#else -#define s5p_sysmmu_enable(ips, pgd) do { } while (0) -#define s5p_sysmmu_disable(ips) do { } while (0) -#define s5p_sysmmu_set_tablebase_pgd(ips, pgd) do { } while (0) -#define s5p_sysmmu_tlb_invalidate(ips) do { } while (0) -#define s5p_sysmmu_set_fault_handler(ips, handler) do { } while (0) +void exynos_sysmmu_set_fault_handler(struct device *sysmmu, + sysmmu_fault_handler_t handler); + +/** exynos_sysmmu_set_prefbuf() - Initialize prefetch buffers of System MMU v3 + * @owner: The device which need to set the prefetch buffers + * @base0: The start virtual address of the area of the @owner device that the + * first prefetch buffer loads translation descriptors + * @size0: The last virtual address of the area of the @owner device that the + * first prefetch buffer loads translation descriptors. + * @base1: The start virtual address of the area of the @owner device that the + * second prefetch buffer loads translation descriptors. This will be + * ignored if @size1 is 0 and this function assigns the 2 prefetch + * buffers with each half of the area specified by @base0 and @size0 + * @size1: The last virtual address of the area of the @owner device that the + * prefetch buffer loads translation descriptors. This can be 0. See + * the description of @base1 for more information with @size1 = 0 + */ +void exynos_sysmmu_set_prefbuf(struct device *owner, + unsigned long base0, unsigned long size0, + unsigned long base1, unsigned long size1); +#else /* CONFIG_EXYNOS_IOMMU */ +#define exynos_sysmmu_enable(owner, pgd) do { } while (0) +#define exynos_sysmmu_disable(owner) do { } while (0) +#define exynos_sysmmu_tlb_invalidate(owner) do { } while (0) +#define exynos_sysmmu_set_fault_handler(sysmmu, handler) do { } while (0) +#define exynos_sysmmu_set_prefbuf(owner, b0, s0, b1, s1) do { } while (0) #endif #endif /* __ASM_PLAT_SYSMMU_H */ diff --git a/arch/arm/plat-samsung/include/plat/ts.h b/arch/arm/plat-samsung/include/plat/ts.h index 26fdb22..3fb52b9 100644 --- a/arch/arm/plat-samsung/include/plat/ts.h +++ b/arch/arm/plat-samsung/include/plat/ts.h @@ -14,10 +14,16 @@ struct s3c2410_ts_mach_info { int delay; int presc; int oversampling_shift; + + int cal_x_max; + int cal_y_max; + int cal_param[7]; + void (*cfg_gpio)(struct platform_device *dev); }; extern void s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *); +extern void s3c24xx_ts1_set_platdata(struct s3c2410_ts_mach_info *); /* defined by architecture to configure gpio */ extern void s3c24xx_ts_cfg_gpio(struct platform_device *dev); diff --git a/arch/arm/plat-samsung/include/plat/tv-core.h b/arch/arm/plat-samsung/include/plat/tv-core.h index 3bc34f3..d647eec 100644 --- a/arch/arm/plat-samsung/include/plat/tv-core.h +++ b/arch/arm/plat-samsung/include/plat/tv-core.h @@ -34,11 +34,4 @@ static inline void s5p_mixer_setname(char *name) #endif } -static inline void s5p_sdo_setname(char *name) -{ -#ifdef CONFIG_S5P_DEV_TV - s5p_device_sdo.name = name; -#endif -} - #endif /* __SAMSUNG_PLAT_TV_H */ diff --git a/arch/arm/plat-samsung/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h index a22a4f2..9b90b08 100644 --- a/arch/arm/plat-samsung/include/plat/udc-hs.h +++ b/arch/arm/plat-samsung/include/plat/udc-hs.h @@ -27,3 +27,14 @@ struct s3c_hsotg_plat { enum s3c_hsotg_dmamode dma; unsigned int is_osc : 1; }; + +typedef enum usb_cable_status { + USB_CABLE_DETACHED = 0, + USB_CABLE_ATTACHED, + USB_OTGHOST_DETACHED, + USB_OTGHOST_ATTACHED, + USB_POWERED_HOST_DETACHED, + USB_POWERED_HOST_ATTACHED, + USB_CABLE_DETACHED_WITHOUT_NOTI, +} usb_cable_status; + diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h index 11b19ea..4dc5adf 100644 --- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h +++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h @@ -14,7 +14,9 @@ #include <plat/regs-watchdog.h> #include <mach/map.h> +#include <linux/kernel.h> #include <linux/clk.h> +#include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> @@ -24,7 +26,7 @@ static inline void arch_wdt_reset(void) __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ - if (!IS_ERR(s3c2410_wdtclk)) + if (s3c2410_wdtclk) clk_enable(s3c2410_wdtclk); /* put initial values into count and data */ |