diff options
Diffstat (limited to 'arch/blackfin/mach-bf538')
| -rw-r--r-- | arch/blackfin/mach-bf538/boards/ezkit.c | 46 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf538/ext-gpio.c | 37 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf538/include/mach/anomaly.h | 38 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf538/include/mach/gpio.h | 3 |
4 files changed, 83 insertions, 41 deletions
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c index e61424e..8356eb5 100644 --- a/arch/blackfin/mach-bf538/boards/ezkit.c +++ b/arch/blackfin/mach-bf538/boards/ezkit.c @@ -49,8 +49,13 @@ static struct resource bfin_uart0_resources[] = { .flags = IORESOURCE_MEM, }, { + .start = IRQ_UART0_TX, + .end = IRQ_UART0_TX, + .flags = IORESOURCE_IRQ, + }, + { .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, + .end = IRQ_UART0_RX, .flags = IORESOURCE_IRQ, }, { @@ -104,8 +109,13 @@ static struct resource bfin_uart1_resources[] = { .flags = IORESOURCE_MEM, }, { + .start = IRQ_UART1_TX, + .end = IRQ_UART1_TX, + .flags = IORESOURCE_IRQ, + }, + { .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, + .end = IRQ_UART1_RX, .flags = IORESOURCE_IRQ, }, { @@ -147,8 +157,13 @@ static struct resource bfin_uart2_resources[] = { .flags = IORESOURCE_MEM, }, { + .start = IRQ_UART2_TX, + .end = IRQ_UART2_TX, + .flags = IORESOURCE_IRQ, + }, + { .start = IRQ_UART2_RX, - .end = IRQ_UART2_RX+1, + .end = IRQ_UART2_RX, .flags = IORESOURCE_IRQ, }, { @@ -502,7 +517,6 @@ static struct flash_platform_data bfin_spi_flash_data = { static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif @@ -523,13 +537,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = { }; #endif -#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) -static struct bfin5xx_spi_chip spi_ad7879_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; -#endif - #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) #include <asm/bfin-lq035q1.h> @@ -559,20 +566,6 @@ static struct platform_device bfin_lq035q1_device = { }; #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) -static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bf538_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -595,7 +588,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spi_ad7879_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif @@ -605,7 +597,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, - .controller_data = &lq035q1_spi_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif @@ -615,7 +606,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif }; diff --git a/arch/blackfin/mach-bf538/ext-gpio.c b/arch/blackfin/mach-bf538/ext-gpio.c index 180b125..471a9b1 100644 --- a/arch/blackfin/mach-bf538/ext-gpio.c +++ b/arch/blackfin/mach-bf538/ext-gpio.c @@ -1,7 +1,7 @@ /* * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs * - * Copyright 2009 Analog Devices Inc. + * Copyright 2009-2011 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -121,3 +121,38 @@ static int __init bf538_extgpio_setup(void) gpiochip_add(&bf538_porte_chip); } arch_initcall(bf538_extgpio_setup); + +#ifdef CONFIG_PM +static struct { + u16 data, dir, inen; +} gpio_bank_saved[3]; + +static void __iomem * const port_bases[3] = { + (void *)PORTCIO, + (void *)PORTDIO, + (void *)PORTEIO, +}; + +void bfin_special_gpio_pm_hibernate_suspend(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(port_bases); ++i) { + gpio_bank_saved[i].data = read_PORTIO(port_bases[i]); + gpio_bank_saved[i].inen = read_PORTIO_INEN(port_bases[i]); + gpio_bank_saved[i].dir = read_PORTIO_DIR(port_bases[i]); + } +} + +void bfin_special_gpio_pm_hibernate_restore(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(port_bases); ++i) { + write_PORTIO_INEN(port_bases[i], gpio_bank_saved[i].inen); + write_PORTIO_SET(port_bases[i], + gpio_bank_saved[i].data & gpio_bank_saved[i].dir); + write_PORTIO_DIR(port_bases[i], gpio_bank_saved[i].dir); + } +} +#endif diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h index 55e7d07..b6ca997 100644 --- a/arch/blackfin/mach-bf538/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h @@ -11,8 +11,8 @@ */ /* This file should be up to date with: - * - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List - * - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List + * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List + * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -56,25 +56,21 @@ #define ANOMALY_05000229 (1) /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ #define ANOMALY_05000233 (1) -/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ -#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Maximum External Clock Speed for Timers */ #define ANOMALY_05000253 (1) -/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ -#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ #define ANOMALY_05000270 (__SILICON_REVISION__ < 4) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) +#define ANOMALY_05000272 (ANOMALY_BF538) /* Writes to Synchronous SDRAM Memory May Be Lost */ #define ANOMALY_05000273 (__SILICON_REVISION__ < 4) /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) @@ -102,8 +98,10 @@ #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) +/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */ +#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */ /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ -#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) +#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */ /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (__SILICON_REVISION__ < 5) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ @@ -134,16 +132,32 @@ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ #define ANOMALY_05000462 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ +#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) +/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ +#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h index 8a5beee..3561c7d 100644 --- a/arch/blackfin/mach-bf538/include/mach/gpio.h +++ b/arch/blackfin/mach-bf538/include/mach/gpio.h @@ -8,7 +8,10 @@ #define _MACH_GPIO_H_ #define MAX_BLACKFIN_GPIOS 16 +#ifdef CONFIG_GPIOLIB +/* We only use the special logic with GPIOLIB devices */ #define BFIN_SPECIAL_GPIO_BANKS 3 +#endif #define GPIO_PF0 0 /* PF */ #define GPIO_PF1 1 |