diff options
Diffstat (limited to 'arch/powerpc/boot')
65 files changed, 5386 insertions, 1431 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index 1cee2f9..4721baf 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -63,10 +63,10 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \ cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \ cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \ - fixed-head.S ep88xc.c ep405.c \ + fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \ cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ - virtex405-head.S + virtex405-head.S redboot-83xx.c cuboot-sam440ep.c src-boot := $(src-wlib) $(src-plat) empty.c src-boot := $(addprefix $(obj)/, $(src-boot)) @@ -213,6 +213,7 @@ image-$(CONFIG_WALNUT) += treeImage.walnut # Board ports in arch/powerpc/platform/44x/Kconfig image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo +image-$(CONFIG_SAM440EP) += cuImage.sam440ep image-$(CONFIG_SEQUOIA) += cuImage.sequoia image-$(CONFIG_RAINIER) += cuImage.rainier image-$(CONFIG_TAISHAN) += cuImage.taishan @@ -242,6 +243,7 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.mpc8349emitx \ cuImage.mpc8349emitxgp image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds +image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot # Board ports in arch/powerpc/platform/85xx/Kconfig image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads @@ -254,6 +256,7 @@ image-$(CONFIG_MPC85xx_DS) += cuImage.mpc8544ds \ cuImage.mpc8572ds image-$(CONFIG_TQM8540) += cuImage.tqm8540 image-$(CONFIG_TQM8541) += cuImage.tqm8541 +image-$(CONFIG_TQM8548) += cuImage.tqm8548 image-$(CONFIG_TQM8555) += cuImage.tqm8555 image-$(CONFIG_TQM8560) += cuImage.tqm8560 image-$(CONFIG_SBC8548) += cuImage.sbc8548 @@ -263,6 +266,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi8560 # Board ports in arch/powerpc/platform/embedded6xx/Kconfig image-$(CONFIG_STORCENTER) += cuImage.storcenter image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2 +image-$(CONFIG_PPC_C2K) += cuImage.c2k # For 32-bit powermacs, build the COFF and miboot images # as well as the ELF images. diff --git a/arch/powerpc/boot/cuboot-c2k.c b/arch/powerpc/boot/cuboot-c2k.c new file mode 100644 index 0000000..e435949 --- /dev/null +++ b/arch/powerpc/boot/cuboot-c2k.c @@ -0,0 +1,190 @@ +/* + * GEFanuc C2K platform code. + * + * Author: Remi Machet <rmachet@slac.stanford.edu> + * + * Originated from prpmc2800.c + * + * 2008 (c) Stanford University + * 2007 (c) MontaVista, Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "types.h" +#include "stdio.h" +#include "io.h" +#include "ops.h" +#include "elf.h" +#include "gunzip_util.h" +#include "mv64x60.h" +#include "cuboot.h" +#include "ppcboot.h" + +static u8 *bridge_base; + +static void c2k_bridge_setup(u32 mem_size) +{ + u32 i, v[30], enables, acc_bits; + u32 pci_base_hi, pci_base_lo, size, buf[2]; + unsigned long cpu_base; + int rc; + void *devp, *mv64x60_devp; + u8 *bridge_pbase, is_coherent; + struct mv64x60_cpu2pci_win *tbl; + int bus; + + bridge_pbase = mv64x60_get_bridge_pbase(); + is_coherent = mv64x60_is_coherent(); + + if (is_coherent) + acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB + | MV64x60_PCI_ACC_CNTL_SWAP_NONE + | MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES + | MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES; + else + acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE + | MV64x60_PCI_ACC_CNTL_SWAP_NONE + | MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES + | MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES; + + mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent); + mv64x60_devp = find_node_by_compatible(NULL, "marvell,mv64360"); + if (mv64x60_devp == NULL) + fatal("Error: Missing marvell,mv64360 device tree node\n\r"); + + enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)); + enables |= 0x007ffe00; /* Disable all cpu->pci windows */ + out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); + + /* Get the cpu -> pci i/o & mem mappings from the device tree */ + devp = NULL; + for (bus = 0; ; bus++) { + char name[] = "pci "; + + name[strlen(name)-1] = bus+'0'; + + devp = find_node_by_alias(name); + if (devp == NULL) + break; + + if (bus >= 2) + fatal("Error: Only 2 PCI controllers are supported at" \ + " this time.\n"); + + mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0, + mem_size, acc_bits); + + rc = getprop(devp, "ranges", v, sizeof(v)); + if (rc == 0) + fatal("Error: Can't find marvell,mv64360-pci ranges" + " property\n\r"); + + /* Get the cpu -> pci i/o & mem mappings from the device tree */ + + for (i = 0; i < rc; i += 6) { + switch (v[i] & 0xff000000) { + case 0x01000000: /* PCI I/O Space */ + tbl = mv64x60_cpu2pci_io; + break; + case 0x02000000: /* PCI MEM Space */ + tbl = mv64x60_cpu2pci_mem; + break; + default: + continue; + } + + pci_base_hi = v[i+1]; + pci_base_lo = v[i+2]; + cpu_base = v[i+3]; + size = v[i+5]; + + buf[0] = cpu_base; + buf[1] = size; + + if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base)) + fatal("Error: Can't translate PCI address " \ + "0x%x\n\r", (u32)cpu_base); + + mv64x60_config_cpu2pci_window(bridge_base, bus, + pci_base_hi, pci_base_lo, cpu_base, size, tbl); + } + + enables &= ~(3<<(9+bus*5)); /* Enable cpu->pci<bus> i/o, + cpu->pci<bus> mem0 */ + out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), + enables); + }; +} + +static void c2k_fixups(void) +{ + u32 mem_size; + + mem_size = mv64x60_get_mem_size(bridge_base); + c2k_bridge_setup(mem_size); /* Do necessary bridge setup */ +} + +#define MV64x60_MPP_CNTL_0 0xf000 +#define MV64x60_MPP_CNTL_2 0xf008 +#define MV64x60_GPP_IO_CNTL 0xf100 +#define MV64x60_GPP_LEVEL_CNTL 0xf110 +#define MV64x60_GPP_VALUE_SET 0xf118 + +static void c2k_reset(void) +{ + u32 temp; + + udelay(5000000); + + if (bridge_base != 0) { + temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0)); + temp &= 0xFFFF0FFF; + out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL)); + temp |= 0x00000004; + out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL)); + temp |= 0x00000004; + out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2)); + temp &= 0xFFFF0FFF; + out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL)); + temp |= 0x00080000; + out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL)); + temp |= 0x00080000; + out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp); + + out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET), + 0x00080004); + } + + for (;;); +} + +static bd_t bd; + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + CUBOOT_INIT(); + + fdt_init(_dtb_start); + + bridge_base = mv64x60_get_bridge_base(); + + platform_ops.fixups = c2k_fixups; + platform_ops.exit = c2k_reset; + + if (serial_console_init() < 0) + exit(); +} diff --git a/arch/powerpc/boot/cuboot-sam440ep.c b/arch/powerpc/boot/cuboot-sam440ep.c new file mode 100644 index 0000000..ec10a47 --- /dev/null +++ b/arch/powerpc/boot/cuboot-sam440ep.c @@ -0,0 +1,49 @@ +/* + * Old U-boot compatibility for Sam440ep based off bamboo.c code + * original copyrights below + * + * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com> + * + * Copyright 2007 IBM Corporation + * + * Based on cuboot-ebony.c + * + * Modified from cuboot-bamboo.c for sam440ep: + * Copyright 2008 Giuseppe Coviello <gicoviello@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "stdio.h" +#include "44x.h" +#include "4xx.h" +#include "cuboot.h" + +#define TARGET_4xx +#define TARGET_44x +#include "ppcboot.h" + +static bd_t bd; + +static void sam440ep_fixups(void) +{ + unsigned long sysclk = 66666666; + + ibm440ep_fixup_clocks(sysclk, 11059200, 25000000); + ibm4xx_sdram_fixup_memsize(); + ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00); + dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr); +} + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + CUBOOT_INIT(); + platform_ops.fixups = sam440ep_fixups; + platform_ops.exit = ibm44x_dbcr_reset; + fdt_init(_dtb_start); + serial_console_init(); +} diff --git a/arch/powerpc/boot/cuboot-warp.c b/arch/powerpc/boot/cuboot-warp.c index eb108a8..2178021 100644 --- a/arch/powerpc/boot/cuboot-warp.c +++ b/arch/powerpc/boot/cuboot-warp.c @@ -10,6 +10,7 @@ #include "ops.h" #include "4xx.h" #include "cuboot.h" +#include "stdio.h" #define TARGET_4xx #define TARGET_44x @@ -17,14 +18,54 @@ static bd_t bd; -static void warp_fixups(void) +static void warp_fixup_one_nor(u32 from, u32 to) { - unsigned long sysclk = 66000000; + void *devp; + char name[50]; + u32 v[2]; + + sprintf(name, "/plb/opb/ebc/nor_flash@0,0/partition@%x", from); + + devp = finddevice(name); + if (!devp) + return; + + if (getprop(devp, "reg", v, sizeof(v)) == sizeof(v)) { + v[0] = to; + setprop(devp, "reg", v, sizeof(v)); + + printf("NOR 64M fixup %x -> %x\r\n", from, to); + } +} + - ibm440ep_fixup_clocks(sysclk, 11059200, 50000000); +static void warp_fixups(void) +{ + ibm440ep_fixup_clocks(66000000, 11059200, 50000000); ibm4xx_sdram_fixup_memsize(); ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr); + + /* Fixup for 64M flash on Rev A boards. */ + if (bd.bi_flashsize == 0x4000000) { + void *devp; + u32 v[3]; + + devp = finddevice("/plb/opb/ebc/nor_flash@0,0"); + if (!devp) + return; + + /* Fixup the size */ + if (getprop(devp, "reg", v, sizeof(v)) == sizeof(v)) { + v[2] = bd.bi_flashsize; + setprop(devp, "reg", v, sizeof(v)); + } + + /* Fixup parition offsets */ + warp_fixup_one_nor(0x300000, 0x3f00000); + warp_fixup_one_nor(0x340000, 0x3f40000); + warp_fixup_one_nor(0x380000, 0x3f80000); + } } diff --git a/arch/powerpc/boot/dts/asp834x-redboot.dts b/arch/powerpc/boot/dts/asp834x-redboot.dts new file mode 100644 index 0000000..8b1bb0e --- /dev/null +++ b/arch/powerpc/boot/dts/asp834x-redboot.dts @@ -0,0 +1,282 @@ +/* + * Analogue & Micro ASP8347 Device Tree Source + * + * Copyright 2008 Codehermit + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "Analogue & Micro ASP8347E"; + compatible = "analogue-and-micro,asp8347e"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8347@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; // 128MB at 0 + }; + + localbus@ff005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8347e-localbus", + "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xff005000 0x1000>; + interrupts = <77 0x8>; + interrupt-parent = <&ipic>; + + ranges = < + 0 0 0xf0000000 0x02000000 + >; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + bank-width = <2>; + device-width = <2>; + }; + }; + + soc8349@ff000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <0x0 0xff000000 0x00100000>; + reg = <0xff000000 0x00000200>; + bus-frequency = <0>; + + wdt@200 { + device_type = "watchdog"; + compatible = "mpc83xx_wdt"; + reg = <0x200 0x100>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <15 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + spi@7000 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x7000 0x1000>; + interrupts = <16 0x8>; + interrupt-parent = <&ipic>; + mode = "cpu"; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8347-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + + /* phy type (ULPI or SERIAL) are only types supported for MPH */ + /* port = 0 or 1 */ + usb@22000 { + compatible = "fsl-usb2-mph"; + reg = <0x22000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&ipic>; + interrupts = <39 0x8>; + phy_type = "ulpi"; + port1; + }; + /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ + usb@23000 { + compatible = "fsl-usb2-dr"; + reg = <0x23000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&ipic>; + interrupts = <38 0x8>; + dr_mode = "otg"; + phy_type = "ulpi"; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; + + phy0: ethernet-phy@0 { + interrupt-parent = <&ipic>; + interrupts = <17 0x8>; + reg = <0x1>; + device_type = "ethernet-phy"; + }; + phy1: ethernet-phy@1 { + interrupt-parent = <&ipic>; + interrupts = <18 0x8>; + reg = <0x2>; + device_type = "ethernet-phy"; + }; + }; + + enet0: ethernet@24000 { + cell-index = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 08 e5 11 32 33 ]; + interrupts = <32 0x8 33 0x8 34 0x8>; + interrupt-parent = <&ipic>; + phy-handle = <&phy0>; + linux,network-index = <0>; + }; + + enet1: ethernet@25000 { + cell-index = <1>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + local-mac-address = [ 00 08 e5 11 32 34 ]; + interrupts = <35 0x8 36 0x8 37 0x8>; + interrupt-parent = <&ipic>; + phy-handle = <&phy1>; + linux,network-index = <1>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <400000000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <400000000>; + interrupts = <10 0x8>; + interrupt-parent = <&ipic>; + }; + + /* May need to remove if on a part without crypto engine */ + crypto@30000 { + device_type = "crypto"; + model = "SEC2"; + compatible = "talitos"; + reg = <0x30000 0x10000>; + interrupts = <11 0x8>; + interrupt-parent = <&ipic>; + num-channels = <4>; + channel-fifo-len = <24>; + exec-units-mask = <0x0000007e>; + /* desc mask is for rev2.0, + * we need runtime fixup for >2.0 */ + descriptor-types-mask = <0x01010ebf>; + }; + + /* IPIC + * interrupts cell = <intr #, sense> + * sense values match linux IORESOURCE_IRQ_* defines: + * sense == 8: Level, low assertion + * sense == 2: Edge, high-to-low change + */ + ipic: pic@700 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + }; + + chosen { + bootargs = "console=ttyS0,38400 root=/dev/mtdblock3 rootfstype=jffs2"; + linux,stdout-path = &serial0; + }; + +}; diff --git a/arch/powerpc/boot/dts/bamboo.dts b/arch/powerpc/boot/dts/bamboo.dts index ba2521b..6ce0cc2 100644 --- a/arch/powerpc/boot/dts/bamboo.dts +++ b/arch/powerpc/boot/dts/bamboo.dts @@ -11,12 +11,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,bamboo"; compatible = "amcc,bamboo"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -34,13 +36,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440EP"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -48,14 +50,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -65,22 +67,22 @@ compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440ep"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-440ep"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -92,29 +94,29 @@ SDRAM0: sdram { compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; DMA0: dma { compatible = "ibm,dma-440ep", "ibm,dma-440gp"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 - /*RXEOB*/ 1 &UIC0 b 4 - /*SERR*/ 2 &UIC1 0 4 - /*TXDE*/ 3 &UIC1 1 4 - /*RXDE*/ 4 &UIC1 2 4>; + interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 + /*RXEOB*/ 0x1 &UIC0 0xb 0x4 + /*SERR*/ 0x2 &UIC1 0x0 0x4 + /*TXDE*/ 0x3 &UIC1 0x1 0x4 + /*RXDE*/ 0x4 &UIC1 0x2 0x4>; }; POB0: opb { @@ -124,101 +126,101 @@ /* Bamboo is oddball in the 44x world and doesn't use the ERPN * bits. */ - ranges = <00000000 0 00000000 80000000 - 80000000 0 80000000 80000000>; + ranges = <0x00000000 0x00000000 0x00000000 0x80000000 + 0x80000000 0x00000000 0x80000000 0x80000000>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; }; UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600300 8>; - virtual-reg = <ef600300>; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <115200>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600400 8>; - virtual-reg = <ef600400>; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600500 8>; - virtual-reg = <ef600500>; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600600 8>; - virtual-reg = <ef600600>; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <4 4>; + interrupts = <0x4 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; - reg = <ef600700 14>; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; - reg = <ef600800 14>; + reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; - reg = <ef600d00 c>; + reg = <0xef600d00 0x0000000c>; }; EMAC0: ethernet@ef600e00 { device_type = "network"; compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = <ef600e00 70>; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0 1>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <0>; }; @@ -227,26 +229,26 @@ device_type = "network"; compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1e 4 1f 4>; - reg = <ef600f00 70>; + interrupts = <0x1e 0x4 0x1f 0x4>; + reg = <0xef600f00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <2 3>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <1>; }; usb@ef601000 { compatible = "ohci-be"; - reg = <ef601000 80>; - interrupts = <8 1 9 1>; + reg = <0xef601000 0x00000080>; + interrupts = <0x8 0x1 0x9 0x1>; interrupt-parent = < &UIC1 >; }; }; @@ -258,35 +260,35 @@ #address-cells = <3>; compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; primary; - reg = <0 eec00000 8 /* Config space access */ - 0 eed00000 4 /* IACK */ - 0 eed00000 4 /* Special cycle */ - 0 ef400000 40>; /* Internal registers */ + reg = <0x00000000 0xeec00000 0x00000008 /* Config space access */ + 0x00000000 0xeed00000 0x00000004 /* IACK */ + 0x00000000 0xeed00000 0x00000004 /* Special cycle */ + 0x00000000 0xef400000 0x00000040>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second * IO range but we don't use it for now */ - ranges = <02000000 0 a0000000 0 a0000000 0 20000000 - 01000000 0 00000000 0 e8000000 0 00010000>; + ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x20000000 + 0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* Bamboo has all 4 IRQ pins tied together per slot */ - interrupt-map-mask = <f800 0 0 0>; + interrupt-map-mask = <0xf800 0x0 0x0 0x0>; interrupt-map = < /* IDSEL 1 */ - 0800 0 0 0 &UIC0 1c 8 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 /* IDSEL 2 */ - 1000 0 0 0 &UIC0 1b 8 + 0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8 /* IDSEL 3 */ - 1800 0 0 0 &UIC0 1a 8 + 0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8 /* IDSEL 4 */ - 2000 0 0 0 &UIC0 19 8 + 0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8 >; }; }; diff --git a/arch/powerpc/boot/dts/c2k.dts b/arch/powerpc/boot/dts/c2k.dts new file mode 100644 index 0000000..f5d625f --- /dev/null +++ b/arch/powerpc/boot/dts/c2k.dts @@ -0,0 +1,371 @@ +/* Device Tree Source for GEFanuc C2K + * + * Author: Remi Machet <rmachet@slac.stanford.edu> + * + * Originated from prpmc2800.dts + * + * 2008 (c) Stanford University + * 2007 (c) MontaVista, Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "C2K"; + compatible = "GEFanuc,C2K"; + coherency-off; + + aliases { + pci0 = &PCI0; + pci1 = &PCI1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "PowerPC,7447"; + reg = <0>; + clock-frequency = <996000000>; /* 996 MHz */ + bus-frequency = <166666667>; /* 166.6666 MHz */ + timebase-frequency = <41666667>; /* 166.6666/4 MHz */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1GB */ + }; + + system-controller@d8000000 { /* Marvell Discovery */ + #address-cells = <1>; + #size-cells = <1>; + model = "mv64460"; + compatible = "marvell,mv64360"; + clock-frequency = <166666667>; /* 166.66... MHz */ + reg = <0xd8000000 0x00010000>; + virtual-reg = <0xd8000000>; + ranges = <0xd4000000 0xd4000000 0x01000000 /* PCI 0 I/O Space */ + 0x80000000 0x80000000 0x08000000 /* PCI 0 MEM Space */ + 0xd0000000 0xd0000000 0x01000000 /* PCI 1 I/O Space */ + 0xa0000000 0xa0000000 0x08000000 /* PCI 1 MEM Space */ + 0xd8100000 0xd8100000 0x00010000 /* FPGA */ + 0xd8110000 0xd8110000 0x00010000 /* FPGA USARTs */ + 0xf8000000 0xf8000000 0x08000000 /* User FLASH */ + 0x00000000 0xd8000000 0x00010000 /* Bridge's regs */ + 0xd8140000 0xd8140000 0x00040000>; /* Integrated SRAM */ + + mdio@2000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,mv64360-mdio"; + reg = <0x2000 4>; + PHY0: ethernet-phy@0 { + device_type = "ethernet-phy"; + interrupts = <76>; /* GPP 12 */ + interrupt-parent = <&PIC>; + reg = <0>; + }; + PHY1: ethernet-phy@1 { + device_type = "ethernet-phy"; + interrupts = <76>; /* GPP 12 */ + interrupt-parent = <&PIC>; + reg = <1>; + }; + PHY2: ethernet-phy@2 { + device_type = "ethernet-phy"; + interrupts = <76>; /* GPP 12 */ + interrupt-parent = <&PIC>; + reg = <2>; + }; + }; + + ethernet-group@2000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,mv64360-eth-group"; + reg = <0x2000 0x2000>; + ethernet@0 { + device_type = "network"; + compatible = "marvell,mv64360-eth"; + reg = <0>; + interrupts = <32>; + interrupt-parent = <&PIC>; + phy = <&PHY0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@1 { + device_type = "network"; + compatible = "marvell,mv64360-eth"; + reg = <1>; + interrupts = <33>; + interrupt-parent = <&PIC>; + phy = <&PHY1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@2 { + device_type = "network"; + compatible = "marvell,mv64360-eth"; + reg = <2>; + interrupts = <34>; + interrupt-parent = <&PIC>; + phy = <&PHY2>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + SDMA0: sdma@4000 { + compatible = "marvell,mv64360-sdma"; + reg = <0x4000 0xc18>; + virtual-reg = <0xd8004000>; + interrupt-base = <0>; + interrupts = <36>; + interrupt-parent = <&PIC>; + }; + + SDMA1: sdma@6000 { + compatible = "marvell,mv64360-sdma"; + reg = <0x6000 0xc18>; + virtual-reg = <0xd8006000>; + interrupt-base = <0>; + interrupts = <38>; + interrupt-parent = <&PIC>; + }; + + BRG0: brg@b200 { + compatible = "marvell,mv64360-brg"; + reg = <0xb200 0x8>; + clock-src = <8>; + clock-frequency = <133333333>; + current-speed = <115200>; + }; + + BRG1: brg@b208 { + compatible = "marvell,mv64360-brg"; + reg = <0xb208 0x8>; + clock-src = <8>; + clock-frequency = <133333333>; + current-speed = <115200>; + }; + + CUNIT: cunit@f200 { + reg = <0xf200 0x200>; + }; + + MPSCROUTING: mpscrouting@b400 { + reg = <0xb400 0xc>; + }; + + MPSCINTR: mpscintr@b800 { + reg = <0xb800 0x100>; + virtual-reg = <0xd800b800>; + }; + + MPSC0: mpsc@8000 { + device_type = "serial"; + compatible = "marvell,mv64360-mpsc"; + reg = <0x8000 0x38>; + virtual-reg = <0xd8008000>; + sdma = <&SDMA0>; + brg = <&BRG0>; + cunit = <&CUNIT>; + mpscrouting = <&MPSCROUTING>; + mpscintr = <&MPSCINTR>; + cell-index = <0>; + interrupts = <40>; + interrupt-parent = <&PIC>; + }; + + MPSC1: mpsc@9000 { + device_type = "serial"; + compatible = "marvell,mv64360-mpsc"; + reg = <0x9000 0x38>; + virtual-reg = <0xd8009000>; + sdma = <&SDMA1>; + brg = <&BRG1>; + cunit = <&CUNIT>; + mpscrouting = <&MPSCROUTING>; + mpscintr = <&MPSCINTR>; + cell-index = <1>; + interrupts = <42>; + interrupt-parent = <&PIC>; + }; + + wdt@b410 { /* watchdog timer */ + compatible = "marvell,mv64360-wdt"; + reg = <0xb410 0x8>; + }; + + i2c@c000 { + compatible = "marvell,mv64360-i2c"; + reg = <0xc000 0x20>; + virtual-reg = <0xd800c000>; + interrupts = <37>; + interrupt-parent = <&PIC>; + }; + + PIC: pic { + #interrupt-cells = <1>; + #address-cells = <0>; + compatible = "marvell,mv64360-pic"; + reg = <0x0000 0x88>; + interrupt-controller; + }; + + mpp@f000 { + compatible = "marvell,mv64360-mpp"; + reg = <0xf000 0x10>; + }; + + gpp@f100 { + compatible = "marvell,mv64360-gpp"; + reg = <0xf100 0x20>; + }; + + PCI0: pci@80000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "marvell,mv64360-pci"; + reg = <0x0cf8 0x8>; + ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000 + 0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>; + bus-range = <0 255>; + clock-frequency = <66000000>; + interrupt-pci-iack = <0x0c34>; + interrupt-parent = <&PIC>; + interrupt-map-mask = <0x0000 0x0 0x0 0x7>; + interrupt-map = < + /* Only one interrupt line for PMC0 slot (INTA) */ + 0x0000 0 0 1 &PIC 88 + >; + }; + + + PCI1: pci@a0000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "marvell,mv64360-pci"; + reg = <0x0c78 0x8>; + ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000 + 0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>; + bus-range = <0 255>; + clock-frequency = <66000000>; + interrupt-pci-iack = <0x0cb4>; + interrupt-parent = <&PIC>; + interrupt-map-mask = <0xf800 0x00 0x00 0x7>; + interrupt-map = < + /* IDSEL 0x01: PMC1 ? */ + 0x0800 0 0 1 &PIC 88 + /* IDSEL 0x02: cPCI bridge */ + 0x1000 0 0 1 &PIC 88 + /* IDSEL 0x03: USB controller */ + 0x1800 0 0 1 &PIC 91 + /* IDSEL 0x04: SATA controller */ + 0x2000 0 0 1 &PIC 95 + >; + }; + + cpu-error@0070 { + compatible = "marvell,mv64360-cpu-error"; + reg = <0x0070 0x10 0x0128 0x28>; + interrupts = <3>; + interrupt-parent = <&PIC>; + }; + + sram-ctrl@0380 { + compatible = "marvell,mv64360-sram-ctrl"; + reg = <0x0380 0x80>; + interrupts = <13>; + interrupt-parent = <&PIC>; + }; + + pci-error@1d40 { + compatible = "marvell,mv64360-pci-error"; + reg = <0x1d40 0x40 0x0c28 0x4>; + interrupts = <12>; + interrupt-parent = <&PIC>; + }; + + pci-error@1dc0 { + compatible = "marvell,mv64360-pci-error"; + reg = <0x1dc0 0x40 0x0ca8 0x4>; + interrupts = <16>; + interrupt-parent = <&PIC>; + }; + + mem-ctrl@1400 { + compatible = "marvell,mv64360-mem-ctrl"; + reg = <0x1400 0x60>; + interrupts = <17>; + interrupt-parent = <&PIC>; + }; + /* Devices attached to the device controller */ + devicebus@045c { + #address-cells = <2>; + #size-cells = <1>; + compatible = "marvell,mv64306-devctrl"; + reg = <0x45C 0x88>; + interrupts = <1>; + interrupt-parent = <&PIC>; + ranges = <0 0 0xd8100000 0x10000 + 2 0 0xd8110000 0x10000 + 4 0 0xf8000000 0x8000000>; + fpga@0,0 { + compatible = "sbs,fpga-c2k"; + reg = <0 0 0x10000>; + }; + fpga_usart@2,0 { + compatible = "sbs,fpga_usart-c2k"; + reg = <2 0 0x10000>; + }; + nor_flash@4,0 { + compatible = "cfi-flash"; + reg = <4 0 0x8000000>; /* 128MB */ + bank-width = <4>; + device-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "boot"; + reg = <0x00000000 0x00080000>; + }; + partition@40000 { + label = "kernel"; + reg = <0x00080000 0x00400000>; + }; + partition@440000 { + label = "initrd"; + reg = <0x00480000 0x00B80000>; + }; + partition@1000000 { + label = "rootfs"; + reg = <0x01000000 0x06800000>; + }; + partition@7800000 { + label = "recovery"; + reg = <0x07800000 0x00800000>; + read-only; + }; + }; + }; + }; + chosen { + linux,stdout-path = &MPSC0; + }; +}; diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts index 3963412..f9fe032 100644 --- a/arch/powerpc/boot/dts/canyonlands.dts +++ b/arch/powerpc/boot/dts/canyonlands.dts @@ -8,12 +8,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,canyonlands"; compatible = "amcc,canyonlands"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -29,13 +31,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,460EX"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by U-Boot */ timebase-frequency = <0>; /* Filled in by U-Boot */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -43,14 +45,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by U-Boot */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-460ex","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -60,11 +62,11 @@ compatible = "ibm,uic-460ex","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -72,11 +74,11 @@ compatible = "ibm,uic-460ex","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <a 4 b 4>; /* cascade */ + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -84,22 +86,22 @@ compatible = "ibm,uic-460ex","ibm,uic"; interrupt-controller; cell-index = <3>; - dcr-reg = <0f0 009>; + dcr-reg = <0x0f0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <10 4 11 4>; /* cascade */ + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-460ex"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-460ex"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -111,74 +113,74 @@ SDRAM0: sdram { compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; - num-rx-chans = <10>; + num-rx-chans = <16>; #address-cells = <0>; #size-cells = <0>; interrupt-parent = <&UIC2>; - interrupts = < /*TXEOB*/ 6 4 - /*RXEOB*/ 7 4 - /*SERR*/ 3 4 - /*TXDE*/ 4 4 - /*RXDE*/ 5 4>; + interrupts = < /*TXEOB*/ 0x6 0x4 + /*RXEOB*/ 0x7 0x4 + /*SERR*/ 0x3 0x4 + /*TXDE*/ 0x4 0x4 + /*RXDE*/ 0x5 0x4>; }; POB0: opb { compatible = "ibm,opb-460ex", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <b0000000 4 b0000000 50000000>; + ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; clock-frequency = <0>; /* Filled in by U-Boot */ EBC0: ebc { compatible = "ibm,ebc-460ex", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by U-Boot */ /* ranges property is supplied by U-Boot */ - interrupts = <6 4>; + interrupts = <0x6 0x4>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl512n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "kernel"; - reg = <0 1e0000>; + reg = <0x00000000 0x001e0000>; }; partition@1e0000 { label = "dtb"; - reg = <1e0000 20000>; + reg = <0x001e0000 0x00020000>; }; partition@200000 { label = "ramdisk"; - reg = <200000 1400000>; + reg = <0x00200000 0x01400000>; }; partition@1600000 { label = "jffs2"; - reg = <1600000 400000>; + reg = <0x01600000 0x00400000>; }; partition@1a00000 { label = "user"; - reg = <1a00000 2560000>; + reg = <0x01a00000 0x02560000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; }; @@ -186,103 +188,103 @@ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600300 8>; - virtual-reg = <ef600300>; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600400 8>; - virtual-reg = <ef600400>; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600500 8>; - virtual-reg = <ef600500>; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; - interrupts = <1d 4>; + interrupts = <0x1d 0x4>; }; UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600600 8>; - virtual-reg = <ef600600>; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; - interrupts = <1e 4>; + interrupts = <0x1e 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-460ex", "ibm,iic"; - reg = <ef600700 14>; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-460ex", "ibm,iic"; - reg = <ef600800 14>; + reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-460ex", "ibm,zmii"; - reg = <ef600d00 c>; + reg = <0xef600d00 0x0000000c>; }; RGMII0: emac-rgmii@ef601500 { compatible = "ibm,rgmii-460ex", "ibm,rgmii"; - reg = <ef601500 8>; + reg = <0xef601500 0x00000008>; has-mdio; }; TAH0: emac-tah@ef601350 { compatible = "ibm,tah-460ex", "ibm,tah"; - reg = <ef601350 30>; + reg = <0xef601350 0x00000030>; }; TAH1: emac-tah@ef601450 { compatible = "ibm,tah-460ex", "ibm,tah"; - reg = <ef601450 30>; + reg = <0xef601450 0x00000030>; }; EMAC0: ethernet@ef600e00 { device_type = "network"; compatible = "ibm,emac-460ex", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC2 10 4 - /*Wake*/ 1 &UIC2 14 4>; - reg = <ef600e00 70>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 + /*Wake*/ 0x1 &UIC2 0x14 0x4>; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <0>; tah-device = <&TAH0>; @@ -295,23 +297,23 @@ device_type = "network"; compatible = "ibm,emac-460ex", "ibm,emac4"; interrupt-parent = <&EMAC1>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC2 11 4 - /*Wake*/ 1 &UIC2 15 4>; - reg = <ef600f00 70>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 + /*Wake*/ 0x1 &UIC2 0x15 0x4>; + reg = <0xef600f00 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <8>; cell-index = <1>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <1>; tah-device = <&TAH1>; @@ -331,27 +333,27 @@ primary; large-inbound-windows; enable-msi-hole; - reg = <c 0ec00000 8 /* Config space access */ - 0 0 0 /* no IACK cycles */ - c 0ed00000 4 /* Special cycles */ - c 0ec80000 100 /* Internal registers */ - c 0ec80100 fc>; /* Internal messaging registers */ + reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ + 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ + 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 - 01000000 0 00000000 0000000c 08000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0 to 0x3f */ - bus-range = <0 3f>; + bus-range = <0x0 0x3f>; /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ - interrupt-map-mask = <0000 0 0 0>; - interrupt-map = < 0000 0 0 0 &UIC1 0 8 >; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; }; PCIE0: pciex@d00000000 { @@ -361,23 +363,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; primary; - port = <0>; /* port number */ - reg = <d 00000000 20000000 /* Config space access */ - c 08010000 00001000>; /* Registers */ - dcr-reg = <100 020>; - sdr-base = <300>; + port = <0x0>; /* port number */ + reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ + 0x0000000c 0x08010000 0x00001000>; /* Registers */ + dcr-reg = <0x100 0x020>; + sdr-base = <0x300>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 - 01000000 0 00000000 0000000f 80000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 40 to 0x7f */ - bus-range = <40 7f>; + bus-range = <0x40 0x7f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -387,12 +389,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 c 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 d 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 e 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; }; PCIE1: pciex@d20000000 { @@ -402,23 +404,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; primary; - port = <1>; /* port number */ - reg = <d 20000000 20000000 /* Config space access */ - c 08011000 00001000>; /* Registers */ - dcr-reg = <120 020>; - sdr-base = <340>; + port = <0x1>; /* port number */ + reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ + 0x0000000c 0x08011000 0x00001000>; /* Registers */ + dcr-reg = <0x120 0x020>; + sdr-base = <0x340>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 - 01000000 0 00000000 0000000f 80010000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 80 to 0xbf */ - bus-range = <80 bf>; + bus-range = <0x80 0xbf>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -428,12 +430,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 10 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 11 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 12 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; }; }; }; diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts index 5079dc8..ec2d142 100644 --- a/arch/powerpc/boot/dts/ebony.dts +++ b/arch/powerpc/boot/dts/ebony.dts @@ -11,12 +11,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "ibm,ebony"; compatible = "ibm,ebony"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -32,13 +34,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440GP"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; // Filled in by zImage timebase-frequency = <0>; // Filled in by zImage - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; /* 32 kB */ - d-cache-size = <8000>; /* 32 kB */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; /* 32 kB */ + d-cache-size = <32768>; /* 32 kB */ dcr-controller; dcr-access-method = "native"; }; @@ -46,14 +48,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; // Filled in by zImage + reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440gp", "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -64,17 +66,17 @@ compatible = "ibm,uic-440gp", "ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; CPC0: cpc { compatible = "ibm,cpc-440gp"; - dcr-reg = <0b0 003 0e0 010>; + dcr-reg = <0x0b0 0x003 0x0e0 0x010>; // FIXME: anything else? }; @@ -87,37 +89,37 @@ SDRAM0: memory-controller { compatible = "ibm,sdram-440gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; // FIXME: anything else? }; SRAM0: sram { compatible = "ibm,sram-440gp"; - dcr-reg = <020 8 00a 1>; + dcr-reg = <0x020 0x008 0x00a 0x001>; }; DMA0: dma { // FIXME: ??? compatible = "ibm,dma-440gp"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; num-rx-chans = <4>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 - /*RXEOB*/ 1 &UIC0 b 4 - /*SERR*/ 2 &UIC1 0 4 - /*TXDE*/ 3 &UIC1 1 4 - /*RXDE*/ 4 &UIC1 2 4>; - interrupt-map-mask = <ffffffff>; + interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 + /*RXEOB*/ 0x1 &UIC0 0xb 0x4 + /*SERR*/ 0x2 &UIC1 0x0 0x4 + /*TXDE*/ 0x3 &UIC1 0x1 0x4 + /*RXDE*/ 0x4 &UIC1 0x2 0x4>; + interrupt-map-mask = <0xffffffff>; }; POB0: opb { @@ -126,34 +128,34 @@ #size-cells = <1>; /* Wish there was a nicer way of specifying a full 32-bit range */ - ranges = <00000000 1 00000000 80000000 - 80000000 1 80000000 80000000>; - dcr-reg = <090 00b>; + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; + dcr-reg = <0x090 0x00b>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; clock-frequency = <0>; // Filled in by zImage EBC0: ebc { compatible = "ibm,ebc-440gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; // Filled in by zImage // ranges property is supplied by zImage // based on firmware's configuration of the // EBC bridge - interrupts = <5 4>; + interrupts = <0x5 0x4>; interrupt-parent = <&UIC1>; small-flash@0,80000 { compatible = "jedec-flash"; bank-width = <1>; - reg = <0 80000 80000>; + reg = <0x00000000 0x00080000 0x00080000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "OpenBIOS"; - reg = <0 80000>; + reg = <0x00000000 0x00080000>; read-only; }; }; @@ -161,101 +163,101 @@ nvram@1,0 { /* NVRAM & RTC */ compatible = "ds1743-nvram"; - #bytes = <2000>; - reg = <1 0 2000>; + #bytes = <0x2000>; + reg = <0x00000001 0x00000000 0x00002000>; }; large-flash@2,0 { compatible = "jedec-flash"; bank-width = <1>; - reg = <2 0 400000>; + reg = <0x00000002 0x00000000 0x00400000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "fs"; - reg = <0 380000>; + reg = <0x00000000 0x00380000>; }; partition@380000 { label = "firmware"; - reg = <380000 80000>; + reg = <0x00380000 0x00080000>; }; }; ir@3,0 { - reg = <3 0 10>; + reg = <0x00000003 0x00000000 0x00000010>; }; fpga@7,0 { compatible = "Ebony-FPGA"; - reg = <7 0 10>; - virtual-reg = <e8300000>; + reg = <0x00000007 0x00000000 0x00000010>; + virtual-reg = <0xe8300000>; }; }; UART0: serial@40000200 { device_type = "serial"; compatible = "ns16550"; - reg = <40000200 8>; - virtual-reg = <e0000200>; - clock-frequency = <A8C000>; - current-speed = <2580>; + reg = <0x40000200 0x00000008>; + virtual-reg = <0xe0000200>; + clock-frequency = <11059200>; + current-speed = <9600>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@40000300 { device_type = "serial"; compatible = "ns16550"; - reg = <40000300 8>; - virtual-reg = <e0000300>; - clock-frequency = <A8C000>; - current-speed = <2580>; + reg = <0x40000300 0x00000008>; + virtual-reg = <0xe0000300>; + clock-frequency = <11059200>; + current-speed = <9600>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC0: i2c@40000400 { /* FIXME */ compatible = "ibm,iic-440gp", "ibm,iic"; - reg = <40000400 14>; + reg = <0x40000400 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@40000500 { /* FIXME */ compatible = "ibm,iic-440gp", "ibm,iic"; - reg = <40000500 14>; + reg = <0x40000500 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; GPIO0: gpio@40000700 { /* FIXME */ compatible = "ibm,gpio-440gp"; - reg = <40000700 20>; + reg = <0x40000700 0x00000020>; }; ZMII0: emac-zmii@40000780 { compatible = "ibm,zmii-440gp", "ibm,zmii"; - reg = <40000780 c>; + reg = <0x40000780 0x0000000c>; }; EMAC0: ethernet@40000800 { device_type = "network"; compatible = "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = <40000800 70>; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0x40000800 0x00000070>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <0 1>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000001>; + phy-map = <0x00000001>; zmii-device = <&ZMII0>; zmii-channel = <0>; }; @@ -263,18 +265,18 @@ device_type = "network"; compatible = "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1e 4 1f 4>; - reg = <40000900 70>; + interrupts = <0x1e 0x4 0x1f 0x4>; + reg = <0x40000900 0x00000070>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <2 3>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000001>; + phy-map = <0x00000001>; zmii-device = <&ZMII0>; zmii-channel = <1>; }; @@ -282,9 +284,9 @@ GPT0: gpt@40000a00 { /* FIXME */ - reg = <40000a00 d4>; + reg = <0x40000a00 0x000000d4>; interrupt-parent = <&UIC0>; - interrupts = <12 4 13 4 14 4 15 4 16 4>; + interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>; }; }; @@ -296,35 +298,35 @@ #address-cells = <3>; compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; primary; - reg = <2 0ec00000 8 /* Config space access */ - 0 0 0 /* no IACK cycles */ - 2 0ed00000 4 /* Special cycles */ - 2 0ec80000 f0 /* Internal registers */ - 2 0ec80100 fc>; /* Internal messaging registers */ + reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x00000002 0x0ed00000 0x00000004 /* Special cycles */ + 0x00000002 0x0ec80000 0x000000f0 /* Internal registers */ + 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 00000003 80000000 0 80000000 - 01000000 0 00000000 00000002 08000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* Ebony has all 4 IRQ pins tied together per slot */ - interrupt-map-mask = <f800 0 0 0>; + interrupt-map-mask = <0xf800 0x0 0x0 0x0>; interrupt-map = < /* IDSEL 1 */ - 0800 0 0 0 &UIC0 17 8 + 0x800 0x0 0x0 0x0 &UIC0 0x17 0x8 /* IDSEL 2 */ - 1000 0 0 0 &UIC0 18 8 + 0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8 /* IDSEL 3 */ - 1800 0 0 0 &UIC0 19 8 + 0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8 /* IDSEL 4 */ - 2000 0 0 0 &UIC0 1a 8 + 0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8 >; }; }; diff --git a/arch/powerpc/boot/dts/ep405.dts b/arch/powerpc/boot/dts/ep405.dts index 9293855..53ef06c 100644 --- a/arch/powerpc/boot/dts/ep405.dts +++ b/arch/powerpc/boot/dts/ep405.dts @@ -9,12 +9,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <1>; #size-cells = <1>; model = "ep405"; compatible = "ep405"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC; @@ -29,13 +31,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,405GP"; - reg = <0>; - clock-frequency = <bebc200>; /* Filled in by zImage */ + reg = <0x00000000>; + clock-frequency = <200000000>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <4000>; - d-cache-size = <4000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <16384>; + d-cache-size = <16384>; dcr-controller; dcr-access-method = "native"; }; @@ -43,14 +45,14 @@ memory { device_type = "memory"; - reg = <0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller { compatible = "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 9>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -65,91 +67,91 @@ SDRAM0: memory-controller { compatible = "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL: mcmal { compatible = "ibm,mcmal-405gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <1>; num-rx-chans = <1>; interrupt-parent = <&UIC0>; interrupts = < - b 4 /* TXEOB */ - c 4 /* RXEOB */ - a 4 /* SERR */ - d 4 /* TXDE */ - e 4 /* RXDE */>; + 0xb 0x4 /* TXEOB */ + 0xc 0x4 /* RXEOB */ + 0xa 0x4 /* SERR */ + 0xd 0x4 /* TXDE */ + 0xe 0x4 /* RXDE */>; }; POB0: opb { compatible = "ibm,opb-405gp", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <ef600000 ef600000 a00000>; - dcr-reg = <0a0 5>; + ranges = <0xef600000 0xef600000 0x00a00000>; + dcr-reg = <0x0a0 0x005>; clock-frequency = <0>; /* Filled in by zImage */ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600300 8>; - virtual-reg = <ef600300>; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <2580>; + current-speed = <9600>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600400 8>; - virtual-reg = <ef600400>; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <2580>; + current-speed = <9600>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC: i2c@ef600500 { compatible = "ibm,iic-405gp", "ibm,iic"; - reg = <ef600500 11>; + reg = <0xef600500 0x00000011>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; GPIO: gpio@ef600700 { compatible = "ibm,gpio-405gp"; - reg = <ef600700 20>; + reg = <0xef600700 0x00000020>; }; EMAC: ethernet@ef600800 { - linux,network-index = <0>; + linux,network-index = <0x0>; device_type = "network"; compatible = "ibm,emac-405gp", "ibm,emac"; interrupt-parent = <&UIC0>; interrupts = < - f 4 /* Ethernet */ - 9 4 /* Ethernet Wake Up */>; + 0xf 0x4 /* Ethernet */ + 0x9 0x4 /* Ethernet Wake Up */>; local-mac-address = [000000000000]; /* Filled in by zImage */ - reg = <ef600800 70>; + reg = <0xef600800 0x00000070>; mal-device = <&MAL>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; }; }; EBC0: ebc { compatible = "ibm,ebc-405gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; @@ -163,13 +165,13 @@ /* NVRAM and RTC */ nvrtc@4,200000 { compatible = "ds1742"; - reg = <4 200000 0>; /* size fixed up by zImage */ + reg = <0x00000004 0x00200000 0x00000000>; /* size fixed up by zImage */ }; /* "BCSR" CPLD contains a PCI irq controller */ bcsr@4,0 { compatible = "ep405-bcsr"; - reg = <4 0 10>; + reg = <0x00000004 0x00000000 0x00000010>; interrupt-controller; /* Routing table */ irq-routing = [ 00 /* SYSERR */ @@ -198,26 +200,26 @@ #address-cells = <3>; compatible = "ibm,plb405gp-pci", "ibm,plb-pci"; primary; - reg = <eec00000 8 /* Config space access */ - eed80000 4 /* IACK */ - eed80000 4 /* Special cycle */ - ef480000 40>; /* Internal registers */ + reg = <0xeec00000 0x00000008 /* Config space access */ + 0xeed80000 0x00000004 /* IACK */ + 0xeed80000 0x00000004 /* Special cycle */ + 0xef480000 0x00000040>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second * IO range but we don't use it for now */ - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e8000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 + 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* That's all I know about IRQs on that thing ... */ - interrupt-map-mask = <f800 0 0 0>; + interrupt-map-mask = <0xf800 0x0 0x0 0x0>; interrupt-map = < /* USB */ - 7000 0 0 0 &UIC0 1e 8 /* IRQ5 */ + 0x7000 0x0 0x0 0x0 &UIC0 0x1e 0x8 /* IRQ5 */ >; }; }; diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts index 0f2fc07..463650c 100644 --- a/arch/powerpc/boot/dts/glacier.dts +++ b/arch/powerpc/boot/dts/glacier.dts @@ -8,12 +8,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,glacier"; compatible = "amcc,glacier", "amcc,canyonlands"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -31,13 +33,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,460GT"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by U-Boot */ timebase-frequency = <0>; /* Filled in by U-Boot */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -45,14 +47,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by U-Boot */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-460gt","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -62,11 +64,11 @@ compatible = "ibm,uic-460gt","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -74,11 +76,11 @@ compatible = "ibm,uic-460gt","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <a 4 b 4>; /* cascade */ + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -86,22 +88,22 @@ compatible = "ibm,uic-460gt","ibm,uic"; interrupt-controller; cell-index = <3>; - dcr-reg = <0f0 009>; + dcr-reg = <0x0f0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <10 4 11 4>; /* cascade */ + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-460gt"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-460gt"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -113,75 +115,75 @@ SDRAM0: sdram { compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; - num-rx-chans = <20>; + num-rx-chans = <32>; #address-cells = <0>; #size-cells = <0>; interrupt-parent = <&UIC2>; - interrupts = < /*TXEOB*/ 6 4 - /*RXEOB*/ 7 4 - /*SERR*/ 3 4 - /*TXDE*/ 4 4 - /*RXDE*/ 5 4>; - desc-base-addr-high = <8>; + interrupts = < /*TXEOB*/ 0x6 0x4 + /*RXEOB*/ 0x7 0x4 + /*SERR*/ 0x3 0x4 + /*TXDE*/ 0x4 0x4 + /*RXDE*/ 0x5 0x4>; + desc-base-addr-high = <0x8>; }; POB0: opb { compatible = "ibm,opb-460gt", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <b0000000 4 b0000000 50000000>; + ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; clock-frequency = <0>; /* Filled in by U-Boot */ EBC0: ebc { compatible = "ibm,ebc-460gt", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by U-Boot */ /* ranges property is supplied by U-Boot */ - interrupts = <6 4>; + interrupts = <0x6 0x4>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl512n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "kernel"; - reg = <0 1e0000>; + reg = <0x00000000 0x001e0000>; }; partition@1e0000 { label = "dtb"; - reg = <1e0000 20000>; + reg = <0x001e0000 0x00020000>; }; partition@200000 { label = "ramdisk"; - reg = <200000 1400000>; + reg = <0x00200000 0x01400000>; }; partition@1600000 { label = "jffs2"; - reg = <1600000 400000>; + reg = <0x01600000 0x00400000>; }; partition@1a00000 { label = "user"; - reg = <1a00000 2560000>; + reg = <0x01a00000 0x02560000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; }; @@ -189,109 +191,109 @@ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600300 8>; - virtual-reg = <ef600300>; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600400 8>; - virtual-reg = <ef600400>; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600500 8>; - virtual-reg = <ef600500>; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; - interrupts = <1d 4>; + interrupts = <0x1d 0x4>; }; UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600600 8>; - virtual-reg = <ef600600>; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; - interrupts = <1e 4>; + interrupts = <0x1e 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-460gt", "ibm,iic"; - reg = <ef600700 14>; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-460gt", "ibm,iic"; - reg = <ef600800 14>; + reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-460gt", "ibm,zmii"; - reg = <ef600d00 c>; + reg = <0xef600d00 0x0000000c>; }; RGMII0: emac-rgmii@ef601500 { compatible = "ibm,rgmii-460gt", "ibm,rgmii"; - reg = <ef601500 8>; + reg = <0xef601500 0x00000008>; has-mdio; }; RGMII1: emac-rgmii@ef601600 { compatible = "ibm,rgmii-460gt", "ibm,rgmii"; - reg = <ef601600 8>; + reg = <0xef601600 0x00000008>; has-mdio; }; TAH0: emac-tah@ef601350 { compatible = "ibm,tah-460gt", "ibm,tah"; - reg = <ef601350 30>; + reg = <0xef601350 0x00000030>; }; TAH1: emac-tah@ef601450 { compatible = "ibm,tah-460gt", "ibm,tah"; - reg = <ef601450 30>; + reg = <0xef601450 0x00000030>; }; EMAC0: ethernet@ef600e00 { device_type = "network"; compatible = "ibm,emac-460gt", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC2 10 4 - /*Wake*/ 1 &UIC2 14 4>; - reg = <ef600e00 70>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 + /*Wake*/ 0x1 &UIC2 0x14 0x4>; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <0>; tah-device = <&TAH0>; @@ -304,23 +306,23 @@ device_type = "network"; compatible = "ibm,emac-460gt", "ibm,emac4"; interrupt-parent = <&EMAC1>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC2 11 4 - /*Wake*/ 1 &UIC2 15 4>; - reg = <ef600f00 70>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 + /*Wake*/ 0x1 &UIC2 0x15 0x4>; + reg = <0xef600f00 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <8>; cell-index = <1>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <1>; tah-device = <&TAH1>; @@ -334,23 +336,23 @@ device_type = "network"; compatible = "ibm,emac-460gt", "ibm,emac4"; interrupt-parent = <&EMAC2>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC2 12 4 - /*Wake*/ 1 &UIC2 16 4>; - reg = <ef601100 70>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 + /*Wake*/ 0x1 &UIC2 0x16 0x4>; + reg = <0xef601100 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <2>; - mal-rx-channel = <10>; + mal-rx-channel = <16>; cell-index = <2>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII1>; rgmii-channel = <0>; has-inverted-stacr-oc; @@ -362,23 +364,23 @@ device_type = "network"; compatible = "ibm,emac-460gt", "ibm,emac4"; interrupt-parent = <&EMAC3>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC2 13 4 - /*Wake*/ 1 &UIC2 17 4>; - reg = <ef601200 70>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4 + /*Wake*/ 0x1 &UIC2 0x17 0x4>; + reg = <0xef601200 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <3>; - mal-rx-channel = <18>; + mal-rx-channel = <24>; cell-index = <3>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII1>; rgmii-channel = <1>; has-inverted-stacr-oc; @@ -396,27 +398,27 @@ primary; large-inbound-windows; enable-msi-hole; - reg = <c 0ec00000 8 /* Config space access */ - 0 0 0 /* no IACK cycles */ - c 0ed00000 4 /* Special cycles */ - c 0ec80000 100 /* Internal registers */ - c 0ec80100 fc>; /* Internal messaging registers */ + reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ + 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ + 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 - 01000000 0 00000000 0000000c 08000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0 to 0x3f */ - bus-range = <0 3f>; + bus-range = <0x0 0x3f>; /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ - interrupt-map-mask = <0000 0 0 0>; - interrupt-map = < 0000 0 0 0 &UIC1 0 8 >; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; }; PCIE0: pciex@d00000000 { @@ -426,23 +428,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; primary; - port = <0>; /* port number */ - reg = <d 00000000 20000000 /* Config space access */ - c 08010000 00001000>; /* Registers */ - dcr-reg = <100 020>; - sdr-base = <300>; + port = <0x0>; /* port number */ + reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ + 0x0000000c 0x08010000 0x00001000>; /* Registers */ + dcr-reg = <0x100 0x020>; + sdr-base = <0x300>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 - 01000000 0 00000000 0000000f 80000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 40 to 0x7f */ - bus-range = <40 7f>; + bus-range = <0x40 0x7f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -452,12 +454,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 c 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 d 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 e 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; }; PCIE1: pciex@d20000000 { @@ -467,23 +469,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; primary; - port = <1>; /* port number */ - reg = <d 20000000 20000000 /* Config space access */ - c 08011000 00001000>; /* Registers */ - dcr-reg = <120 020>; - sdr-base = <340>; + port = <0x1>; /* port number */ + reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ + 0x0000000c 0x08011000 0x00001000>; /* Registers */ + dcr-reg = <0x120 0x020>; + sdr-base = <0x340>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 - 01000000 0 00000000 0000000f 80010000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 80 to 0xbf */ - bus-range = <80 bf>; + bus-range = <0x80 0xbf>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -493,12 +495,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 10 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 11 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 12 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; }; }; }; diff --git a/arch/powerpc/boot/dts/haleakala.dts b/arch/powerpc/boot/dts/haleakala.dts index b5d95ac..2c2fcea 100644 --- a/arch/powerpc/boot/dts/haleakala.dts +++ b/arch/powerpc/boot/dts/haleakala.dts @@ -8,12 +8,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <1>; #size-cells = <1>; model = "amcc,haleakala"; compatible = "amcc,haleakala", "amcc,kilauea"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -28,13 +30,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,405EXr"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by U-Boot */ timebase-frequency = <0>; /* Filled in by U-Boot */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <4000>; /* 16 kB */ - d-cache-size = <4000>; /* 16 kB */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <16384>; /* 16 kB */ + d-cache-size = <16384>; /* 16 kB */ dcr-controller; dcr-access-method = "native"; }; @@ -42,14 +44,14 @@ memory { device_type = "memory"; - reg = <0 0>; /* Filled in by U-Boot */ + reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ }; UIC0: interrupt-controller { compatible = "ibm,uic-405exr", "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -59,11 +61,11 @@ compatible = "ibm,uic-405exr","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -71,11 +73,11 @@ compatible = "ibm,uic-405exr","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1c 4 1d 4>; /* cascade */ + interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -88,72 +90,72 @@ SDRAM0: memory-controller { compatible = "ibm,sdram-405exr"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal-405exr", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 - /*RXEOB*/ 1 &UIC0 b 4 - /*SERR*/ 2 &UIC1 0 4 - /*TXDE*/ 3 &UIC1 1 4 - /*RXDE*/ 4 &UIC1 2 4>; - interrupt-map-mask = <ffffffff>; + interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 + /*RXEOB*/ 0x1 &UIC0 0xb 0x4 + /*SERR*/ 0x2 &UIC1 0x0 0x4 + /*TXDE*/ 0x3 &UIC1 0x1 0x4 + /*RXDE*/ 0x4 &UIC1 0x2 0x4>; + interrupt-map-mask = <0xffffffff>; }; POB0: opb { compatible = "ibm,opb-405exr", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <80000000 80000000 10000000 - ef600000 ef600000 a00000 - f0000000 f0000000 10000000>; - dcr-reg = <0a0 5>; + ranges = <0x80000000 0x80000000 0x10000000 + 0xef600000 0xef600000 0x00a00000 + 0xf0000000 0xf0000000 0x10000000>; + dcr-reg = <0x0a0 0x005>; clock-frequency = <0>; /* Filled in by U-Boot */ EBC0: ebc { compatible = "ibm,ebc-405exr", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by U-Boot */ /* ranges property is supplied by U-Boot */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl512n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "kernel"; - reg = <0 200000>; + reg = <0x00000000 0x00200000>; }; partition@200000 { label = "root"; - reg = <200000 200000>; + reg = <0x00200000 0x00200000>; }; partition@400000 { label = "user"; - reg = <400000 3b60000>; + reg = <0x00400000 0x03b60000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; }; @@ -161,68 +163,68 @@ UART0: serial@ef600200 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600200 8>; - virtual-reg = <ef600200>; + reg = <0xef600200 0x00000008>; + virtual-reg = <0xef600200>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1a 4>; + interrupts = <0x1a 0x4>; }; UART1: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600300 8>; - virtual-reg = <ef600300>; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC0: i2c@ef600400 { compatible = "ibm,iic-405exr", "ibm,iic"; - reg = <ef600400 14>; + reg = <0xef600400 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600500 { compatible = "ibm,iic-405exr", "ibm,iic"; - reg = <ef600500 14>; + reg = <0xef600500 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; RGMII0: emac-rgmii@ef600b00 { compatible = "ibm,rgmii-405exr", "ibm,rgmii"; - reg = <ef600b00 104>; + reg = <0xef600b00 0x00000104>; has-mdio; }; EMAC0: ethernet@ef600900 { - linux,network-index = <0>; + linux,network-index = <0x0>; device_type = "network"; compatible = "ibm,emac-405exr", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC0 18 4 - /*Wake*/ 1 &UIC1 1d 4>; - reg = <ef600900 70>; + interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4 + /*Wake*/ 0x1 &UIC1 0x1d 0x4>; + reg = <0xef600900 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <0>; has-inverted-stacr-oc; @@ -237,23 +239,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; primary; - port = <0>; /* port number */ - reg = <a0000000 20000000 /* Config space access */ - ef000000 00001000>; /* Registers */ - dcr-reg = <040 020>; - sdr-base = <400>; + port = <0x0>; /* port number */ + reg = <0xa0000000 0x20000000 /* Config space access */ + 0xef000000 0x00001000>; /* Registers */ + dcr-reg = <0x040 0x020>; + sdr-base = <0x400>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 90000000 0 08000000 - 01000000 0 00000000 e0000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 + 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0x00 to 0x3f */ - bus-range = <00 3f>; + bus-range = <0x0 0x3f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -263,12 +265,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ - 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ - 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ - 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; }; }; }; diff --git a/arch/powerpc/boot/dts/holly.dts b/arch/powerpc/boot/dts/holly.dts index b5d8789..f87fe7b 100644 --- a/arch/powerpc/boot/dts/holly.dts +++ b/arch/powerpc/boot/dts/holly.dts @@ -10,6 +10,8 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { model = "41K7339"; compatible = "ibm,holly"; @@ -21,22 +23,22 @@ #size-cells =<0>; PowerPC,750CL@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; - i-cache-line-size = <20>; - d-cache-size = <8000>; - i-cache-size = <8000>; - d-cache-sets = <80>; - i-cache-sets = <80>; - timebase-frequency = <2faf080>; - clock-frequency = <23c34600>; - bus-frequency = <bebc200>; + reg = <0x00000000>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + d-cache-sets = <128>; + i-cache-sets = <128>; + timebase-frequency = <50000000>; + clock-frequency = <600000000>; + bus-frequency = <200000000>; }; }; memory@0 { device_type = "memory"; - reg = <00000000 20000000>; + reg = <0x00000000 0x20000000>; }; tsi109@c0000000 { @@ -44,33 +46,33 @@ compatible = "tsi109-bridge", "tsi108-bridge"; #address-cells = <1>; #size-cells = <1>; - ranges = <00000000 c0000000 00010000>; - reg = <c0000000 00010000>; + ranges = <0x00000000 0xc0000000 0x00010000>; + reg = <0xc0000000 0x00010000>; i2c@7000 { device_type = "i2c"; compatible = "tsi109-i2c", "tsi108-i2c"; interrupt-parent = <&MPIC>; - interrupts = <e 2>; - reg = <7000 400>; + interrupts = <0xe 0x2>; + reg = <0x00007000 0x00000400>; }; MDIO: mdio@6000 { device_type = "mdio"; compatible = "tsi109-mdio", "tsi108-mdio"; - reg = <6000 50>; + reg = <0x00006000 0x00000050>; #address-cells = <1>; #size-cells = <0>; PHY1: ethernet-phy@1 { compatible = "bcm5461a"; - reg = <1>; + reg = <0x00000001>; txc-rxc-delay-disable; }; PHY2: ethernet-phy@2 { compatible = "bcm5461a"; - reg = <2>; + reg = <0x00000002>; txc-rxc-delay-disable; }; }; @@ -80,10 +82,10 @@ compatible = "tsi109-ethernet", "tsi108-ethernet"; #address-cells = <1>; #size-cells = <0>; - reg = <6000 200>; + reg = <0x00006000 0x00000200>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupt-parent = <&MPIC>; - interrupts = <10 2>; + interrupts = <0x10 0x2>; mdio-handle = <&MDIO>; phy-handle = <&PHY1>; }; @@ -93,10 +95,10 @@ compatible = "tsi109-ethernet", "tsi108-ethernet"; #address-cells = <1>; #size-cells = <0>; - reg = <6400 200>; + reg = <0x00006400 0x00000200>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupt-parent = <&MPIC>; - interrupts = <11 2>; + interrupts = <0x11 0x2>; mdio-handle = <&MDIO>; phy-handle = <&PHY2>; }; @@ -104,23 +106,23 @@ serial@7808 { device_type = "serial"; compatible = "ns16550"; - reg = <7808 200>; - virtual-reg = <c0007808>; - clock-frequency = <3F9C6000>; - current-speed = <1c200>; + reg = <0x00007808 0x00000200>; + virtual-reg = <0xc0007808>; + clock-frequency = <1067212800>; + current-speed = <115200>; interrupt-parent = <&MPIC>; - interrupts = <c 2>; + interrupts = <0xc 0x2>; }; serial@7c08 { device_type = "serial"; compatible = "ns16550"; - reg = <7c08 200>; - virtual-reg = <c0007c08>; - clock-frequency = <3F9C6000>; - current-speed = <1c200>; + reg = <0x00007c08 0x00000200>; + virtual-reg = <0xc0007c08>; + clock-frequency = <1067212800>; + current-speed = <115200>; interrupt-parent = <&MPIC>; - interrupts = <d 2>; + interrupts = <0xd 0x2>; }; MPIC: pic@7400 { @@ -128,7 +130,7 @@ compatible = "chrp,open-pic"; interrupt-controller; #interrupt-cells = <2>; - reg = <7400 400>; + reg = <0x00007400 0x00000400>; big-endian; }; @@ -138,42 +140,42 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <1000 1000>; - bus-range = <0 0>; + reg = <0x00001000 0x00001000>; + bus-range = <0x0 0x0>; /*----------------------------------------------------+ | PCI memory range. | 01 denotes I/O space | 02 denotes 32-bit memory space +----------------------------------------------------*/ - ranges = <02000000 0 40000000 40000000 0 10000000 - 01000000 0 00000000 7e000000 0 00010000>; - clock-frequency = <7f28154>; + ranges = <0x02000000 0x00000000 0x40000000 0x40000000 0x00000000 0x10000000 + 0x01000000 0x00000000 0x00000000 0x7e000000 0x00000000 0x00010000>; + clock-frequency = <133333332>; interrupt-parent = <&MPIC>; - interrupts = <17 2>; - interrupt-map-mask = <f800 0 0 7>; + interrupts = <0x17 0x2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; /*----------------------------------------------------+ | The INTA, INTB, INTC, INTD are shared. +----------------------------------------------------*/ interrupt-map = < - 0800 0 0 1 &RT0 24 0 - 0800 0 0 2 &RT0 25 0 - 0800 0 0 3 &RT0 26 0 - 0800 0 0 4 &RT0 27 0 - - 1000 0 0 1 &RT0 25 0 - 1000 0 0 2 &RT0 26 0 - 1000 0 0 3 &RT0 27 0 - 1000 0 0 4 &RT0 24 0 - - 1800 0 0 1 &RT0 26 0 - 1800 0 0 2 &RT0 27 0 - 1800 0 0 3 &RT0 24 0 - 1800 0 0 4 &RT0 25 0 - - 2000 0 0 1 &RT0 27 0 - 2000 0 0 2 &RT0 24 0 - 2000 0 0 3 &RT0 25 0 - 2000 0 0 4 &RT0 26 0 + 0x800 0x0 0x0 0x1 &RT0 0x24 0x0 + 0x800 0x0 0x0 0x2 &RT0 0x25 0x0 + 0x800 0x0 0x0 0x3 &RT0 0x26 0x0 + 0x800 0x0 0x0 0x4 &RT0 0x27 0x0 + + 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0 + 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0 + 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0 + 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0 + + 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0 + 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0 + 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0 + 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0 + + 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0 + 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0 + 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0 + 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0 >; RT0: router@1180 { @@ -183,7 +185,7 @@ clock-frequency = <0>; #address-cells = <0>; #interrupt-cells = <2>; - interrupts = <17 2>; + interrupts = <0x17 0x2>; interrupt-parent = <&MPIC>; }; }; diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts index cc2873a..b94bf61 100644 --- a/arch/powerpc/boot/dts/katmai.dts +++ b/arch/powerpc/boot/dts/katmai.dts @@ -12,12 +12,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,katmai"; compatible = "amcc,katmai"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -33,13 +35,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440SPe"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -47,14 +49,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440spe","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -64,11 +66,11 @@ compatible = "ibm,uic-440spe","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -76,11 +78,11 @@ compatible = "ibm,uic-440spe","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <a 4 b 4>; /* cascade */ + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -88,22 +90,22 @@ compatible = "ibm,uic-440spe","ibm,uic"; interrupt-controller; cell-index = <3>; - dcr-reg = <0f0 009>; + dcr-reg = <0x0f0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <10 4 11 4>; /* cascade */ + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440spe"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-440spe"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -115,108 +117,108 @@ SDRAM0: sdram { compatible = "ibm,sdram-440spe", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal-440spe", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; num-rx-chans = <1>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*TXEOB*/ 0 &UIC1 6 4 - /*RXEOB*/ 1 &UIC1 7 4 - /*SERR*/ 2 &UIC1 1 4 - /*TXDE*/ 3 &UIC1 2 4 - /*RXDE*/ 4 &UIC1 3 4>; + interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4 + /*RXEOB*/ 0x1 &UIC1 0x7 0x4 + /*SERR*/ 0x2 &UIC1 0x1 0x4 + /*TXDE*/ 0x3 &UIC1 0x2 0x4 + /*RXDE*/ 0x4 &UIC1 0x3 0x4>; }; POB0: opb { compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <00000000 4 e0000000 20000000>; + ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; }; UART0: serial@10000200 { device_type = "serial"; compatible = "ns16550"; - reg = <10000200 8>; - virtual-reg = <a0000200>; + reg = <0x10000200 0x00000008>; + virtual-reg = <0xa0000200>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <115200>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@10000300 { device_type = "serial"; compatible = "ns16550"; - reg = <10000300 8>; - virtual-reg = <a0000300>; + reg = <0x10000300 0x00000008>; + virtual-reg = <0xa0000300>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@10000600 { device_type = "serial"; compatible = "ns16550"; - reg = <10000600 8>; - virtual-reg = <a0000600>; + reg = <0x10000600 0x00000008>; + virtual-reg = <0xa0000600>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC1>; - interrupts = <5 4>; + interrupts = <0x5 0x4>; }; IIC0: i2c@10000400 { compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; - reg = <10000400 14>; + reg = <0x10000400 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@10000500 { compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; - reg = <10000500 14>; + reg = <0x10000500 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; EMAC0: ethernet@10000800 { - linux,network-index = <0>; + linux,network-index = <0x0>; device_type = "network"; compatible = "ibm,emac-440spe", "ibm,emac4"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = <10000800 70>; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0x10000800 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "gmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; has-inverted-stacr-oc; has-new-stacr-staopc; }; @@ -231,23 +233,23 @@ primary; large-inbound-windows; enable-msi-hole; - reg = <c 0ec00000 8 /* Config space access */ - 0 0 0 /* no IACK cycles */ - c 0ed00000 4 /* Special cycles */ - c 0ec80000 100 /* Internal registers */ - c 0ec80100 fc>; /* Internal messaging registers */ + reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ + 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ + 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 - 01000000 0 00000000 0000000c 08000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0 to 0xf */ - bus-range = <0 f>; + bus-range = <0x0 0xf>; /* * On Katmai, the following PCI-X interrupts signals @@ -258,13 +260,13 @@ * INTC: J2: 1-2 * INTD: J1: 1-2 */ - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 1 */ - 0800 0 0 1 &UIC1 14 8 - 0800 0 0 2 &UIC1 13 8 - 0800 0 0 3 &UIC1 12 8 - 0800 0 0 4 &UIC1 11 8 + 0x800 0x0 0x0 0x1 &UIC1 0x14 0x8 + 0x800 0x0 0x0 0x2 &UIC1 0x13 0x8 + 0x800 0x0 0x0 0x3 &UIC1 0x12 0x8 + 0x800 0x0 0x0 0x4 &UIC1 0x11 0x8 >; }; @@ -275,23 +277,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; primary; - port = <0>; /* port number */ - reg = <d 00000000 20000000 /* Config space access */ - c 10000000 00001000>; /* Registers */ - dcr-reg = <100 020>; - sdr-base = <300>; + port = <0x0>; /* port number */ + reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ + 0x0000000c 0x10000000 0x00001000>; /* Registers */ + dcr-reg = <0x100 0x020>; + sdr-base = <0x300>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 - 01000000 0 00000000 0000000f 80000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 10 to 0x1f */ - bus-range = <10 1f>; + bus-range = <0x10 0x1f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -301,12 +303,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 0 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 1 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 2 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 3 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>; }; PCIE1: pciex@d20000000 { @@ -316,23 +318,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; primary; - port = <1>; /* port number */ - reg = <d 20000000 20000000 /* Config space access */ - c 10001000 00001000>; /* Registers */ - dcr-reg = <120 020>; - sdr-base = <340>; + port = <0x1>; /* port number */ + reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ + 0x0000000c 0x10001000 0x00001000>; /* Registers */ + dcr-reg = <0x120 0x020>; + sdr-base = <0x340>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 - 01000000 0 00000000 0000000f 80010000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 10 to 0x1f */ - bus-range = <20 2f>; + bus-range = <0x20 0x2f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -342,12 +344,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 4 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 5 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 6 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 7 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>; }; PCIE2: pciex@d40000000 { @@ -357,23 +359,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; primary; - port = <2>; /* port number */ - reg = <d 40000000 20000000 /* Config space access */ - c 10002000 00001000>; /* Registers */ - dcr-reg = <140 020>; - sdr-base = <370>; + port = <0x2>; /* port number */ + reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */ + 0x0000000c 0x10002000 0x00001000>; /* Registers */ + dcr-reg = <0x140 0x020>; + sdr-base = <0x370>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000f 00000000 0 80000000 - 01000000 0 00000000 0000000f 80020000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 10 to 0x1f */ - bus-range = <30 3f>; + bus-range = <0x30 0x3f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -383,12 +385,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 8 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 9 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 a 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 b 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>; }; }; diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts index 48c9a6e..3ed6a8f 100644 --- a/arch/powerpc/boot/dts/kilauea.dts +++ b/arch/powerpc/boot/dts/kilauea.dts @@ -8,12 +8,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <1>; #size-cells = <1>; model = "amcc,kilauea"; compatible = "amcc,kilauea"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -29,13 +31,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,405EX"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by U-Boot */ timebase-frequency = <0>; /* Filled in by U-Boot */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <4000>; /* 16 kB */ - d-cache-size = <4000>; /* 16 kB */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <16384>; /* 16 kB */ + d-cache-size = <16384>; /* 16 kB */ dcr-controller; dcr-access-method = "native"; }; @@ -43,14 +45,14 @@ memory { device_type = "memory"; - reg = <0 0>; /* Filled in by U-Boot */ + reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ }; UIC0: interrupt-controller { compatible = "ibm,uic-405ex", "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -60,11 +62,11 @@ compatible = "ibm,uic-405ex","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -72,11 +74,11 @@ compatible = "ibm,uic-405ex","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1c 4 1d 4>; /* cascade */ + interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -89,72 +91,72 @@ SDRAM0: memory-controller { compatible = "ibm,sdram-405ex"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 - /*RXEOB*/ 1 &UIC0 b 4 - /*SERR*/ 2 &UIC1 0 4 - /*TXDE*/ 3 &UIC1 1 4 - /*RXDE*/ 4 &UIC1 2 4>; - interrupt-map-mask = <ffffffff>; + interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 + /*RXEOB*/ 0x1 &UIC0 0xb 0x4 + /*SERR*/ 0x2 &UIC1 0x0 0x4 + /*TXDE*/ 0x3 &UIC1 0x1 0x4 + /*RXDE*/ 0x4 &UIC1 0x2 0x4>; + interrupt-map-mask = <0xffffffff>; }; POB0: opb { compatible = "ibm,opb-405ex", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <80000000 80000000 10000000 - ef600000 ef600000 a00000 - f0000000 f0000000 10000000>; - dcr-reg = <0a0 5>; + ranges = <0x80000000 0x80000000 0x10000000 + 0xef600000 0xef600000 0x00a00000 + 0xf0000000 0xf0000000 0x10000000>; + dcr-reg = <0x0a0 0x005>; clock-frequency = <0>; /* Filled in by U-Boot */ EBC0: ebc { compatible = "ibm,ebc-405ex", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by U-Boot */ /* ranges property is supplied by U-Boot */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl512n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "kernel"; - reg = <0 200000>; + reg = <0x00000000 0x00200000>; }; partition@200000 { label = "root"; - reg = <200000 200000>; + reg = <0x00200000 0x00200000>; }; partition@400000 { label = "user"; - reg = <400000 3b60000>; + reg = <0x00400000 0x03b60000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; }; @@ -162,68 +164,68 @@ UART0: serial@ef600200 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600200 8>; - virtual-reg = <ef600200>; + reg = <0xef600200 0x00000008>; + virtual-reg = <0xef600200>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1a 4>; + interrupts = <0x1a 0x4>; }; UART1: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600300 8>; - virtual-reg = <ef600300>; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC0: i2c@ef600400 { compatible = "ibm,iic-405ex", "ibm,iic"; - reg = <ef600400 14>; + reg = <0xef600400 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600500 { compatible = "ibm,iic-405ex", "ibm,iic"; - reg = <ef600500 14>; + reg = <0xef600500 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; RGMII0: emac-rgmii@ef600b00 { compatible = "ibm,rgmii-405ex", "ibm,rgmii"; - reg = <ef600b00 104>; + reg = <0xef600b00 0x00000104>; has-mdio; }; EMAC0: ethernet@ef600900 { - linux,network-index = <0>; + linux,network-index = <0x0>; device_type = "network"; compatible = "ibm,emac-405ex", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC0 18 4 - /*Wake*/ 1 &UIC1 1d 4>; - reg = <ef600900 70>; + interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4 + /*Wake*/ 0x1 &UIC1 0x1d 0x4>; + reg = <0xef600900 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <0>; has-inverted-stacr-oc; @@ -231,27 +233,27 @@ }; EMAC1: ethernet@ef600a00 { - linux,network-index = <1>; + linux,network-index = <0x1>; device_type = "network"; compatible = "ibm,emac-405ex", "ibm,emac4"; interrupt-parent = <&EMAC1>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC0 19 4 - /*Wake*/ 1 &UIC1 1f 4>; - reg = <ef600a00 70>; + interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4 + /*Wake*/ 0x1 &UIC1 0x1f 0x4>; + reg = <0xef600a00 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <1>; has-inverted-stacr-oc; @@ -266,23 +268,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; primary; - port = <0>; /* port number */ - reg = <a0000000 20000000 /* Config space access */ - ef000000 00001000>; /* Registers */ - dcr-reg = <040 020>; - sdr-base = <400>; + port = <0x0>; /* port number */ + reg = <0xa0000000 0x20000000 /* Config space access */ + 0xef000000 0x00001000>; /* Registers */ + dcr-reg = <0x040 0x020>; + sdr-base = <0x400>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 90000000 0 08000000 - 01000000 0 00000000 e0000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 + 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0x00 to 0x3f */ - bus-range = <00 3f>; + bus-range = <0x0 0x3f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -292,12 +294,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ - 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ - 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ - 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; }; PCIE1: pciex@0c0000000 { @@ -307,23 +309,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; primary; - port = <1>; /* port number */ - reg = <c0000000 20000000 /* Config space access */ - ef001000 00001000>; /* Registers */ - dcr-reg = <060 020>; - sdr-base = <440>; + port = <0x1>; /* port number */ + reg = <0xc0000000 0x20000000 /* Config space access */ + 0xef001000 0x00001000>; /* Registers */ + dcr-reg = <0x060 0x020>; + sdr-base = <0x440>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 98000000 0 08000000 - 01000000 0 00000000 e0010000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000 + 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0x40 to 0x7f */ - bus-range = <40 7f>; + bus-range = <0x40 0x7f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -333,12 +335,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC2 b 4 /* swizzled int A */ - 0000 0 0 2 &UIC2 c 4 /* swizzled int B */ - 0000 0 0 3 &UIC2 d 4 /* swizzled int C */ - 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; }; }; }; diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts index f869ce3c..fd58043 100644 --- a/arch/powerpc/boot/dts/ksi8560.dts +++ b/arch/powerpc/boot/dts/ksi8560.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; /* From U-boot */ bus-frequency = <0>; /* From U-boot */ clock-frequency = <0>; /* From U-boot */ + next-level-cache = <&L2>; }; }; @@ -62,7 +63,7 @@ interrupts = <0x12 0x2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; /* 32 bytes */ @@ -82,6 +83,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { /* For TSECs */ #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/makalu.dts b/arch/powerpc/boot/dts/makalu.dts index 84cc5e7..1dfcd7e 100644 --- a/arch/powerpc/boot/dts/makalu.dts +++ b/arch/powerpc/boot/dts/makalu.dts @@ -8,12 +8,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <1>; #size-cells = <1>; model = "amcc,makalu"; compatible = "amcc,makalu"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -29,13 +31,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,405EX"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by U-Boot */ timebase-frequency = <0>; /* Filled in by U-Boot */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <4000>; /* 16 kB */ - d-cache-size = <4000>; /* 16 kB */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <16384>; /* 16 kB */ + d-cache-size = <16384>; /* 16 kB */ dcr-controller; dcr-access-method = "native"; }; @@ -43,14 +45,14 @@ memory { device_type = "memory"; - reg = <0 0>; /* Filled in by U-Boot */ + reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ }; UIC0: interrupt-controller { compatible = "ibm,uic-405ex", "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -60,11 +62,11 @@ compatible = "ibm,uic-405ex","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -72,11 +74,11 @@ compatible = "ibm,uic-405ex","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1c 4 1d 4>; /* cascade */ + interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -89,72 +91,72 @@ SDRAM0: memory-controller { compatible = "ibm,sdram-405ex"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 - /*RXEOB*/ 1 &UIC0 b 4 - /*SERR*/ 2 &UIC1 0 4 - /*TXDE*/ 3 &UIC1 1 4 - /*RXDE*/ 4 &UIC1 2 4>; - interrupt-map-mask = <ffffffff>; + interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 + /*RXEOB*/ 0x1 &UIC0 0xb 0x4 + /*SERR*/ 0x2 &UIC1 0x0 0x4 + /*TXDE*/ 0x3 &UIC1 0x1 0x4 + /*RXDE*/ 0x4 &UIC1 0x2 0x4>; + interrupt-map-mask = <0xffffffff>; }; POB0: opb { compatible = "ibm,opb-405ex", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <80000000 80000000 10000000 - ef600000 ef600000 a00000 - f0000000 f0000000 10000000>; - dcr-reg = <0a0 5>; + ranges = <0x80000000 0x80000000 0x10000000 + 0xef600000 0xef600000 0x00a00000 + 0xf0000000 0xf0000000 0x10000000>; + dcr-reg = <0x0a0 0x005>; clock-frequency = <0>; /* Filled in by U-Boot */ EBC0: ebc { compatible = "ibm,ebc-405ex", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by U-Boot */ /* ranges property is supplied by U-Boot */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl512n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "kernel"; - reg = <0 200000>; + reg = <0x00000000 0x00200000>; }; partition@200000 { label = "root"; - reg = <200000 200000>; + reg = <0x00200000 0x00200000>; }; partition@400000 { label = "user"; - reg = <400000 3b60000>; + reg = <0x00400000 0x03b60000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; }; @@ -162,68 +164,68 @@ UART0: serial@ef600200 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600200 8>; - virtual-reg = <ef600200>; + reg = <0xef600200 0x00000008>; + virtual-reg = <0xef600200>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1a 4>; + interrupts = <0x1a 0x4>; }; UART1: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600300 8>; - virtual-reg = <ef600300>; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC0: i2c@ef600400 { compatible = "ibm,iic-405ex", "ibm,iic"; - reg = <ef600400 14>; + reg = <0xef600400 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600500 { compatible = "ibm,iic-405ex", "ibm,iic"; - reg = <ef600500 14>; + reg = <0xef600500 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; RGMII0: emac-rgmii@ef600b00 { compatible = "ibm,rgmii-405ex", "ibm,rgmii"; - reg = <ef600b00 104>; + reg = <0xef600b00 0x00000104>; has-mdio; }; EMAC0: ethernet@ef600900 { - linux,network-index = <0>; + linux,network-index = <0x0>; device_type = "network"; compatible = "ibm,emac-405ex", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC0 18 4 - /*Wake*/ 1 &UIC1 1d 4>; - reg = <ef600900 70>; + interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4 + /*Wake*/ 0x1 &UIC1 0x1d 0x4>; + reg = <0xef600900 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <0000003f>; /* Start at 6 */ + phy-map = <0x0000003f>; /* Start at 6 */ rgmii-device = <&RGMII0>; rgmii-channel = <0>; has-inverted-stacr-oc; @@ -231,27 +233,27 @@ }; EMAC1: ethernet@ef600a00 { - linux,network-index = <1>; + linux,network-index = <0x1>; device_type = "network"; compatible = "ibm,emac-405ex", "ibm,emac4"; interrupt-parent = <&EMAC1>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC0 19 4 - /*Wake*/ 1 &UIC1 1f 4>; - reg = <ef600a00 70>; + interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4 + /*Wake*/ 0x1 &UIC1 0x1f 0x4>; + reg = <0xef600a00 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <1>; has-inverted-stacr-oc; @@ -266,23 +268,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; primary; - port = <0>; /* port number */ - reg = <a0000000 20000000 /* Config space access */ - ef000000 00001000>; /* Registers */ - dcr-reg = <040 020>; - sdr-base = <400>; + port = <0x0>; /* port number */ + reg = <0xa0000000 0x20000000 /* Config space access */ + 0xef000000 0x00001000>; /* Registers */ + dcr-reg = <0x040 0x020>; + sdr-base = <0x400>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 90000000 0 08000000 - 01000000 0 00000000 e0000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 + 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0x00 to 0x3f */ - bus-range = <00 3f>; + bus-range = <0x0 0x3f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -292,12 +294,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ - 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ - 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ - 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; }; PCIE1: pciex@0c0000000 { @@ -307,23 +309,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; primary; - port = <1>; /* port number */ - reg = <c0000000 20000000 /* Config space access */ - ef001000 00001000>; /* Registers */ - dcr-reg = <060 020>; - sdr-base = <440>; + port = <0x1>; /* port number */ + reg = <0xc0000000 0x20000000 /* Config space access */ + 0xef001000 0x00001000>; /* Registers */ + dcr-reg = <0x060 0x020>; + sdr-base = <0x440>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 98000000 0 08000000 - 01000000 0 00000000 e0010000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000 + 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0x40 to 0x7f */ - bus-range = <40 7f>; + bus-range = <0x40 0x7f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -333,12 +335,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC2 b 4 /* swizzled int A */ - 0000 0 0 2 &UIC2 c 4 /* swizzled int B */ - 0000 0 0 3 &UIC2 d 4 /* swizzled int C */ - 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; }; }; }; diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts index 4936349..705c23c 100644 --- a/arch/powerpc/boot/dts/mpc7448hpc2.dts +++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts @@ -124,14 +124,12 @@ }; mpic: pic@7400 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x7400 0x400>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; pci@1000 { compatible = "tsi108-pci"; diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts index e1f0dca..b206843 100644 --- a/arch/powerpc/boot/dts/mpc8313erdb.dts +++ b/arch/powerpc/boot/dts/mpc8313erdb.dts @@ -144,6 +144,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8313-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ usb@23000 { compatible = "fsl-usb2-dr"; diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts index d7a1ece..a40e806 100644 --- a/arch/powerpc/boot/dts/mpc8315erdb.dts +++ b/arch/powerpc/boot/dts/mpc8315erdb.dts @@ -132,6 +132,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8315-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts index 539e02f..b5968b6 100644 --- a/arch/powerpc/boot/dts/mpc832x_mds.dts +++ b/arch/powerpc/boot/dts/mpc832x_mds.dts @@ -114,6 +114,41 @@ interrupt-parent = <&ipic>; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8323-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + crypto@30000 { device_type = "crypto"; model = "SEC2"; diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts index 179c81c..a798d86 100644 --- a/arch/powerpc/boot/dts/mpc832x_rdb.dts +++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts @@ -68,7 +68,7 @@ compatible = "fsl-i2c"; reg = <0x3000 0x100>; interrupts = <14 0x8>; - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; dfsrr; }; @@ -79,7 +79,7 @@ reg = <0x4500 0x100>; clock-frequency = <0>; interrupts = <9 0x8>; - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; }; serial1: serial@4600 { @@ -89,7 +89,42 @@ reg = <0x4600 0x100>; clock-frequency = <0>; interrupts = <10 0x8>; - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8323-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; }; crypto@30000 { @@ -98,7 +133,7 @@ compatible = "talitos"; reg = <0x30000 0x7000>; interrupts = <11 0x8>; - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; /* Rev. 2.2 */ num-channels = <1>; channel-fifo-len = <24>; @@ -106,7 +141,7 @@ descriptor-types-mask = <0x0122003f>; }; - pic:pic@700 { + ipic:pic@700 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; @@ -240,13 +275,13 @@ compatible = "fsl,ucc-mdio"; phy00:ethernet-phy@00 { - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; interrupts = <0>; reg = <0x0>; device_type = "ethernet-phy"; }; phy04:ethernet-phy@04 { - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; interrupts = <0>; reg = <0x4>; device_type = "ethernet-phy"; @@ -261,7 +296,7 @@ reg = <0x80 0x80>; big-endian; interrupts = <32 0x8 33 0x8>; //high:32 low:33 - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; }; }; @@ -270,21 +305,21 @@ interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x10 AD16 (USB) */ - 0x8000 0x0 0x0 0x1 &pic 17 0x8 + 0x8000 0x0 0x0 0x1 &ipic 17 0x8 /* IDSEL 0x11 AD17 (Mini1)*/ - 0x8800 0x0 0x0 0x1 &pic 18 0x8 - 0x8800 0x0 0x0 0x2 &pic 19 0x8 - 0x8800 0x0 0x0 0x3 &pic 20 0x8 - 0x8800 0x0 0x0 0x4 &pic 48 0x8 + 0x8800 0x0 0x0 0x1 &ipic 18 0x8 + 0x8800 0x0 0x0 0x2 &ipic 19 0x8 + 0x8800 0x0 0x0 0x3 &ipic 20 0x8 + 0x8800 0x0 0x0 0x4 &ipic 48 0x8 /* IDSEL 0x12 AD18 (PCI/Mini2) */ - 0x9000 0x0 0x0 0x1 &pic 19 0x8 - 0x9000 0x0 0x0 0x2 &pic 20 0x8 - 0x9000 0x0 0x0 0x3 &pic 48 0x8 - 0x9000 0x0 0x0 0x4 &pic 17 0x8>; + 0x9000 0x0 0x0 0x1 &ipic 19 0x8 + 0x9000 0x0 0x0 0x2 &ipic 20 0x8 + 0x9000 0x0 0x0 0x3 &ipic 48 0x8 + 0x9000 0x0 0x0 0x4 &ipic 17 0x8>; - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; interrupts = <66 0x8>; bus-range = <0x0 0x0>; ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts index 9426676..fc0f4c9 100644 --- a/arch/powerpc/boot/dts/mpc8349emitx.dts +++ b/arch/powerpc/boot/dts/mpc8349emitx.dts @@ -93,6 +93,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@22000 { compatible = "fsl-usb2-mph"; reg = <0x22000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts index f81d735..e6afb1d 100644 --- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts +++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts @@ -91,6 +91,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts index 0199c5c..9c75c7c 100644 --- a/arch/powerpc/boot/dts/mpc834x_mds.dts +++ b/arch/powerpc/boot/dts/mpc834x_mds.dts @@ -103,6 +103,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + /* phy type (ULPI or SERIAL) are only types supported for MPH */ /* port = 0 or 1 */ usb@22000 { diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts index 8160ff2..8e33b15 100644 --- a/arch/powerpc/boot/dts/mpc836x_mds.dts +++ b/arch/powerpc/boot/dts/mpc836x_mds.dts @@ -118,6 +118,41 @@ interrupt-parent = <&ipic>; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + crypto@30000 { device_type = "crypto"; model = "SEC2"; diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts new file mode 100644 index 0000000..8acd1d6 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts @@ -0,0 +1,432 @@ +/* + * MPC8360E RDK Device Tree Source + * + * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2007-2008 MontaVista Software, Inc. + * + * Author: Anton Vorontsov <avorontsov@ru.mvista.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8360rdk"; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + pci0 = &pci0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8360@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + /* filled by u-boot */ + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + /* filled by u-boot */ + reg = <0 0>; + }; + + soc@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc", + "simple-bus"; + ranges = <0 0xe0000000 0x200000>; + reg = <0xe0000000 0x200>; + /* filled by u-boot */ + bus-frequency = <0>; + + wdt@200 { + compatible = "mpc83xx_wdt"; + reg = <0x200 0x100>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <16 8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + serial0: serial@4500 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + interrupts = <9 8>; + interrupt-parent = <&ipic>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + + serial1: serial@4600 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + interrupts = <10 8>; + interrupt-parent = <&ipic>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + + crypto@30000 { + compatible = "fsl,sec2-crypto"; + reg = <0x30000 0x10000>; + interrupts = <11 8>; + interrupt-parent = <&ipic>; + num-channels = <4>; + channel-fifo-len = <24>; + exec-units-mask = <0x7e>; + /* + * desc mask is for rev1.x, we need runtime fixup + * for >=2.x + */ + descriptor-types-mask = <0x1010ebf>; + }; + + ipic: interrupt-controller@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + }; + + qe_pio_b: gpio-controller@1418 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x1418 0x18>; + gpio-controller; + }; + + qe_pio_e: gpio-controller@1460 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x1460 0x18>; + gpio-controller; + }; + + qe@100000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe", "simple-bus"; + ranges = <0 0x100000 0x100000>; + reg = <0x100000 0x480>; + /* filled by u-boot */ + clock-frequency = <0>; + bus-frequency = <0>; + brg-frequency = <0>; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0 0x10000 0xc000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0 0xc000>; + }; + }; + + timer@440 { + compatible = "fsl,mpc8360-qe-gtm", + "fsl,qe-gtm", "fsl,gtm"; + reg = <0x440 0x40>; + interrupts = <12 13 14 15>; + interrupt-parent = <&qeic>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + + spi@4c0 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x4c0 0x40>; + interrupts = <2>; + interrupt-parent = <&qeic>; + mode = "cpu-qe"; + }; + + spi@500 { + cell-index = <1>; + compatible = "fsl,spi"; + reg = <0x500 0x40>; + interrupts = <1>; + interrupt-parent = <&qeic>; + mode = "cpu-qe"; + }; + + enet0: ucc@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + rx-clock-name = "none"; + tx-clock-name = "clk9"; + phy-handle = <&phy2>; + phy-connection-type = "rgmii-rxid"; + /* filled by u-boot */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + enet1: ucc@3000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <2>; + reg = <0x3000 0x200>; + interrupts = <33>; + interrupt-parent = <&qeic>; + rx-clock-name = "none"; + tx-clock-name = "clk4"; + phy-handle = <&phy4>; + phy-connection-type = "rgmii-rxid"; + /* filled by u-boot */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + enet2: ucc@2600 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <7>; + reg = <0x2600 0x200>; + interrupts = <42>; + interrupt-parent = <&qeic>; + rx-clock-name = "clk20"; + tx-clock-name = "clk19"; + phy-handle = <&phy1>; + phy-connection-type = "mii"; + /* filled by u-boot */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + enet3: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + rx-clock-name = "clk8"; + tx-clock-name = "clk7"; + phy-handle = <&phy3>; + phy-connection-type = "mii"; + /* filled by u-boot */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + mdio@2120 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,ucc-mdio"; + reg = <0x2120 0x18>; + + phy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + compatible = "national,DP83848VV"; + reg = <1>; + }; + + phy2: ethernet-phy@2 { + device_type = "ethernet-phy"; + compatible = "broadcom,BCM5481UA2KMLG"; + reg = <2>; + }; + + phy3: ethernet-phy@3 { + device_type = "ethernet-phy"; + compatible = "national,DP83848VV"; + reg = <3>; + }; + + phy4: ethernet-phy@4 { + device_type = "ethernet-phy"; + compatible = "broadcom,BCM5481UA2KMLG"; + reg = <4>; + }; + }; + + serial2: ucc@2400 { + device_type = "serial"; + compatible = "ucc_uart"; + reg = <0x2400 0x200>; + cell-index = <5>; + port-number = <0>; + rx-clock-name = "brg7"; + tx-clock-name = "brg8"; + interrupts = <40>; + interrupt-parent = <&qeic>; + soft-uart; + }; + + serial3: ucc@3400 { + device_type = "serial"; + compatible = "ucc_uart"; + reg = <0x3400 0x200>; + cell-index = <6>; + port-number = <1>; + rx-clock-name = "brg13"; + tx-clock-name = "brg14"; + interrupts = <41>; + interrupt-parent = <&qeic>; + soft-uart; + }; + + qeic: interrupt-controller@80 { + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "fsl,qe-ic"; + interrupt-controller; + reg = <0x80 0x80>; + big-endian; + interrupts = <32 8 33 8>; + interrupt-parent = <&ipic>; + }; + }; + }; + + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xe0005000 0xd8>; + ranges = <0 0 0xff800000 0x0800000 + 1 0 0x60000000 0x0001000 + 2 0 0x70000000 0x4000000>; + + flash@0,0 { + compatible = "intel,PC28F640P30T85", "cfi-flash"; + reg = <0 0 0x800000>; + bank-width = <2>; + device-width = <1>; + }; + + display@2,0 { + device_type = "display"; + compatible = "fujitsu,MB86277", "fujitsu,mint"; + reg = <2 0 0x4000000>; + fujitsu,sh3; + little-endian; + /* filled by u-boot */ + address = <0>; + depth = <0>; + width = <0>; + height = <0>; + linebytes = <0>; + /* linux,opened; - added by uboot */ + }; + }; + + pci0: pci@e0008500 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci"; + reg = <0xe0008500 0x100>; + ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 + 0x42000000 0 0x80000000 0x80000000 0 0x10000000 + 0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>; + interrupts = <66 8>; + interrupt-parent = <&ipic>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */ + 0xa000 0 0 1 &ipic 18 8 + 0xa000 0 0 2 &ipic 19 8 + + /* PCI1 IDSEL 0x15 AD21 */ + 0xa800 0 0 1 &ipic 19 8 + 0xa800 0 0 2 &ipic 20 8 + 0xa800 0 0 3 &ipic 21 8 + 0xa800 0 0 4 &ipic 18 8>; + /* filled by u-boot */ + bus-range = <0 0>; + clock-frequency = <0>; + }; +}; diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts index fea5925..49a38cb 100644 --- a/arch/powerpc/boot/dts/mpc8377_mds.dts +++ b/arch/powerpc/boot/dts/mpc8377_mds.dts @@ -233,41 +233,6 @@ interrupt-parent = <&ipic>; }; - crypto@30000 { - model = "SEC3"; - compatible = "talitos"; - reg = <0x30000 0x10000>; - interrupts = <11 0x8>; - interrupt-parent = <&ipic>; - /* Rev. 3.0 geometry */ - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x000001fe>; - descriptor-types-mask = <0x03ab0ebf>; - }; - - sdhc@2e000 { - model = "eSDHC"; - compatible = "fsl,esdhc"; - reg = <0x2e000 0x1000>; - interrupts = <42 0x8>; - interrupt-parent = <&ipic>; - }; - - sata@18000 { - compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; - reg = <0x18000 0x1000>; - interrupts = <44 0x8>; - interrupt-parent = <&ipic>; - }; - - sata@19000 { - compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; - reg = <0x19000 0x1000>; - interrupts = <45 0x8>; - interrupt-parent = <&ipic>; - }; - dma@82a8 { #address-cells = <1>; #size-cells = <1>; @@ -303,6 +268,41 @@ }; }; + crypto@30000 { + model = "SEC3"; + compatible = "talitos"; + reg = <0x30000 0x10000>; + interrupts = <11 0x8>; + interrupt-parent = <&ipic>; + /* Rev. 3.0 geometry */ + num-channels = <4>; + channel-fifo-len = <24>; + exec-units-mask = <0x000001fe>; + descriptor-types-mask = <0x03ab0ebf>; + }; + + sdhc@2e000 { + model = "eSDHC"; + compatible = "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <42 0x8>; + interrupt-parent = <&ipic>; + }; + + sata@18000 { + compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; + reg = <0x18000 0x1000>; + interrupts = <44 0x8>; + interrupt-parent = <&ipic>; + }; + + sata@19000 { + compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; + reg = <0x19000 0x1000>; + interrupts = <45 0x8>; + interrupt-parent = <&ipic>; + }; + /* IPIC * interrupts cell = <intr #, sense> * sense values match linux IORESOURCE_IRQ_* defines: diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts index f3083c7..1f45387 100644 --- a/arch/powerpc/boot/dts/mpc8377_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts @@ -143,6 +143,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8377-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts index 1d6ea08..99ad49d 100644 --- a/arch/powerpc/boot/dts/mpc8378_mds.dts +++ b/arch/powerpc/boot/dts/mpc8378_mds.dts @@ -157,6 +157,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8378-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts index 0e872a6..44e34d3 100644 --- a/arch/powerpc/boot/dts/mpc8378_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts @@ -143,6 +143,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8378-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts index 6f78a9f..980be81 100644 --- a/arch/powerpc/boot/dts/mpc8379_mds.dts +++ b/arch/powerpc/boot/dts/mpc8379_mds.dts @@ -157,6 +157,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8379-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts index 1eb8def..eeedf58 100644 --- a/arch/powerpc/boot/dts/mpc8379_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts @@ -143,6 +143,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8379-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index 18033ed..f2273a8 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes @@ -83,6 +84,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -165,14 +207,12 @@ interrupt-parent = <&mpic>; }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; }; diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index 663c7c5..21ad71b 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8541-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes @@ -83,6 +84,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -148,14 +190,12 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; cpm@919c0 { diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 6a0d8db..6cf533f 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -41,6 +41,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -65,7 +66,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8544-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes @@ -210,14 +211,28 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; + }; + + msi@41600 { + compatible = "fsl,mpc8544-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; }; }; diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 4811b81..d1fa6bb 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -45,6 +45,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -68,7 +69,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8548-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes @@ -99,6 +100,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -208,14 +250,12 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; }; diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index b025c56..6fc8059 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8555-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes @@ -83,6 +84,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -148,14 +190,12 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; cpm@919c0 { diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index 0cc16ab..ba8159d 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts @@ -64,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes @@ -73,6 +73,47 @@ interrupts = <16 2>; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -134,6 +175,7 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; device_type = "open-pic"; }; diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index a025a8e..be9a289 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -42,6 +42,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -70,7 +71,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8568-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes @@ -106,6 +107,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8568-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8568-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8568-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8568-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -202,14 +244,12 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; par_io@e0100 { diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index 66f27ab..cb06325 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts @@ -42,6 +42,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; PowerPC,8572@1 { @@ -54,6 +55,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -84,7 +86,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,mpc8572-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes @@ -115,6 +117,88 @@ dfsrr; }; + dma@c300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; + reg = <0xc300 0x4>; + ranges = <0x0 0xc100 0x200>; + cell-index = <1>; + dma-channel@0 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <76 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <77 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <78 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <79 2>; + }; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -221,15 +305,29 @@ fsl,has-rstcr; }; + msi@41600 { + compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; }; diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts index fa9b6bb..65a5f64 100644 --- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts +++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts @@ -172,14 +172,28 @@ }; mpic: interrupt-controller@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; + }; + + msi@41600 { + compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; }; global-utilities@e0000 { diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts index 1e4bfe9..ae08761 100644 --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts +++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts @@ -134,6 +134,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -239,14 +280,12 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; global-utilities@e0000 { diff --git a/arch/powerpc/boot/dts/ps3.dts b/arch/powerpc/boot/dts/ps3.dts index 379ded2..96ba5b5 100644 --- a/arch/powerpc/boot/dts/ps3.dts +++ b/arch/powerpc/boot/dts/ps3.dts @@ -18,6 +18,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +/dts-v1/; + / { model = "SonyPS3"; compatible = "sony,ps3"; @@ -34,7 +36,7 @@ memory { device_type = "memory"; - reg = <0 0 0 0>; + reg = <0x00000000 0x00000000 0x00000000 0x00000000>; }; /* @@ -55,14 +57,14 @@ cpu@0 { device_type = "cpu"; - reg = <0>; - ibm,ppc-interrupt-server#s = <0 1>; + reg = <0x00000000>; + ibm,ppc-interrupt-server#s = <0x0 0x1>; clock-frequency = <0>; timebase-frequency = <0>; - i-cache-size = <8000>; - d-cache-size = <8000>; - i-cache-line-size = <80>; - d-cache-line-size = <80>; + i-cache-size = <32768>; + d-cache-size = <32768>; + i-cache-line-size = <128>; + d-cache-line-size = <128>; }; }; }; diff --git a/arch/powerpc/boot/dts/rainier.dts b/arch/powerpc/boot/dts/rainier.dts index 6a8fa70..2afb63a 100644 --- a/arch/powerpc/boot/dts/rainier.dts +++ b/arch/powerpc/boot/dts/rainier.dts @@ -12,12 +12,14 @@ * */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,rainier"; compatible = "amcc,rainier"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -35,13 +37,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440GRx"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -49,14 +51,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440grx","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -66,11 +68,11 @@ compatible = "ibm,uic-440grx","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -78,22 +80,22 @@ compatible = "ibm,uic-440grx","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1c 4 1d 4>; /* cascade */ + interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440grx", "ibm,sdr-440ep"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-440grx", "ibm,cpr-440ep"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -105,80 +107,80 @@ SDRAM0: sdram { compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; DMA0: dma { compatible = "ibm,dma-440grx", "ibm,dma-4xx"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440grx", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 - /*RXEOB*/ 1 &UIC0 b 4 - /*SERR*/ 2 &UIC1 0 4 - /*TXDE*/ 3 &UIC1 1 4 - /*RXDE*/ 4 &UIC1 2 4>; - interrupt-map-mask = <ffffffff>; + interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 + /*RXEOB*/ 0x1 &UIC0 0xb 0x4 + /*SERR*/ 0x2 &UIC1 0x0 0x4 + /*TXDE*/ 0x3 &UIC1 0x1 0x4 + /*RXDE*/ 0x4 &UIC1 0x2 0x4>; + interrupt-map-mask = <0xffffffff>; }; POB0: opb { compatible = "ibm,opb-440grx", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <00000000 1 00000000 80000000 - 80000000 1 80000000 80000000>; + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440grx", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl256n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "Kernel"; - reg = <0 180000>; + reg = <0x00000000 0x00180000>; }; partition@180000 { label = "ramdisk"; - reg = <180000 200000>; + reg = <0x00180000 0x00200000>; }; partition@380000 { label = "file system"; - reg = <380000 3aa0000>; + reg = <0x00380000 0x03aa0000>; }; partition@3e20000 { label = "kozio"; - reg = <3e20000 140000>; + reg = <0x03e20000 0x00140000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; @@ -187,69 +189,69 @@ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600300 8>; - virtual-reg = <ef600300>; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <115200>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600400 8>; - virtual-reg = <ef600400>; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600500 8>; - virtual-reg = <ef600500>; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC1>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600600 8>; - virtual-reg = <ef600600>; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC1>; - interrupts = <4 4>; + interrupts = <0x4 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-440grx", "ibm,iic"; - reg = <ef600700 14>; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-440grx", "ibm,iic"; - reg = <ef600800 14>; + reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-440grx", "ibm,zmii"; - reg = <ef600d00 c>; + reg = <0xef600d00 0x0000000c>; }; RGMII0: emac-rgmii@ef601000 { compatible = "ibm,rgmii-440grx", "ibm,rgmii"; - reg = <ef601000 8>; + reg = <0xef601000 0x00000008>; has-mdio; }; @@ -257,23 +259,23 @@ device_type = "network"; compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC0 18 4 - /*Wake*/ 1 &UIC1 1d 4>; - reg = <ef600e00 70>; + interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4 + /*Wake*/ 0x1 &UIC1 0x1d 0x4>; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <0>; rgmii-device = <&RGMII0>; @@ -286,23 +288,23 @@ device_type = "network"; compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4"; interrupt-parent = <&EMAC1>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC0 19 4 - /*Wake*/ 1 &UIC1 1f 4>; - reg = <ef600f00 70>; + interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4 + /*Wake*/ 0x1 &UIC1 0x1f 0x4>; + reg = <0xef600f00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <1>; rgmii-device = <&RGMII0>; @@ -319,24 +321,25 @@ #address-cells = <3>; compatible = "ibm,plb440grx-pci", "ibm,plb-pci"; primary; - reg = <1 eec00000 8 /* Config space access */ - 1 eed00000 4 /* IACK */ - 1 eed00000 4 /* Special cycle */ - 1 ef400000 40>; /* Internal registers */ + reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */ + 0x00000001 0xeed00000 0x00000004 /* IACK */ + 0x00000001 0xeed00000 0x00000004 /* Special cycle */ + 0x00000001 0xef400000 0x00000040>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second * IO range but we don't use it for now */ - ranges = <02000000 0 80000000 1 80000000 0 10000000 - 01000000 0 00000000 1 e8000000 0 00100000>; + ranges = <0x02000000 0x0 0x80000000 0x1 0x80000000 0x0 0x40000000 + 0x01000000 0x0 0x00000000 0x1 0xe8000000 0x0 0x00010000 + 0x01000000 0x0 0x00000000 0x1 0xe8800000 0x0 0x03800000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* All PCI interrupts are routed to IRQ 67 */ - interrupt-map-mask = <0000 0 0 0>; - interrupt-map = < 0000 0 0 0 &UIC2 3 8 >; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >; }; }; diff --git a/arch/powerpc/boot/dts/sam440ep.dts b/arch/powerpc/boot/dts/sam440ep.dts new file mode 100644 index 0000000..f0663be --- /dev/null +++ b/arch/powerpc/boot/dts/sam440ep.dts @@ -0,0 +1,293 @@ +/* + * Device Tree Source for ACube Sam440ep based off bamboo.dts code + * original copyrights below + * + * Copyright (c) 2006, 2007 IBM Corp. + * Josh Boyer <jwboyer@linux.vnet.ibm.com> + * + * Modified from bamboo.dts for sam440ep: + * Copyright 2008 Giuseppe Coviello <gicoviello@gmail.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "acube,sam440ep"; + compatible = "acube,sam440ep"; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + serial0 = &UART0; + serial1 = &UART1; + serial2 = &UART2; + serial3 = &UART3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,440EP"; + reg = <0>; + clock-frequency = <0>; /* Filled in by zImage */ + timebase-frequency = <0>; /* Filled in by zImage */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0 0>; /* Filled in by zImage */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-440ep","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0x0c0 9>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-440ep","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0x0d0 9>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x1e 4 0x1f 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-440ep"; + dcr-reg = <0x00e 2>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-440ep"; + dcr-reg = <0x00c 2>; + }; + + plb { + compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by zImage */ + + SDRAM0: sdram { + compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; + dcr-reg = <0x010 2>; + }; + + DMA0: dma { + compatible = "ibm,dma-440ep", "ibm,dma-440gp"; + dcr-reg = <0x100 0x027>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; + dcr-reg = <0x180 0x062>; + num-tx-chans = <4>; + num-rx-chans = <2>; + interrupt-parent = <&MAL0>; + interrupts = <0 1 2 3 4>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*TXEOB*/ 0 &UIC0 10 4 + /*RXEOB*/ 1 &UIC0 11 4 + /*SERR*/ 2 &UIC1 0 4 + /*TXDE*/ 3 &UIC1 1 4 + /*RXDE*/ 4 &UIC1 2 4>; + }; + + POB0: opb { + compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + /* Bamboo is oddball in the 44x world and doesn't use the ERPN + * bits. + */ + ranges = <0x00000000 0 0x00000000 0x80000000 + 0x80000000 0 0x80000000 0x80000000>; + interrupt-parent = <&UIC1>; + interrupts = <7 4>; + clock-frequency = <0>; /* Filled in by zImage */ + + EBC0: ebc { + compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; + dcr-reg = <0x012 2>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by zImage */ + interrupts = <5 1>; + interrupt-parent = <&UIC1>; + }; + + UART0: serial@ef600300 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xef600300 8>; + virtual-reg = <0xef600300>; + clock-frequency = <0>; /* Filled in by zImage */ + current-speed = <0x1c200>; + interrupt-parent = <&UIC0>; + interrupts = <0 4>; + }; + + UART1: serial@ef600400 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xef600400 8>; + virtual-reg = <0xef600400>; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <1 4>; + }; + + UART2: serial@ef600500 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xef600500 8>; + virtual-reg = <0xef600500>; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <3 4>; + }; + + UART3: serial@ef600600 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xef600600 8>; + virtual-reg = <0xef600600>; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <4 4>; + }; + + IIC0: i2c@ef600700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; + index = <0>; + reg = <0xef600700 0x14>; + interrupt-parent = <&UIC0>; + interrupts = <2 4>; + rtc@68 { + compatible = "stm,m41t80"; + reg = <0x68>; + }; + }; + + IIC1: i2c@ef600800 { + compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; + index = <5>; + reg = <0xef600800 0x14>; + interrupt-parent = <&UIC0>; + interrupts = <7 4>; + }; + + ZMII0: emac-zmii@ef600d00 { + compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; + reg = <0xef600d00 0xc>; + }; + + EMAC0: ethernet@ef600e00 { + linux,network-index = <0>; + device_type = "network"; + compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; + interrupt-parent = <&UIC1>; + interrupts = <0x1c 4 0x1d 4>; + reg = <0xef600e00 0x70>; + local-mac-address = [000000000000]; + mal-device = <&MAL0>; + mal-tx-channel = <0 1>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <0x5dc>; + rx-fifo-size = <0x1000>; + tx-fifo-size = <0x800>; + phy-mode = "rmii"; + phy-map = <00000000>; + zmii-device = <&ZMII0>; + zmii-channel = <0>; + }; + + EMAC1: ethernet@ef600f00 { + linux,network-index = <1>; + device_type = "network"; + compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; + interrupt-parent = <&UIC1>; + interrupts = <0x1e 4 0x1f 4>; + reg = <0xef600f00 0x70>; + local-mac-address = [000000000000]; + mal-device = <&MAL0>; + mal-tx-channel = <2 3>; + mal-rx-channel = <1>; + cell-index = <1>; + max-frame-size = <0x5dc>; + rx-fifo-size = <0x1000>; + tx-fifo-size = <0x800>; + phy-mode = "rmii"; + phy-map = <00000000>; + zmii-device = <&ZMII0>; + zmii-channel = <1>; + }; + usb@ef601000 { + compatible = "ohci-be"; + reg = <0xef601000 0x80>; + interrupts = <8 4 9 4>; + interrupt-parent = <&UIC1>; + }; + }; + + PCI0: pci@ec000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; + primary; + reg = <0 0xeec00000 8 /* Config space access */ + 0 0xeed00000 4 /* IACK */ + 0 0xeed00000 4 /* Special cycle */ + 0 0xef400000 0x40>; /* Internal registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed. Chip supports a second + * IO range but we don't use it for now + */ + ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000 + 0x01000000 0 0x00000000 0 0xe8000000 0 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0 0 0 0 0 0x80000000>; + }; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@ef600300"; + }; +}; diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts index 3839d4b..5b76bb2 100644 --- a/arch/powerpc/boot/dts/sbc8349.dts +++ b/arch/powerpc/boot/dts/sbc8349.dts @@ -95,6 +95,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + /* phy type (ULPI or SERIAL) are only types supported for MPH */ /* port = 0 or 1 */ usb@22000 { diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts index 22d9671..21cbacb 100644 --- a/arch/powerpc/boot/dts/sbc8548.dts +++ b/arch/powerpc/boot/dts/sbc8548.dts @@ -44,6 +44,7 @@ timebase-frequency = <0>; // From uboot bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -161,7 +162,7 @@ interrupts = <0x12 0x2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8548-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes @@ -192,6 +193,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -265,12 +307,10 @@ mpic: pic@40000 { interrupt-controller; #address-cells = <0>; - #size-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; }; diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts index 0476802..db3632e 100644 --- a/arch/powerpc/boot/dts/sbc8560.dts +++ b/arch/powerpc/boot/dts/sbc8560.dts @@ -43,6 +43,7 @@ timebase-frequency = <0>; // From uboot bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -66,7 +67,7 @@ interrupts = <0x12 0x2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8560-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes @@ -97,6 +98,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -155,8 +197,8 @@ mpic: pic@40000 { interrupt-controller; #address-cells = <0>; - #size-cells = <0>; #interrupt-cells = <2>; + compatible = "chrp,open-pic"; reg = <0x40000 0x40000>; device_type = "open-pic"; }; diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts index 3eebeec..9652456 100644 --- a/arch/powerpc/boot/dts/sbc8641d.dts +++ b/arch/powerpc/boot/dts/sbc8641d.dts @@ -151,6 +151,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts index 72d6756..149dabc 100644 --- a/arch/powerpc/boot/dts/sequoia.dts +++ b/arch/powerpc/boot/dts/sequoia.dts @@ -12,12 +12,14 @@ * */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,sequoia"; compatible = "amcc,sequoia"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -35,13 +37,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440EPx"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -49,14 +51,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440epx","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -66,11 +68,11 @@ compatible = "ibm,uic-440epx","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -78,22 +80,22 @@ compatible = "ibm,uic-440epx","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1c 4 1d 4>; /* cascade */ + interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440epx", "ibm,sdr-440ep"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-440epx", "ibm,cpr-440ep"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -105,44 +107,44 @@ SDRAM0: sdram { compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; DMA0: dma { compatible = "ibm,dma-440epx", "ibm,dma-4xx"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440epx", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 - /*RXEOB*/ 1 &UIC0 b 4 - /*SERR*/ 2 &UIC1 0 4 - /*TXDE*/ 3 &UIC1 1 4 - /*RXDE*/ 4 &UIC1 2 4>; - interrupt-map-mask = <ffffffff>; + interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 + /*RXEOB*/ 0x1 &UIC0 0xb 0x4 + /*SERR*/ 0x2 &UIC1 0x0 0x4 + /*TXDE*/ 0x3 &UIC1 0x1 0x4 + /*RXDE*/ 0x4 &UIC1 0x2 0x4>; + interrupt-map-mask = <0xffffffff>; }; USB1: usb@e0000400 { compatible = "ohci-be"; - reg = <0 e0000400 60>; + reg = <0x00000000 0xe0000400 0x00000060>; interrupt-parent = <&UIC0>; - interrupts = <15 8>; + interrupts = <0x15 0x8>; }; USB0: ehci@e0000300 { compatible = "ibm,usb-ehci-440epx", "usb-ehci"; interrupt-parent = <&UIC0>; - interrupts = <1a 4>; - reg = <0 e0000300 90 0 e0000390 70>; + interrupts = <0x1a 0x4>; + reg = <0x00000000 0xe0000300 0x00000090 0x00000000 0xe0000390 0x00000070>; big-endian; }; @@ -150,50 +152,50 @@ compatible = "ibm,opb-440epx", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <00000000 1 00000000 80000000 - 80000000 1 80000000 80000000>; + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440epx", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl256n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "Kernel"; - reg = <0 180000>; + reg = <0x00000000 0x00180000>; }; partition@180000 { label = "ramdisk"; - reg = <180000 200000>; + reg = <0x00180000 0x00200000>; }; partition@380000 { label = "file system"; - reg = <380000 3aa0000>; + reg = <0x00380000 0x03aa0000>; }; partition@3e20000 { label = "kozio"; - reg = <3e20000 140000>; + reg = <0x03e20000 0x00140000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; @@ -202,69 +204,69 @@ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600300 8>; - virtual-reg = <ef600300>; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <115200>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600400 8>; - virtual-reg = <ef600400>; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600500 8>; - virtual-reg = <ef600500>; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC1>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600600 8>; - virtual-reg = <ef600600>; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC1>; - interrupts = <4 4>; + interrupts = <0x4 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-440epx", "ibm,iic"; - reg = <ef600700 14>; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-440epx", "ibm,iic"; - reg = <ef600800 14>; + reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-440epx", "ibm,zmii"; - reg = <ef600d00 c>; + reg = <0xef600d00 0x0000000c>; }; RGMII0: emac-rgmii@ef601000 { compatible = "ibm,rgmii-440epx", "ibm,rgmii"; - reg = <ef601000 8>; + reg = <0xef601000 0x00000008>; has-mdio; }; @@ -272,23 +274,23 @@ device_type = "network"; compatible = "ibm,emac-440epx", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC0 18 4 - /*Wake*/ 1 &UIC1 1d 4>; - reg = <ef600e00 70>; + interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4 + /*Wake*/ 0x1 &UIC1 0x1d 0x4>; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <0>; rgmii-device = <&RGMII0>; @@ -301,23 +303,23 @@ device_type = "network"; compatible = "ibm,emac-440epx", "ibm,emac4"; interrupt-parent = <&EMAC1>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*Status*/ 0 &UIC0 19 4 - /*Wake*/ 1 &UIC1 1f 4>; - reg = <ef600f00 70>; + interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4 + /*Wake*/ 0x1 &UIC1 0x1f 0x4>; + reg = <0xef600f00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <1>; rgmii-device = <&RGMII0>; @@ -334,10 +336,10 @@ #address-cells = <3>; compatible = "ibm,plb440epx-pci", "ibm,plb-pci"; primary; - reg = <1 eec00000 8 /* Config space access */ - 1 eed00000 4 /* IACK */ - 1 eed00000 4 /* Special cycle */ - 1 ef400000 40>; /* Internal registers */ + reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */ + 0x00000001 0xeed00000 0x00000004 /* IACK */ + 0x00000001 0xeed00000 0x00000004 /* Special cycle */ + 0x00000001 0xef400000 0x00000040>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second @@ -347,16 +349,16 @@ * I/O 1 E800 0000 1 E800 FFFF 64KB * I/O 1 E880 0000 1 EBFF FFFF 56MB */ - ranges = <02000000 0 80000000 1 80000000 0 40000000 - 01000000 0 00000000 1 e8000000 0 00010000 - 01000000 0 00000000 1 e8800000 0 03800000>; + ranges = <0x02000000 0x00000000 0x80000000 0x00000001 0x80000000 0x00000000 0x40000000 + 0x01000000 0x00000000 0x00000000 0x00000001 0xe8000000 0x00000000 0x00010000 + 0x01000000 0x00000000 0x00000000 0x00000001 0xe8800000 0x00000000 0x03800000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* All PCI interrupts are routed to IRQ 67 */ - interrupt-map-mask = <0000 0 0 0>; - interrupt-map = < 0000 0 0 0 &UIC2 3 8 >; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >; }; }; diff --git a/arch/powerpc/boot/dts/storcenter.dts b/arch/powerpc/boot/dts/storcenter.dts index 5893816..eab680c 100644 --- a/arch/powerpc/boot/dts/storcenter.dts +++ b/arch/powerpc/boot/dts/storcenter.dts @@ -95,6 +95,7 @@ mpic: interrupt-controller@40000 { #interrupt-cells = <2>; + #address-cells = <0>; device_type = "open-pic"; compatible = "chrp,open-pic"; interrupt-controller; diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts index f81fd7f..fcd1db6 100644 --- a/arch/powerpc/boot/dts/stx_gp3_8560.dts +++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts @@ -38,6 +38,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -62,7 +63,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; @@ -82,6 +83,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -131,6 +173,7 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; device_type = "open-pic"; }; diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts index e808e1c..d4867de 100644 --- a/arch/powerpc/boot/dts/taishan.dts +++ b/arch/powerpc/boot/dts/taishan.dts @@ -10,12 +10,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,taishan"; compatible = "amcc,taishan"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC2; @@ -31,13 +33,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440GX"; - reg = <0>; - clock-frequency = <2FAF0800>; // 800MHz + reg = <0x00000000>; + clock-frequency = <800000000>; // 800MHz timebase-frequency = <0>; // Filled in by zImage - i-cache-line-size = <32>; - d-cache-line-size = <32>; - i-cache-size = <8000>; /* 32 kB */ - d-cache-size = <8000>; /* 32 kB */ + i-cache-line-size = <50>; + d-cache-line-size = <50>; + i-cache-size = <32768>; /* 32 kB */ + d-cache-size = <32768>; /* 32 kB */ dcr-controller; dcr-access-method = "native"; }; @@ -45,7 +47,7 @@ memory { device_type = "memory"; - reg = <0 0 0>; // Filled in by zImage + reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage }; @@ -53,7 +55,7 @@ compatible = "ibm,uic-440gx", "ibm,uic"; interrupt-controller; cell-index = <3>; - dcr-reg = <200 009>; + dcr-reg = <0x200 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -64,11 +66,11 @@ compatible = "ibm,uic-440gx", "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <01 4 00 4>; /* cascade - first non-critical */ + interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */ interrupt-parent = <&UICB0>; }; @@ -77,11 +79,11 @@ compatible = "ibm,uic-440gx", "ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <03 4 02 4>; /* cascade */ + interrupts = <0x3 0x4 0x2 0x4>; /* cascade */ interrupt-parent = <&UICB0>; }; @@ -89,29 +91,29 @@ compatible = "ibm,uic-440gx", "ibm,uic"; interrupt-controller; cell-index = <2>; /* was 1 */ - dcr-reg = <210 009>; + dcr-reg = <0x210 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <05 4 04 4>; /* cascade */ + interrupts = <0x5 0x4 0x4 0x4>; /* cascade */ interrupt-parent = <&UICB0>; }; CPC0: cpc { compatible = "ibm,cpc-440gp"; - dcr-reg = <0b0 003 0e0 010>; + dcr-reg = <0x0b0 0x003 0x0e0 0x010>; // FIXME: anything else? }; L2C0: l2c { compatible = "ibm,l2-cache-440gx", "ibm,l2-cache"; - dcr-reg = <20 8 /* Internal SRAM DCR's */ - 30 8>; /* L2 cache DCR's */ - cache-line-size = <20>; /* 32 bytes */ - cache-size = <40000>; /* L2, 256K */ + dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ + 0x030 0x008>; /* L2 cache DCR's */ + cache-line-size = <32>; /* 32 bytes */ + cache-size = <262144>; /* L2, 256K */ interrupt-parent = <&UIC2>; - interrupts = <17 1>; + interrupts = <0x17 0x1>; }; plb { @@ -119,41 +121,41 @@ #address-cells = <2>; #size-cells = <1>; ranges; - clock-frequency = <9896800>; // 160MHz + clock-frequency = <160000000>; // 160MHz SDRAM0: memory-controller { compatible = "ibm,sdram-440gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; // FIXME: anything else? }; SRAM0: sram { compatible = "ibm,sram-440gp"; - dcr-reg = <020 8 00a 1>; + dcr-reg = <0x020 0x008 0x00a 0x001>; }; DMA0: dma { // FIXME: ??? compatible = "ibm,dma-440gp"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440gx", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; num-rx-chans = <4>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 - /*RXEOB*/ 1 &UIC0 b 4 - /*SERR*/ 2 &UIC1 0 4 - /*TXDE*/ 3 &UIC1 1 4 - /*RXDE*/ 4 &UIC1 2 4>; - interrupt-map-mask = <ffffffff>; + interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 + /*RXEOB*/ 0x1 &UIC0 0xb 0x4 + /*SERR*/ 0x2 &UIC1 0x0 0x4 + /*TXDE*/ 0x3 &UIC1 0x1 0x4 + /*RXDE*/ 0x4 &UIC1 0x2 0x4>; + interrupt-map-mask = <0xffffffff>; }; POB0: opb { @@ -162,29 +164,56 @@ #size-cells = <1>; /* Wish there was a nicer way of specifying a full 32-bit range */ - ranges = <00000000 1 00000000 80000000 - 80000000 1 80000000 80000000>; - dcr-reg = <090 00b>; + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; + dcr-reg = <0x090 0x00b>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; - clock-frequency = <4C4B400>; // 80MHz + interrupts = <0x7 0x4>; + clock-frequency = <80000000>; // 80MHz EBC0: ebc { compatible = "ibm,ebc-440gx", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; - clock-frequency = <4C4B400>; // 80MHz + clock-frequency = <80000000>; // 80MHz /* ranges property is supplied by zImage * based on firmware's configuration of the * EBC bridge */ - interrupts = <5 4>; + interrupts = <0x5 0x4>; interrupt-parent = <&UIC1>; - /* TODO: Add other EBC devices */ + nor_flash@0,0 { + compatible = "cfi-flash"; + bank-width = <4>; + device-width = <2>; + reg = <0x0 0x0 0x4000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x0 0x180000>; + }; + partition@180000 { + label = "root"; + reg = <0x180000 0x200000>; + }; + partition@380000 { + label = "user"; + reg = <0x380000 0x3bc0000>; + }; + partition@3f40000 { + label = "env"; + reg = <0x3f40000 0x80000>; + }; + partition@3fc0000 { + label = "u-boot"; + reg = <0x3fc0000 0x40000>; + }; + }; }; @@ -192,103 +221,103 @@ UART0: serial@40000200 { device_type = "serial"; compatible = "ns16550"; - reg = <40000200 8>; - virtual-reg = <e0000200>; - clock-frequency = <A8C000>; - current-speed = <1C200>; /* 115200 */ + reg = <0x40000200 0x00000008>; + virtual-reg = <0xe0000200>; + clock-frequency = <11059200>; + current-speed = <115200>; /* 115200 */ interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@40000300 { device_type = "serial"; compatible = "ns16550"; - reg = <40000300 8>; - virtual-reg = <e0000300>; - clock-frequency = <A8C000>; - current-speed = <1C200>; /* 115200 */ + reg = <0x40000300 0x00000008>; + virtual-reg = <0xe0000300>; + clock-frequency = <11059200>; + current-speed = <115200>; /* 115200 */ interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC0: i2c@40000400 { /* FIXME */ compatible = "ibm,iic-440gp", "ibm,iic"; - reg = <40000400 14>; + reg = <0x40000400 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@40000500 { /* FIXME */ compatible = "ibm,iic-440gp", "ibm,iic"; - reg = <40000500 14>; + reg = <0x40000500 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; GPIO0: gpio@40000700 { /* FIXME */ compatible = "ibm,gpio-440gp"; - reg = <40000700 20>; + reg = <0x40000700 0x00000020>; }; ZMII0: emac-zmii@40000780 { compatible = "ibm,zmii-440gx", "ibm,zmii"; - reg = <40000780 c>; + reg = <0x40000780 0x0000000c>; }; RGMII0: emac-rgmii@40000790 { compatible = "ibm,rgmii"; - reg = <40000790 8>; + reg = <0x40000790 0x00000008>; }; TAH0: emac-tah@40000b50 { compatible = "ibm,tah-440gx", "ibm,tah"; - reg = <40000b50 30>; + reg = <0x40000b50 0x00000030>; }; TAH1: emac-tah@40000d50 { compatible = "ibm,tah-440gx", "ibm,tah"; - reg = <40000d50 30>; + reg = <0x40000d50 0x00000030>; }; EMAC0: ethernet@40000800 { - unused = <1>; + unused = <0x1>; device_type = "network"; compatible = "ibm,emac-440gx", "ibm,emac4"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = <40000800 70>; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0x40000800 0x00000070>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000001>; + phy-map = <0x00000001>; zmii-device = <&ZMII0>; zmii-channel = <0>; }; EMAC1: ethernet@40000900 { - unused = <1>; + unused = <0x1>; device_type = "network"; compatible = "ibm,emac-440gx", "ibm,emac4"; interrupt-parent = <&UIC1>; - interrupts = <1e 4 1f 4>; - reg = <40000900 70>; + interrupts = <0x1e 0x4 0x1f 0x4>; + reg = <0x40000900 0x00000070>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000001>; + phy-map = <0x00000001>; zmii-device = <&ZMII0>; zmii-channel = <1>; }; @@ -297,18 +326,18 @@ device_type = "network"; compatible = "ibm,emac-440gx", "ibm,emac4"; interrupt-parent = <&UIC2>; - interrupts = <0 4 1 4>; - reg = <40000c00 70>; + interrupts = <0x0 0x4 0x1 0x4>; + reg = <0x40000c00 0x00000070>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <2>; mal-rx-channel = <2>; cell-index = <2>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000001>; + phy-map = <0x00000001>; rgmii-device = <&RGMII0>; rgmii-channel = <0>; zmii-device = <&ZMII0>; @@ -321,18 +350,18 @@ device_type = "network"; compatible = "ibm,emac-440gx", "ibm,emac4"; interrupt-parent = <&UIC2>; - interrupts = <2 4 3 4>; - reg = <40000e00 70>; + interrupts = <0x2 0x4 0x3 0x4>; + reg = <0x40000e00 0x00000070>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <3>; mal-rx-channel = <3>; cell-index = <3>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000003>; + phy-map = <0x00000003>; rgmii-device = <&RGMII0>; rgmii-channel = <1>; zmii-device = <&ZMII0>; @@ -344,9 +373,9 @@ GPT0: gpt@40000a00 { /* FIXME */ - reg = <40000a00 d4>; + reg = <0x40000a00 0x000000d4>; interrupt-parent = <&UIC0>; - interrupts = <12 4 13 4 14 4 15 4 16 4>; + interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>; }; }; @@ -360,34 +389,34 @@ primary; large-inbound-windows; enable-msi-hole; - reg = <2 0ec00000 8 /* Config space access */ - 0 0 0 /* no IACK cycles */ - 2 0ed00000 4 /* Special cycles */ - 2 0ec80000 100 /* Internal registers */ - 2 0ec80100 fc>; /* Internal messaging registers */ + reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x00000002 0x0ed00000 0x00000004 /* Special cycles */ + 0x00000002 0x0ec80000 0x00000100 /* Internal registers */ + 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 00000003 80000000 0 80000000 - 01000000 0 00000000 00000002 08000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 1 */ - 0800 0 0 1 &UIC0 17 8 - 0800 0 0 2 &UIC0 18 8 - 0800 0 0 3 &UIC0 19 8 - 0800 0 0 4 &UIC0 1a 8 + 0x800 0x0 0x0 0x1 &UIC0 0x17 0x8 + 0x800 0x0 0x0 0x2 &UIC0 0x18 0x8 + 0x800 0x0 0x0 0x3 &UIC0 0x19 0x8 + 0x800 0x0 0x0 0x4 &UIC0 0x1a 0x8 /* IDSEL 2 */ - 1000 0 0 1 &UIC0 18 8 - 1000 0 0 2 &UIC0 19 8 - 1000 0 0 3 &UIC0 1a 8 - 1000 0 0 4 &UIC0 17 8 + 0x1000 0x0 0x0 0x1 &UIC0 0x18 0x8 + 0x1000 0x0 0x0 0x2 &UIC0 0x19 0x8 + 0x1000 0x0 0x0 0x3 &UIC0 0x1a 0x8 + 0x1000 0x0 0x0 0x4 &UIC0 0x17 0x8 >; }; }; diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts index 1addb3a..e1d260b 100644 --- a/arch/powerpc/boot/dts/tqm8540.dts +++ b/arch/powerpc/boot/dts/tqm8540.dts @@ -12,8 +12,8 @@ /dts-v1/; / { - model = "tqm,8540"; - compatible = "tqm,8540", "tqm,85xx"; + model = "tqc,tqm8540"; + compatible = "tqc,tqm8540"; #address-cells = <1>; #size-cells = <1>; @@ -40,6 +40,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -64,7 +65,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; @@ -89,6 +90,47 @@ }; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -177,6 +219,7 @@ #interrupt-cells = <2>; reg = <0x40000 0x40000>; device_type = "open-pic"; + compatible = "chrp,open-pic"; }; }; diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts index 9e01093..d083a64 100644 --- a/arch/powerpc/boot/dts/tqm8541.dts +++ b/arch/powerpc/boot/dts/tqm8541.dts @@ -12,8 +12,8 @@ /dts-v1/; / { - model = "tqm,8541"; - compatible = "tqm,8541", "tqm,85xx"; + model = "tqc,tqm8541"; + compatible = "tqc,tqm8541"; #address-cells = <1>; #size-cells = <1>; @@ -39,6 +39,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; @@ -88,6 +89,47 @@ }; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -164,6 +206,7 @@ #interrupt-cells = <2>; reg = <0x40000 0x40000>; device_type = "open-pic"; + compatible = "chrp,open-pic"; }; cpm@919c0 { diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts new file mode 100644 index 0000000..64d2d5b --- /dev/null +++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts @@ -0,0 +1,406 @@ +/* + * TQM8548 Device Tree Source + * + * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2008 Wolfgang Grandegger <wg@denx.de> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "tqc,tqm8548"; + compatible = "tqc,tqm8548"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8548@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000>; // Filled in by U-Boot + }; + + soc8548@a0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <0x0 0xa0000000 0x100000>; + reg = <0xa0000000 0x1000>; // CCSRBAR + bus-frequency = <0>; + + memory-controller@2000 { + compatible = "fsl,mpc8548-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8548-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x80000>; // L2, 512K + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; + + phy1: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <1>; + device_type = "ethernet-phy"; + }; + phy2: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <2>; + device_type = "ethernet-phy"; + }; + phy3: ethernet-phy@3 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <3>; + device_type = "ethernet-phy"; + }; + phy4: ethernet-phy@4 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <4>; + device_type = "ethernet-phy"; + }; + phy5: ethernet-phy@5 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <5>; + device_type = "ethernet-phy"; + }; + }; + + enet0: ethernet@24000 { + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy2>; + }; + + enet1: ethernet@25000 { + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy1>; + }; + + enet2: ethernet@26000 { + cell-index = <2>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy3>; + }; + + enet3: ethernet@27000 { + cell-index = <3>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 38 2 39 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy4>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? + current-speed = <115200>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? + current-speed = <115200>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { // global utilities reg + compatible = "fsl,mpc8548-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + }; + + localbus@a0005000 { + compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xa0005000 0x100>; // BRx, ORx, etc. + + ranges = < + 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 + 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 + 2 0x0 0xa3000000 0x00008000 // CAN (2 x i82527) + 3 0x0 0xa3010000 0x00008000 // NAND FLASH + + >; + + flash@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <1 0x0 0x8000000>; + bank-width = <4>; + device-width = <1>; + + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00200000>; + }; + partition@200000 { + label = "root"; + reg = <0x00200000 0x00300000>; + }; + partition@500000 { + label = "user"; + reg = <0x00500000 0x07a00000>; + }; + partition@7f00000 { + label = "env1"; + reg = <0x07f00000 0x00040000>; + }; + partition@7f40000 { + label = "env2"; + reg = <0x07f40000 0x00040000>; + }; + partition@7f80000 { + label = "u-boot"; + reg = <0x07f80000 0x00080000>; + read-only; + }; + }; + + /* Note: CAN support needs be enabled in U-Boot */ + can0@2,0 { + compatible = "intel,82527"; // Bosch CC770 + reg = <2 0x0 0x100>; + interrupts = <4 0>; + interrupt-parent = <&mpic>; + }; + + can1@2,100 { + compatible = "intel,82527"; // Bosch CC770 + reg = <2 0x100 0x100>; + interrupts = <4 0>; + interrupt-parent = <&mpic>; + }; + + /* Note: NAND support needs to be enabled in U-Boot */ + upm@3,0 { + #address-cells = <0>; + #size-cells = <0>; + compatible = "fsl,upm-nand"; + reg = <3 0x0 0x800>; + fsl,upm-addr-offset = <0x10>; + fsl,upm-cmd-offset = <0x08>; + chip-delay = <25>; // in micro-seconds + + nand@0 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "fs"; + reg = <0x00000000 0x01000000>; + }; + }; + }; + }; + + pci0: pci@a0008000 { + cell-index = <0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; + device_type = "pci"; + reg = <0xa0008000 0x1000>; + clock-frequency = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 28 */ + 0xe000 0 0 1 &mpic 2 1 + 0xe000 0 0 2 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <24 2>; + bus-range = <0 0>; + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 + 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>; + }; + + pci1: pcie@a000a000 { + cell-index = <2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 (PEX) */ + 0x00000 0 0 1 &mpic 0 1 + 0x00000 0 0 2 &mpic 1 1 + 0x00000 0 0 3 &mpic 2 1 + 0x00000 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <26 2>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>; + clock-frequency = <33333333>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xa000a000 0x1000>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0 0xb0000000 0x02000000 0 + 0xb0000000 0 0x10000000 + 0x01000000 0 0x00000000 0x01000000 0 + 0x00000000 0 0x08000000>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts new file mode 100644 index 0000000..13cd728 --- /dev/null +++ b/arch/powerpc/boot/dts/tqm8548.dts @@ -0,0 +1,406 @@ +/* + * TQM8548 Device Tree Source + * + * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2008 Wolfgang Grandegger <wg@denx.de> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "tqc,tqm8548"; + compatible = "tqc,tqm8548"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8548@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000>; // Filled in by U-Boot + }; + + soc8548@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <0x0 0xe0000000 0x100000>; + reg = <0xe0000000 0x1000>; // CCSRBAR + bus-frequency = <0>; + + memory-controller@2000 { + compatible = "fsl,mpc8548-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8548-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x80000>; // L2, 512K + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; + + phy1: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <1>; + device_type = "ethernet-phy"; + }; + phy2: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <2>; + device_type = "ethernet-phy"; + }; + phy3: ethernet-phy@3 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <3>; + device_type = "ethernet-phy"; + }; + phy4: ethernet-phy@4 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <4>; + device_type = "ethernet-phy"; + }; + phy5: ethernet-phy@5 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <5>; + device_type = "ethernet-phy"; + }; + }; + + enet0: ethernet@24000 { + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy2>; + }; + + enet1: ethernet@25000 { + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy1>; + }; + + enet2: ethernet@26000 { + cell-index = <2>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy3>; + }; + + enet3: ethernet@27000 { + cell-index = <3>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 38 2 39 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy4>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? + current-speed = <115200>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? + current-speed = <115200>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { // global utilities reg + compatible = "fsl,mpc8548-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + }; + + localbus@e0005000 { + compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xe0005000 0x100>; // BRx, ORx, etc. + + ranges = < + 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 + 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 + 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527) + 3 0x0 0xe3010000 0x00008000 // NAND FLASH + + >; + + flash@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <1 0x0 0x8000000>; + bank-width = <4>; + device-width = <1>; + + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00200000>; + }; + partition@200000 { + label = "root"; + reg = <0x00200000 0x00300000>; + }; + partition@500000 { + label = "user"; + reg = <0x00500000 0x07a00000>; + }; + partition@7f00000 { + label = "env1"; + reg = <0x07f00000 0x00040000>; + }; + partition@7f40000 { + label = "env2"; + reg = <0x07f40000 0x00040000>; + }; + partition@7f80000 { + label = "u-boot"; + reg = <0x07f80000 0x00080000>; + read-only; + }; + }; + + /* Note: CAN support needs be enabled in U-Boot */ + can0@2,0 { + compatible = "intel,82527"; // Bosch CC770 + reg = <2 0x0 0x100>; + interrupts = <4 0>; + interrupt-parent = <&mpic>; + }; + + can1@2,100 { + compatible = "intel,82527"; // Bosch CC770 + reg = <2 0x100 0x100>; + interrupts = <4 0>; + interrupt-parent = <&mpic>; + }; + + /* Note: NAND support needs to be enabled in U-Boot */ + upm@3,0 { + #address-cells = <0>; + #size-cells = <0>; + compatible = "fsl,upm-nand"; + reg = <3 0x0 0x800>; + fsl,upm-addr-offset = <0x10>; + fsl,upm-cmd-offset = <0x08>; + chip-delay = <25>; // in micro-seconds + + nand@0 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "fs"; + reg = <0x00000000 0x01000000>; + }; + }; + }; + }; + + pci0: pci@e0008000 { + cell-index = <0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; + device_type = "pci"; + reg = <0xe0008000 0x1000>; + clock-frequency = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 28 */ + 0xe000 0 0 1 &mpic 2 1 + 0xe000 0 0 2 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <24 2>; + bus-range = <0 0>; + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 + 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; + }; + + pci1: pcie@e000a000 { + cell-index = <2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 (PEX) */ + 0x00000 0 0 1 &mpic 0 1 + 0x00000 0 0 2 &mpic 1 1 + 0x00000 0 0 3 &mpic 2 1 + 0x00000 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <26 2>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0 0x00000000 0xef000000 0 0x08000000>; + clock-frequency = <33333333>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xe000a000 0x1000>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0 0xc0000000 0x02000000 0 + 0xc0000000 0 0x20000000 + 0x01000000 0 0x00000000 0x01000000 0 + 0x00000000 0 0x08000000>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts index a20eb06..96b0b94 100644 --- a/arch/powerpc/boot/dts/tqm8555.dts +++ b/arch/powerpc/boot/dts/tqm8555.dts @@ -12,8 +12,8 @@ /dts-v1/; / { - model = "tqm,8555"; - compatible = "tqm,8555", "tqm,85xx"; + model = "tqc,tqm8555"; + compatible = "tqc,tqm8555"; #address-cells = <1>; #size-cells = <1>; @@ -39,6 +39,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; @@ -88,6 +89,47 @@ }; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -164,6 +206,7 @@ #interrupt-cells = <2>; reg = <0x40000 0x40000>; device_type = "open-pic"; + compatible = "chrp,open-pic"; }; cpm@919c0 { diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts index b9ac6c9..3fe3520 100644 --- a/arch/powerpc/boot/dts/tqm8560.dts +++ b/arch/powerpc/boot/dts/tqm8560.dts @@ -2,6 +2,7 @@ * TQM 8560 Device Tree Source * * Copyright 2008 Freescale Semiconductor Inc. + * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -12,8 +13,8 @@ /dts-v1/; / { - model = "tqm,8560"; - compatible = "tqm,8560", "tqm,85xx"; + model = "tqc,tqm8560"; + compatible = "tqc,tqm8560"; #address-cells = <1>; #size-cells = <1>; @@ -40,6 +41,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -64,7 +66,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; @@ -89,6 +91,47 @@ }; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -145,6 +188,7 @@ #interrupt-cells = <2>; reg = <0x40000 0x40000>; device_type = "open-pic"; + compatible = "chrp,open-pic"; }; cpm@919c0 { @@ -221,6 +265,70 @@ }; }; + localbus@e0005000 { + compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xe0005000 0x100>; // BRx, ORx, etc. + + ranges = < + 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 + 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 + 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527) + >; + + flash@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <1 0x0 0x8000000>; + bank-width = <4>; + device-width = <1>; + + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00200000>; + }; + partition@200000 { + label = "root"; + reg = <0x00200000 0x00300000>; + }; + partition@500000 { + label = "user"; + reg = <0x00500000 0x07a00000>; + }; + partition@7f00000 { + label = "env1"; + reg = <0x07f00000 0x00040000>; + }; + partition@7f40000 { + label = "env2"; + reg = <0x07f40000 0x00040000>; + }; + partition@7f80000 { + label = "u-boot"; + reg = <0x07f80000 0x00080000>; + read-only; + }; + }; + + /* Note: CAN support needs be enabled in U-Boot */ + can0@2,0 { + compatible = "intel,82527"; // Bosch CC770 + reg = <2 0x0 0x100>; + interrupts = <4 0>; + interrupt-parent = <&mpic>; + }; + + can1@2,100 { + compatible = "intel,82527"; // Bosch CC770 + reg = <2 0x100 0x100>; + interrupts = <4 0>; + interrupt-parent = <&mpic>; + }; + }; + pci0: pci@e0008000 { cell-index = <0>; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/walnut.dts b/arch/powerpc/boot/dts/walnut.dts index a328607..4a9f726 100644 --- a/arch/powerpc/boot/dts/walnut.dts +++ b/arch/powerpc/boot/dts/walnut.dts @@ -9,12 +9,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <1>; #size-cells = <1>; model = "ibm,walnut"; compatible = "ibm,walnut"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC; @@ -29,13 +31,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,405GP"; - reg = <0>; - clock-frequency = <bebc200>; /* Filled in by zImage */ + reg = <0x00000000>; + clock-frequency = <200000000>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <4000>; - d-cache-size = <4000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <16384>; + d-cache-size = <16384>; dcr-controller; dcr-access-method = "native"; }; @@ -43,14 +45,14 @@ memory { device_type = "memory"; - reg = <0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller { compatible = "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 9>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -65,63 +67,63 @@ SDRAM0: memory-controller { compatible = "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL: mcmal { compatible = "ibm,mcmal-405gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <1>; num-rx-chans = <1>; interrupt-parent = <&UIC0>; interrupts = < - b 4 /* TXEOB */ - c 4 /* RXEOB */ - a 4 /* SERR */ - d 4 /* TXDE */ - e 4 /* RXDE */>; + 0xb 0x4 /* TXEOB */ + 0xc 0x4 /* RXEOB */ + 0xa 0x4 /* SERR */ + 0xd 0x4 /* TXDE */ + 0xe 0x4 /* RXDE */>; }; POB0: opb { compatible = "ibm,opb-405gp", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <ef600000 ef600000 a00000>; - dcr-reg = <0a0 5>; + ranges = <0xef600000 0xef600000 0x00a00000>; + dcr-reg = <0x0a0 0x005>; clock-frequency = <0>; /* Filled in by zImage */ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600300 8>; - virtual-reg = <ef600300>; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <2580>; + current-speed = <9600>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600400 8>; - virtual-reg = <ef600400>; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <2580>; + current-speed = <9600>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC: i2c@ef600500 { compatible = "ibm,iic-405gp", "ibm,iic"; - reg = <ef600500 11>; + reg = <0xef600500 0x00000011>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; GPIO: gpio@ef600700 { compatible = "ibm,gpio-405gp"; - reg = <ef600700 20>; + reg = <0xef600700 0x00000020>; }; EMAC: ethernet@ef600800 { @@ -129,26 +131,26 @@ compatible = "ibm,emac-405gp", "ibm,emac"; interrupt-parent = <&UIC0>; interrupts = < - f 4 /* Ethernet */ - 9 4 /* Ethernet Wake Up */>; + 0xf 0x4 /* Ethernet */ + 0x9 0x4 /* Ethernet Wake Up */>; local-mac-address = [000000000000]; /* Filled in by zImage */ - reg = <ef600800 70>; + reg = <0xef600800 0x00000070>; mal-device = <&MAL>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000001>; + phy-map = <0x00000001>; }; }; EBC0: ebc { compatible = "ibm,ebc-405gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; /* The ranges property is supplied by the bootwrapper @@ -158,18 +160,18 @@ clock-frequency = <0>; /* Filled in by zImage */ sram@0,0 { - reg = <0 0 80000>; + reg = <0x00000000 0x00000000 0x00080000>; }; flash@0,80000 { compatible = "jedec-flash"; bank-width = <1>; - reg = <0 80000 80000>; + reg = <0x00000000 0x00080000 0x00080000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "OpenBIOS"; - reg = <0 80000>; + reg = <0x00000000 0x00080000>; read-only; }; }; @@ -177,24 +179,24 @@ nvram@1,0 { /* NVRAM and RTC */ compatible = "ds1743-nvram"; - #bytes = <2000>; - reg = <1 0 2000>; + #bytes = <0x2000>; + reg = <0x00000001 0x00000000 0x00002000>; }; keyboard@2,0 { compatible = "intel,82C42PC"; - reg = <2 0 2>; + reg = <0x00000002 0x00000000 0x00000002>; }; ir@3,0 { compatible = "ti,TIR2000PAG"; - reg = <3 0 10>; + reg = <0x00000003 0x00000000 0x00000010>; }; fpga@7,0 { compatible = "Walnut-FPGA"; - reg = <7 0 10>; - virtual-reg = <f0300005>; + reg = <0x00000007 0x00000000 0x00000010>; + virtual-reg = <0xf0300005>; }; }; @@ -205,35 +207,35 @@ #address-cells = <3>; compatible = "ibm,plb405gp-pci", "ibm,plb-pci"; primary; - reg = <eec00000 8 /* Config space access */ - eed80000 4 /* IACK */ - eed80000 4 /* Special cycle */ - ef480000 40>; /* Internal registers */ + reg = <0xeec00000 0x00000008 /* Config space access */ + 0xeed80000 0x00000004 /* IACK */ + 0xeed80000 0x00000004 /* Special cycle */ + 0xef480000 0x00000040>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second * IO range but we don't use it for now */ - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e8000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 + 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* Walnut has all 4 IRQ pins tied together per slot */ - interrupt-map-mask = <f800 0 0 0>; + interrupt-map-mask = <0xf800 0x0 0x0 0x0>; interrupt-map = < /* IDSEL 1 */ - 0800 0 0 0 &UIC0 1c 8 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 /* IDSEL 2 */ - 1000 0 0 0 &UIC0 1d 8 + 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8 /* IDSEL 3 */ - 1800 0 0 0 &UIC0 1e 8 + 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8 /* IDSEL 4 */ - 2000 0 0 0 &UIC0 1f 8 + 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8 >; }; }; diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts index b04a52e..340018c 100644 --- a/arch/powerpc/boot/dts/warp.dts +++ b/arch/powerpc/boot/dts/warp.dts @@ -9,12 +9,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "pika,warp"; compatible = "pika,warp"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -28,13 +30,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440EP"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -42,14 +44,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -59,22 +61,22 @@ compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440ep"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-440ep"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -86,86 +88,79 @@ SDRAM0: sdram { compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; DMA0: dma { compatible = "ibm,dma-440ep", "ibm,dma-440gp"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 - /*RXEOB*/ 1 &UIC0 b 4 - /*SERR*/ 2 &UIC1 0 4 - /*TXDE*/ 3 &UIC1 1 4 - /*RXDE*/ 4 &UIC1 2 4>; + interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 + /*RXEOB*/ 0x1 &UIC0 0xb 0x4 + /*SERR*/ 0x2 &UIC1 0x0 0x4 + /*TXDE*/ 0x3 &UIC1 0x1 0x4 + /*RXDE*/ 0x4 &UIC1 0x2 0x4>; }; POB0: opb { compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <00000000 0 00000000 80000000 - 80000000 0 80000000 80000000>; + ranges = <0x00000000 0x00000000 0x00000000 0x80000000 + 0x80000000 0x00000000 0x80000000 0x80000000>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; fpga@2,0 { compatible = "pika,fpga"; - reg = <2 0 2200>; - interrupts = <18 8>; + reg = <0x00000002 0x00000000 0x00001000>; + interrupts = <0x18 0x8>; interrupt-parent = <&UIC0>; }; + fpga@2,4000 { + compatible = "pika,fpga-sd"; + reg = <0x00000002 0x00004000 0x00000A00>; + }; + nor_flash@0,0 { - compatible = "amd,s29gl512n", "cfi-flash"; + compatible = "amd,s29gl032a", "cfi-flash"; bank-width = <2>; - reg = <0 0 4000000>; + reg = <0x00000000 0x00000000 0x00400000>; #address-cells = <1>; #size-cells = <1>; - partition@0 { - label = "kernel"; - reg = <0 180000>; - }; - partition@180000 { - label = "root"; - reg = <180000 3480000>; - }; - partition@3600000 { - label = "user"; - reg = <3600000 900000>; - }; - partition@3f00000 { + partition@300000 { label = "fpga"; - reg = <3f00000 40000>; + reg = <0x0030000 0x00040000>; }; - partition@3f40000 { + partition@340000 { label = "env"; - reg = <3f40000 40000>; + reg = <0x0340000 0x00040000>; }; - partition@3f80000 { + partition@380000 { label = "u-boot"; - reg = <3f80000 80000>; + reg = <0x0380000 0x00080000>; }; }; }; @@ -173,60 +168,80 @@ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600300 8>; - virtual-reg = <ef600300>; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <115200>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; - reg = <ef600700 14>; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; + index = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + ad7414@4a { + compatible = "adi,ad7414"; + reg = <0x4a>; + interrupts = <0x19 0x8>; + interrupt-parent = <&UIC0>; + }; }; GPIO0: gpio@ef600b00 { compatible = "ibm,gpio-440ep"; - reg = <ef600b00 48>; + reg = <0xef600b00 0x00000048>; + #gpio-cells = <2>; + gpio-controller; }; GPIO1: gpio@ef600c00 { compatible = "ibm,gpio-440ep"; - reg = <ef600c00 48>; + reg = <0xef600c00 0x00000048>; + #gpio-cells = <2>; + gpio-controller; + + led@31 { + compatible = "linux,gpio-led"; + linux,name = ":green:"; + gpios = <&GPIO1 0x30 0>; + }; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; - reg = <ef600d00 c>; + reg = <0xef600d00 0x0000000c>; }; EMAC0: ethernet@ef600e00 { device_type = "network"; compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = <ef600e00 70>; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0 1>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <0>; }; usb@ef601000 { compatible = "ohci-be"; - reg = <ef601000 80>; - interrupts = <8 1 9 1>; + reg = <0xef601000 0x00000080>; + interrupts = <0x8 0x1 0x9 0x1>; interrupt-parent = < &UIC1 >; }; }; diff --git a/arch/powerpc/boot/dts/yosemite.dts b/arch/powerpc/boot/dts/yosemite.dts index 0d6d332..e39422a 100644 --- a/arch/powerpc/boot/dts/yosemite.dts +++ b/arch/powerpc/boot/dts/yosemite.dts @@ -9,12 +9,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,yosemite"; compatible = "amcc,yosemite","amcc,bamboo"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -32,13 +34,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440EP"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -46,14 +48,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -63,22 +65,22 @@ compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440ep"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-440ep"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -90,29 +92,29 @@ SDRAM0: sdram { compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; DMA0: dma { compatible = "ibm,dma-440ep", "ibm,dma-440gp"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 - /*RXEOB*/ 1 &UIC0 b 4 - /*SERR*/ 2 &UIC1 0 4 - /*TXDE*/ 3 &UIC1 1 4 - /*RXDE*/ 4 &UIC1 2 4>; + interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 + /*RXEOB*/ 0x1 &UIC0 0xb 0x4 + /*SERR*/ 0x2 &UIC1 0x0 0x4 + /*TXDE*/ 0x3 &UIC1 0x1 0x4 + /*RXDE*/ 0x4 &UIC1 0x2 0x4>; }; POB0: opb { @@ -122,110 +124,110 @@ /* Bamboo is oddball in the 44x world and doesn't use the ERPN * bits. */ - ranges = <00000000 0 00000000 80000000 - 80000000 0 80000000 80000000>; + ranges = <0x00000000 0x00000000 0x00000000 0x80000000 + 0x80000000 0x00000000 0x80000000 0x80000000>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; }; UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600300 8>; - virtual-reg = <ef600300>; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <115200>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600400 8>; - virtual-reg = <ef600400>; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600500 8>; - virtual-reg = <ef600500>; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; status = "disabled"; }; UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = <ef600600 8>; - virtual-reg = <ef600600>; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <4 4>; + interrupts = <0x4 0x4>; status = "disabled"; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; - reg = <ef600700 14>; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; - reg = <ef600800 14>; + reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; spi@ef600900 { compatible = "amcc,spi-440ep"; - reg = <ef600900 6>; - interrupts = <8 4>; + reg = <0xef600900 0x00000006>; + interrupts = <0x8 0x4>; interrupt-parent = <&UIC0>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; - reg = <ef600d00 c>; + reg = <0xef600d00 0x0000000c>; }; EMAC0: ethernet@ef600e00 { device_type = "network"; compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = <ef600e00 70>; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0 1>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <0>; }; @@ -234,26 +236,26 @@ device_type = "network"; compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1e 4 1f 4>; - reg = <ef600f00 70>; + interrupts = <0x1e 0x4 0x1f 0x4>; + reg = <0xef600f00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <2 3>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <1>; }; usb@ef601000 { compatible = "ohci-be"; - reg = <ef601000 80>; - interrupts = <8 4 9 4>; + reg = <0xef601000 0x00000080>; + interrupts = <0x8 0x4 0x9 0x4>; interrupt-parent = < &UIC1 >; }; }; @@ -265,35 +267,35 @@ #address-cells = <3>; compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; primary; - reg = <0 eec00000 8 /* Config space access */ - 0 eed00000 4 /* IACK */ - 0 eed00000 4 /* Special cycle */ - 0 ef400000 40>; /* Internal registers */ + reg = <0x00000000 0xeec00000 0x00000008 /* Config space access */ + 0x00000000 0xeed00000 0x00000004 /* IACK */ + 0x00000000 0xeed00000 0x00000004 /* Special cycle */ + 0x00000000 0xef400000 0x00000040>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second * IO range but we don't use it for now */ - ranges = <02000000 0 a0000000 0 a0000000 0 20000000 - 01000000 0 00000000 0 e8000000 0 00010000>; + ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x20000000 + 0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* Bamboo has all 4 IRQ pins tied together per slot */ - interrupt-map-mask = <f800 0 0 0>; + interrupt-map-mask = <0xf800 0x0 0x0 0x0>; interrupt-map = < /* IDSEL 1 */ - 0800 0 0 0 &UIC0 1c 8 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 /* IDSEL 2 */ - 1000 0 0 0 &UIC0 1b 8 + 0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8 /* IDSEL 3 */ - 1800 0 0 0 &UIC0 1a 8 + 0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8 /* IDSEL 4 */ - 2000 0 0 0 &UIC0 19 8 + 0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8 >; }; }; diff --git a/arch/powerpc/boot/redboot-83xx.c b/arch/powerpc/boot/redboot-83xx.c new file mode 100644 index 0000000..79aa9e1 --- /dev/null +++ b/arch/powerpc/boot/redboot-83xx.c @@ -0,0 +1,60 @@ +/* + * RedBoot firmware support + * + * Author: Scott Wood <scottwood@freescale.com> + * + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * Copyright (c) 2008 Codehermit + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "stdio.h" +#include "redboot.h" +#include "fsl-soc.h" +#include "io.h" + +static bd_t bd; +BSS_STACK(4096); + +#define MHZ(x) ((x + 500000) / 1000000) + +static void platform_fixups(void) +{ + void *node; + + dt_fixup_memory(bd.bi_memstart, bd.bi_memsize); + dt_fixup_mac_addresses(bd.bi_enetaddr); + dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 16, bd.bi_busfreq); + + node = finddevice("/soc/cpm/brg"); + if (node) { + printf("BRG clock-frequency <- 0x%x (%dMHz)\r\n", + bd.bi_busfreq, MHZ(bd.bi_busfreq)); + setprop(node, "clock-frequency", &bd.bi_busfreq, 4); + } + +} + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + memcpy(&bd, (char *)r3, sizeof(bd)); + + if (bd.bi_tag != 0x42444944) + return; + + simple_alloc_init(_end, + bd.bi_memstart + bd.bi_memsize - (unsigned long)_end, + 32, 64); + + fdt_init(_dtb_start); + serial_console_init(); + platform_ops.fixups = platform_fixups; + + loader_info.cmdline = (char *)bd.bi_cmdline; + loader_info.cmdline_len = strlen((char *)bd.bi_cmdline); +} diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index d6c96d9..cb87a01 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -171,13 +171,13 @@ cuboot*) *-mpc824*) platformo=$object/cuboot-824x.o ;; - *-mpc83*) + *-mpc83*|*-asp834x*) platformo=$object/cuboot-83xx.o ;; *-tqm8541|*-mpc8560*|*-tqm8560|*-tqm8555|*-ksi8560*) platformo=$object/cuboot-85xx-cpm2.o ;; - *-mpc85*|*-tqm8540|*-sbc85*) + *-mpc85*|*-tqm85*|*-sbc85*) platformo=$object/cuboot-85xx.o ;; esac @@ -203,6 +203,10 @@ simpleboot-virtex405-*) platformo="$object/virtex405-head.o $object/simpleboot.o" binary=y ;; +asp834x-redboot) + platformo="$object/fixed-head.o $object/redboot-83xx.o" + binary=y + ;; esac vmz="$tmpdir/`basename \"$kernel\"`.$ext" |