diff options
Diffstat (limited to 'arch')
144 files changed, 1347 insertions, 809 deletions
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 2b36afd..7e55ea6 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -534,7 +534,7 @@ config ARCH_DISCONTIGMEM_ENABLE bool "Discontiguous Memory Support (EXPERIMENTAL)" depends on EXPERIMENTAL help - Say Y to upport efficient handling of discontiguous physical memory, + Say Y to support efficient handling of discontiguous physical memory, for architectures which are either NUMA (Non-Uniform Memory Access) or have huge holes in the physical address space for other reasons. See <file:Documentation/vm/numa> for more. diff --git a/arch/alpha/kernel/alpha_ksyms.c b/arch/alpha/kernel/alpha_ksyms.c index dbe327d..8b02420 100644 --- a/arch/alpha/kernel/alpha_ksyms.c +++ b/arch/alpha/kernel/alpha_ksyms.c @@ -1,5 +1,5 @@ /* - * linux/arch/alpha/kernel/ksyms.c + * linux/arch/alpha/kernel/alpha_ksyms.c * * Export the alpha-specific functions that are needed for loadable * modules. diff --git a/arch/alpha/kernel/head.S b/arch/alpha/kernel/head.S index 1e2a62a..e27d23c 100644 --- a/arch/alpha/kernel/head.S +++ b/arch/alpha/kernel/head.S @@ -1,5 +1,5 @@ /* - * alpha/boot/head.S + * arch/alpha/kernel/head.S * * initial boot stuff.. At this point, the bootloader has already * switched into OSF/1 PAL-code, and loaded us at the correct address diff --git a/arch/alpha/kernel/machvec_impl.h b/arch/alpha/kernel/machvec_impl.h index 08b8302..0caa45a 100644 --- a/arch/alpha/kernel/machvec_impl.h +++ b/arch/alpha/kernel/machvec_impl.h @@ -1,5 +1,5 @@ /* - * linux/arch/alpha/kernel/machvec.h + * linux/arch/alpha/kernel/machvec_impl.h * * Copyright (C) 1997, 1998 Richard Henderson * diff --git a/arch/alpha/lib/dbg_stackcheck.S b/arch/alpha/lib/dbg_stackcheck.S index 3c1f3e6..78f6b92 100644 --- a/arch/alpha/lib/dbg_stackcheck.S +++ b/arch/alpha/lib/dbg_stackcheck.S @@ -1,5 +1,5 @@ /* - * arch/alpha/lib/stackcheck.S + * arch/alpha/lib/dbg_stackcheck.S * Contributed by Richard Henderson (rth@tamu.edu) * * Verify that we have not overflowed the stack. Oops if we have. diff --git a/arch/alpha/lib/dbg_stackkill.S b/arch/alpha/lib/dbg_stackkill.S index e9f6a9d..c1e40a1 100644 --- a/arch/alpha/lib/dbg_stackkill.S +++ b/arch/alpha/lib/dbg_stackkill.S @@ -1,5 +1,5 @@ /* - * arch/alpha/lib/killstack.S + * arch/alpha/lib/dbg_stackkill.S * Contributed by Richard Henderson (rth@cygnus.com) * * Clobber the balance of the kernel stack, hoping to catch diff --git a/arch/alpha/lib/memset.S b/arch/alpha/lib/memset.S index 8ff6e7e..311b8cf 100644 --- a/arch/alpha/lib/memset.S +++ b/arch/alpha/lib/memset.S @@ -1,5 +1,5 @@ /* - * linux/arch/alpha/memset.S + * linux/arch/alpha/lib/memset.S * * This is an efficient (and small) implementation of the C library "memset()" * function for the alpha. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f9362ee..adb05de 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -629,7 +629,7 @@ config ALIGNMENT_TRAP depends on CPU_CP15_MMU default y if !ARCH_EBSA110 help - ARM processors can not fetch/store information which is not + ARM processors cannot fetch/store information which is not naturally aligned on the bus, i.e., a 4 byte fetch must start at an address divisible by 4. On 32-bit ARM processors, these non-aligned fetch/store instructions will be emulated in software if you say diff --git a/arch/arm/boot/compressed/head-clps7500.S b/arch/arm/boot/compressed/head-clps7500.S index 941c5f5..4f3c78a 100644 --- a/arch/arm/boot/compressed/head-clps7500.S +++ b/arch/arm/boot/compressed/head-clps7500.S @@ -1,5 +1,5 @@ /* - * linux/arch/arm/boot/compressed/head.S + * linux/arch/arm/boot/compressed/head-clps7500.S * * Copyright (C) 1999, 2000, 2001 Nexus Electronics Ltd */ diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 29818bd..30046ad 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-sa1100/sa1111.c + * linux/arch/arm/common/sa1111.c * * SA1111 support * diff --git a/arch/arm/mach-imx/leds.c b/arch/arm/mach-imx/leds.c index 471c1db..cf30803 100644 --- a/arch/arm/mach-imx/leds.c +++ b/arch/arm/mach-imx/leds.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-imx/leds.h + * linux/arch/arm/mach-imx/leds.c * * Copyright (C) 2004 Sascha Hauer <sascha@saschahauer.de> * diff --git a/arch/arm/mach-imx/leds.h b/arch/arm/mach-imx/leds.h index 83fa21e..49dc1c1 100644 --- a/arch/arm/mach-imx/leds.h +++ b/arch/arm/mach-imx/leds.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-imx/leds.h + * arch/arm/mach-imx/leds.h * * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> * diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index 2cebb28..7bc94f3 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c @@ -1,5 +1,5 @@ /* - * arch/arch/mach-ixp4xx/coyote-pci.c + * arch/arm/mach-ixp4xx/coyote-pci.c * * PCI setup routines for ADI Engineering Coyote platform * diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index ed52708..509a95a 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c @@ -1,5 +1,5 @@ /* - * arch/arch/mach-ixp4xx/ixdpg425-pci.c + * arch/arm/mach-ixp4xx/ixdpg425-pci.c * * PCI setup routines for Intel IXDPG425 Platform * diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c index a691011..a21b12f 100644 --- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c +++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c @@ -164,7 +164,7 @@ static void lh7a40x_ack_cpld_irq (u32 irq) /* CPLD doesn't have ack capability, but some devices may */ #if defined (CPLD_INTMASK_TOUCH) - /* The touch control *must* mask the the interrupt because the + /* The touch control *must* mask the interrupt because the * interrupt bit is read by the driver to determine if the pen * is still down. */ if (irq == IRQ_TOUCH) diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 976edfb..c4b7902 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap1/id.c + * linux/arch/arm/mach-omap1/serial.c * * OMAP1 CPU identification code * diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 2db6b73..c37b0e6 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap/omap2/board-apollon.c + * linux/arch/arm/mach-omap2/board-apollon.c * * Copyright (C) 2005,2006 Samsung Electronics * Author: Kyungmin Park <kyungmin.park@samsung.com> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index eaecbf4..9093815 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap/omap2/board-generic.c + * linux/arch/arm/mach-omap2/board-generic.c * * Copyright (C) 2005 Nokia Corporation * Author: Paul Mundt <paul.mundt@nokia.com> diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 996aeda..26a95a6 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap/omap2/board-h4.c + * linux/arch/arm/mach-omap2/board-h4.c * * Copyright (C) 2005 Nokia Corporation * Author: Paul Mundt <paul.mundt@nokia.com> diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 1ed2fff..1187009 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap/omap2/irq.c + * linux/arch/arm/mach-omap2/irq.c * * Interrupt handler for OMAP2 boards. * diff --git a/arch/arm/mach-omap2/prcm-regs.h b/arch/arm/mach-omap2/prcm-regs.h index 22ac7be..5e1c4b5 100644 --- a/arch/arm/mach-omap2/prcm-regs.h +++ b/arch/arm/mach-omap2/prcm-regs.h @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap2/prcm-reg.h + * linux/arch/arm/mach-omap2/prcm-regs.h * * OMAP24XX Power Reset and Clock Management (PRCM) registers * diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 0884bc7..aaa5589 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-omap/omap2/serial.c + * arch/arm/mach-omap2/serial.c * * OMAP2 serial support. * diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S index a5ef7f6..b275766 100644 --- a/arch/arm/mach-omap2/sram-fn.S +++ b/arch/arm/mach-omap2/sram-fn.S @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap2/sram.S + * linux/arch/arm/mach-omap2/sram-fn.S * * Omap2 specific functions that need to be run in internal SRAM * diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c index d781549..a72476c 100644 --- a/arch/arm/mach-pxa/corgi_lcd.c +++ b/arch/arm/mach-pxa/corgi_lcd.c @@ -1,5 +1,5 @@ /* - * linux/drivers/video/w100fb.c + * linux/arch/arm/mach-pxa/corgi_lcd.c * * Corgi/Spitz LCD Specific Code * diff --git a/arch/arm/mach-pxa/leds.h b/arch/arm/mach-pxa/leds.h index 4f829b8..7f0dfe0 100644 --- a/arch/arm/mach-pxa/leds.h +++ b/arch/arm/mach-pxa/leds.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-pxa/leds.h + * arch/arm/mach-pxa/leds.h * * Copyright (c) 2001 Jeff Sutherland, Accelent Systems Inc. * diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index df37594..63965c7 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -13,7 +13,7 @@ config MACH_ANUBIS bool "Simtec Electronics ANUBIS" select CPU_S3C2440 help - Say Y gere if you are using the Simtec Electronics ANUBIS + Say Y here if you are using the Simtec Electronics ANUBIS development system config MACH_OSIRIS diff --git a/arch/arm/mach-s3c2410/s3c2400-gpio.c b/arch/arm/mach-s3c2410/s3c2400-gpio.c index f2a7817..1576d01 100644 --- a/arch/arm/mach-s3c2410/s3c2400-gpio.c +++ b/arch/arm/mach-s3c2410/s3c2400-gpio.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c2410/gpio.c +/* linux/arch/arm/mach-s3c2410/s3c2400-gpio.c * * Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org> * diff --git a/arch/arm/mach-s3c2410/s3c2410-clock.c b/arch/arm/mach-s3c2410/s3c2410-clock.c index 9971866..00abe19 100644 --- a/arch/arm/mach-s3c2410/s3c2410-clock.c +++ b/arch/arm/mach-s3c2410/s3c2410-clock.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c2410/clock.c +/* linux/arch/arm/mach-s3c2410/s3c2410-clock.c * * Copyright (c) 2006 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/mach-s3c2410/s3c2410-gpio.c b/arch/arm/mach-s3c2410/s3c2410-gpio.c index 471a714..a2098f6 100644 --- a/arch/arm/mach-s3c2410/s3c2410-gpio.c +++ b/arch/arm/mach-s3c2410/s3c2410-gpio.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c2410/gpio.c +/* linux/arch/arm/mach-s3c2410/s3c2410-gpio.c * * Copyright (c) 2004-2006 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/mach-s3c2410/s3c2442.c b/arch/arm/mach-s3c2410/s3c2442.c index debae24..581667e 100644 --- a/arch/arm/mach-s3c2410/s3c2442.c +++ b/arch/arm/mach-s3c2410/s3c2442.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c2410/s3c2440.c +/* linux/arch/arm/mach-s3c2410/s3c2442.c * * Copyright (c) 2006 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/mach-s3c2410/s3c244x-irq.c b/arch/arm/mach-s3c2410/s3c244x-irq.c index 0d13546..ec702f8 100644 --- a/arch/arm/mach-s3c2410/s3c244x-irq.c +++ b/arch/arm/mach-s3c2410/s3c244x-irq.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c2410/s3c2440-irq.c +/* linux/arch/arm/mach-s3c2410/s3c244x-irq.c * * Copyright (c) 2003,2004 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/mach-s3c2410/s3c244x.h b/arch/arm/mach-s3c2410/s3c244x.h index 3e7f5f7..1488c1e 100644 --- a/arch/arm/mach-s3c2410/s3c244x.h +++ b/arch/arm/mach-s3c2410/s3c244x.h @@ -1,4 +1,4 @@ -/* arch/arm/mach-s3c2410/s3c2440.h +/* arch/arm/mach-s3c2410/s3c244x.h * * Copyright (c) 2004-2005 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/mach-s3c2410/usb-simtec.h b/arch/arm/mach-s3c2410/usb-simtec.h index 92c0cc8..d8aa612 100644 --- a/arch/arm/mach-s3c2410/usb-simtec.h +++ b/arch/arm/mach-s3c2410/usb-simtec.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c2410/usb-simtec.c +/* linux/arch/arm/mach-s3c2410/usb-simtec.h * * Copyright (c) 2004 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/mach-sa1100/dma.c b/arch/arm/mach-sa1100/dma.c index 3c6441d..2ea2a65 100644 --- a/arch/arm/mach-sa1100/dma.c +++ b/arch/arm/mach-sa1100/dma.c @@ -1,5 +1,5 @@ /* - * arch/arm/kernel/dma-sa1100.c + * arch/arm/mach-sa1100/dma.c * * Support functions for the SA11x0 internal DMA channels. * diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c index 7cd86d3..5386a81f 100644 --- a/arch/arm/mach-shark/leds.c +++ b/arch/arm/mach-shark/leds.c @@ -1,5 +1,5 @@ /* - * arch/arm/kernel/leds-shark.c + * arch/arm/mach-shark/leds.c * by Alexander Schulz * * derived from: diff --git a/arch/arm/plat-omap/sram-fn.S b/arch/arm/plat-omap/sram-fn.S index 85cffe2..9e1813c 100644 --- a/arch/arm/plat-omap/sram-fn.S +++ b/arch/arm/plat-omap/sram-fn.S @@ -1,5 +1,5 @@ /* - * linux/arch/arm/plat-omap/sram.S + * linux/arch/arm/plat-omap/sram-fn.S * * Functions that need to be run in internal SRAM * diff --git a/arch/cris/arch-v10/drivers/Kconfig b/arch/cris/arch-v10/drivers/Kconfig index 8b50e84..734d5f3 100644 --- a/arch/cris/arch-v10/drivers/Kconfig +++ b/arch/cris/arch-v10/drivers/Kconfig @@ -550,7 +550,7 @@ config ETRAX_IDE select BLK_DEV_IDEDMA help Enable this to get support for ATA/IDE. - You can't use paralell ports or SCSI ports + You can't use parallel ports or SCSI ports at the same time. @@ -744,7 +744,7 @@ config ETRAX_PA_CHANGEABLE_BITS default "FF" help This is a bitmask with information of what bits in PA that a user - can change change the value on using ioctl's. + can change the value on using ioctl's. Bit set = changeable. You probably want 00 here. diff --git a/arch/cris/arch-v32/Kconfig b/arch/cris/arch-v32/Kconfig index 22f0ddc..4f79d8e 100644 --- a/arch/cris/arch-v32/Kconfig +++ b/arch/cris/arch-v32/Kconfig @@ -162,7 +162,7 @@ config ETRAX_SDRAM_GRP1_CONFIG depends on ETRAX_ARCH_V32 default "0" help - SDRAM configuration for group 1. The defult value is 0 + SDRAM configuration for group 1. The default value is 0 because group 1 is not used in the default configuration, described in the help for SDRAM_GRP0_CONFIG. diff --git a/arch/h8300/kernel/ints.c b/arch/h8300/kernel/ints.c index 1488b6a..1bfc77e 100644 --- a/arch/h8300/kernel/ints.c +++ b/arch/h8300/kernel/ints.c @@ -1,5 +1,5 @@ /* - * linux/arch/h8300/platform/h8300h/ints.c + * linux/arch/h8300/kernel/ints.c * * Yoshinori Sato <ysato@users.sourceforge.jp> * diff --git a/arch/i386/Kconfig b/arch/i386/Kconfig index af219e5..8ff1c6f 100644 --- a/arch/i386/Kconfig +++ b/arch/i386/Kconfig @@ -682,7 +682,7 @@ config EFI depends on ACPI default n ---help--- - This enables the the kernel to boot on EFI platforms using + This enables the kernel to boot on EFI platforms using system configuration information passed to it from the firmware. This also enables the kernel to use any EFI runtime services that are available (such as the EFI variable services). diff --git a/arch/i386/kernel/acpi/boot.c b/arch/i386/kernel/acpi/boot.c index 1aaea6a..92f79cd 100644 --- a/arch/i386/kernel/acpi/boot.c +++ b/arch/i386/kernel/acpi/boot.c @@ -62,8 +62,6 @@ static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id) { return #include <mach_mpparse.h> #endif /* CONFIG_X86_LOCAL_APIC */ -static inline int gsi_irq_sharing(int gsi) { return gsi; } - #endif /* X86 */ #define BAD_MADT_ENTRY(entry, end) ( \ @@ -468,12 +466,7 @@ void __init acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger) int acpi_gsi_to_irq(u32 gsi, unsigned int *irq) { -#ifdef CONFIG_X86_IO_APIC - if (use_pci_vector() && !platform_legacy_irq(gsi)) - *irq = IO_APIC_VECTOR(gsi); - else -#endif - *irq = gsi_irq_sharing(gsi); + *irq = gsi; return 0; } diff --git a/arch/i386/kernel/cpu/common.c b/arch/i386/kernel/cpu/common.c index b2f24d5..d9f3e3c 100644 --- a/arch/i386/kernel/cpu/common.c +++ b/arch/i386/kernel/cpu/common.c @@ -669,8 +669,7 @@ old_gdt: */ atomic_inc(&init_mm.mm_count); current->active_mm = &init_mm; - if (current->mm) - BUG(); + BUG_ON(current->mm); enter_lazy_tlb(&init_mm, current); load_esp0(t, thread); diff --git a/arch/i386/kernel/efi.c b/arch/i386/kernel/efi.c index f943698..8b40648 100644 --- a/arch/i386/kernel/efi.c +++ b/arch/i386/kernel/efi.c @@ -498,8 +498,7 @@ void __init efi_enter_virtual_mode(void) check_range_for_systab(md); } - if (!efi.systab) - BUG(); + BUG_ON(!efi.systab); status = phys_efi_set_virtual_address_map( memmap.desc_size * memmap.nr_map, diff --git a/arch/i386/kernel/i8259.c b/arch/i386/kernel/i8259.c index ea5f4e7..d07ed31 100644 --- a/arch/i386/kernel/i8259.c +++ b/arch/i386/kernel/i8259.c @@ -34,35 +34,15 @@ * moves to arch independent land */ -DEFINE_SPINLOCK(i8259A_lock); - -static void end_8259A_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) && - irq_desc[irq].action) - enable_8259A_irq(irq); -} - -#define shutdown_8259A_irq disable_8259A_irq - static int i8259A_auto_eoi; - +DEFINE_SPINLOCK(i8259A_lock); static void mask_and_ack_8259A(unsigned int); -unsigned int startup_8259A_irq(unsigned int irq) -{ - enable_8259A_irq(irq); - return 0; /* never anything pending */ -} - -static struct hw_interrupt_type i8259A_irq_type = { - .typename = "XT-PIC", - .startup = startup_8259A_irq, - .shutdown = shutdown_8259A_irq, - .enable = enable_8259A_irq, - .disable = disable_8259A_irq, - .ack = mask_and_ack_8259A, - .end = end_8259A_irq, +static struct irq_chip i8259A_chip = { + .name = "XT-PIC", + .mask = disable_8259A_irq, + .unmask = enable_8259A_irq, + .mask_ack = mask_and_ack_8259A, }; /* @@ -133,7 +113,7 @@ void make_8259A_irq(unsigned int irq) { disable_irq_nosync(irq); io_apic_irqs &= ~(1<<irq); - irq_desc[irq].chip = &i8259A_irq_type; + set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq); enable_irq(irq); } @@ -327,12 +307,12 @@ void init_8259A(int auto_eoi) outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */ if (auto_eoi) /* - * in AEOI mode we just have to mask the interrupt + * In AEOI mode we just have to mask the interrupt * when acking. */ - i8259A_irq_type.ack = disable_8259A_irq; + i8259A_chip.mask_ack = disable_8259A_irq; else - i8259A_irq_type.ack = mask_and_ack_8259A; + i8259A_chip.mask_ack = mask_and_ack_8259A; udelay(100); /* wait for 8259A to initialize */ @@ -389,12 +369,13 @@ void __init init_ISA_irqs (void) /* * 16 old-style INTA-cycle interrupts: */ - irq_desc[i].chip = &i8259A_irq_type; + set_irq_chip_and_handler(i, &i8259A_chip, + handle_level_irq); } else { /* * 'high' PCI IRQs filled in on demand */ - irq_desc[i].chip = &no_irq_type; + irq_desc[i].chip = &no_irq_chip; } } } diff --git a/arch/i386/kernel/io_apic.c b/arch/i386/kernel/io_apic.c index fd0df75..b7287fb 100644 --- a/arch/i386/kernel/io_apic.c +++ b/arch/i386/kernel/io_apic.c @@ -31,6 +31,9 @@ #include <linux/acpi.h> #include <linux/module.h> #include <linux/sysdev.h> +#include <linux/pci.h> +#include <linux/msi.h> +#include <linux/htirq.h> #include <asm/io.h> #include <asm/smp.h> @@ -38,6 +41,8 @@ #include <asm/timer.h> #include <asm/i8259.h> #include <asm/nmi.h> +#include <asm/msidef.h> +#include <asm/hypertransport.h> #include <mach_apic.h> #include <mach_apicdef.h> @@ -86,15 +91,6 @@ static struct irq_pin_list { int apic, pin, next; } irq_2_pin[PIN_MAP_SIZE]; -int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1}; -#ifdef CONFIG_PCI_MSI -#define vector_to_irq(vector) \ - (platform_legacy_irq(vector) ? vector : vector_irq[vector]) -#else -#define vector_to_irq(vector) (vector) -#endif - - union entry_union { struct { u32 w1, w2; }; struct IO_APIC_route_entry entry; @@ -280,7 +276,7 @@ static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) break; entry = irq_2_pin + entry->next; } - set_irq_info(irq, cpumask); + set_native_irq_info(irq, cpumask); spin_unlock_irqrestore(&ioapic_lock, flags); } @@ -1181,46 +1177,45 @@ static inline int IO_APIC_irq_trigger(int irq) /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }; -int assign_irq_vector(int irq) +static int __assign_irq_vector(int irq) { static int current_vector = FIRST_DEVICE_VECTOR, offset = 0; - unsigned long flags; int vector; - BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS); + BUG_ON((unsigned)irq >= NR_IRQ_VECTORS); - spin_lock_irqsave(&vector_lock, flags); - - if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) { - spin_unlock_irqrestore(&vector_lock, flags); + if (IO_APIC_VECTOR(irq) > 0) return IO_APIC_VECTOR(irq); - } -next: + current_vector += 8; if (current_vector == SYSCALL_VECTOR) - goto next; + current_vector += 8; if (current_vector >= FIRST_SYSTEM_VECTOR) { offset++; - if (!(offset%8)) { - spin_unlock_irqrestore(&vector_lock, flags); + if (!(offset % 8)) return -ENOSPC; - } current_vector = FIRST_DEVICE_VECTOR + offset; } vector = current_vector; - vector_irq[vector] = irq; - if (irq != AUTO_ASSIGN) - IO_APIC_VECTOR(irq) = vector; + IO_APIC_VECTOR(irq) = vector; + + return vector; +} + +static int assign_irq_vector(int irq) +{ + unsigned long flags; + int vector; + spin_lock_irqsave(&vector_lock, flags); + vector = __assign_irq_vector(irq); spin_unlock_irqrestore(&vector_lock, flags); return vector; } - -static struct hw_interrupt_type ioapic_level_type; -static struct hw_interrupt_type ioapic_edge_type; +static struct irq_chip ioapic_chip; #define IOAPIC_AUTO -1 #define IOAPIC_EDGE 0 @@ -1228,16 +1223,14 @@ static struct hw_interrupt_type ioapic_edge_type; static void ioapic_register_intr(int irq, int vector, unsigned long trigger) { - unsigned idx; - - idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq; - if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || trigger == IOAPIC_LEVEL) - irq_desc[idx].chip = &ioapic_level_type; + set_irq_chip_and_handler(irq, &ioapic_chip, + handle_fasteoi_irq); else - irq_desc[idx].chip = &ioapic_edge_type; - set_intr_gate(vector, interrupt[idx]); + set_irq_chip_and_handler(irq, &ioapic_chip, + handle_edge_irq); + set_intr_gate(vector, interrupt[irq]); } static void __init setup_IO_APIC_irqs(void) @@ -1346,7 +1339,8 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in * The timer IRQ doesn't have to know that behind the * scene we have a 8259A-master in AEOI mode ... */ - irq_desc[0].chip = &ioapic_edge_type; + irq_desc[0].chip = &ioapic_chip; + set_irq_handler(0, handle_edge_irq); /* * Add it to the IO-APIC irq-routing table: @@ -1481,17 +1475,12 @@ void __init print_IO_APIC(void) ); } } - if (use_pci_vector()) - printk(KERN_INFO "Using vector-based indexing\n"); printk(KERN_DEBUG "IRQ to pin mappings:\n"); for (i = 0; i < NR_IRQS; i++) { struct irq_pin_list *entry = irq_2_pin + i; if (entry->pin < 0) continue; - if (use_pci_vector() && !platform_legacy_irq(i)) - printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i)); - else - printk(KERN_DEBUG "IRQ%d ", i); + printk(KERN_DEBUG "IRQ%d ", i); for (;;) { printk("-> %d:%d", entry->apic, entry->pin); if (!entry->next) @@ -1918,6 +1907,8 @@ static int __init timer_irq_works(void) */ /* + * Startup quirk: + * * Starting up a edge-triggered IO-APIC interrupt is * nasty - we need to make sure that we get the edge. * If it is already asserted for some reason, we need @@ -1925,8 +1916,10 @@ static int __init timer_irq_works(void) * * This is not complete - we should be able to fake * an edge even if it isn't on the 8259A... + * + * (We do this for level-triggered IRQs too - it cannot hurt.) */ -static unsigned int startup_edge_ioapic_irq(unsigned int irq) +static unsigned int startup_ioapic_irq(unsigned int irq) { int was_pending = 0; unsigned long flags; @@ -1943,47 +1936,18 @@ static unsigned int startup_edge_ioapic_irq(unsigned int irq) return was_pending; } -/* - * Once we have recorded IRQ_PENDING already, we can mask the - * interrupt for real. This prevents IRQ storms from unhandled - * devices. - */ -static void ack_edge_ioapic_irq(unsigned int irq) +static void ack_ioapic_irq(unsigned int irq) { - move_irq(irq); - if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED)) - == (IRQ_PENDING | IRQ_DISABLED)) - mask_IO_APIC_irq(irq); + move_native_irq(irq); ack_APIC_irq(); } -/* - * Level triggered interrupts can just be masked, - * and shutting down and starting up the interrupt - * is the same as enabling and disabling them -- except - * with a startup need to return a "was pending" value. - * - * Level triggered interrupts are special because we - * do not touch any IO-APIC register while handling - * them. We ack the APIC in the end-IRQ handler, not - * in the start-IRQ-handler. Protection against reentrance - * from the same interrupt is still provided, both by the - * generic IRQ layer and by the fact that an unacked local - * APIC does not accept IRQs. - */ -static unsigned int startup_level_ioapic_irq (unsigned int irq) -{ - unmask_IO_APIC_irq(irq); - - return 0; /* don't check for pending */ -} - -static void end_level_ioapic_irq (unsigned int irq) +static void ack_ioapic_quirk_irq(unsigned int irq) { unsigned long v; int i; - move_irq(irq); + move_native_irq(irq); /* * It appears there is an erratum which affects at least version 0x11 * of I/O APIC (that's the 82093AA and cores integrated into various @@ -2018,105 +1982,26 @@ static void end_level_ioapic_irq (unsigned int irq) } } -#ifdef CONFIG_PCI_MSI -static unsigned int startup_edge_ioapic_vector(unsigned int vector) -{ - int irq = vector_to_irq(vector); - - return startup_edge_ioapic_irq(irq); -} - -static void ack_edge_ioapic_vector(unsigned int vector) -{ - int irq = vector_to_irq(vector); - - move_native_irq(vector); - ack_edge_ioapic_irq(irq); -} - -static unsigned int startup_level_ioapic_vector (unsigned int vector) -{ - int irq = vector_to_irq(vector); - - return startup_level_ioapic_irq (irq); -} - -static void end_level_ioapic_vector (unsigned int vector) -{ - int irq = vector_to_irq(vector); - - move_native_irq(vector); - end_level_ioapic_irq(irq); -} - -static void mask_IO_APIC_vector (unsigned int vector) -{ - int irq = vector_to_irq(vector); - - mask_IO_APIC_irq(irq); -} - -static void unmask_IO_APIC_vector (unsigned int vector) -{ - int irq = vector_to_irq(vector); - - unmask_IO_APIC_irq(irq); -} - -#ifdef CONFIG_SMP -static void set_ioapic_affinity_vector (unsigned int vector, - cpumask_t cpu_mask) -{ - int irq = vector_to_irq(vector); - - set_native_irq_info(vector, cpu_mask); - set_ioapic_affinity_irq(irq, cpu_mask); -} -#endif -#endif - -static int ioapic_retrigger(unsigned int irq) +static int ioapic_retrigger_irq(unsigned int irq) { send_IPI_self(IO_APIC_VECTOR(irq)); return 1; } -/* - * Level and edge triggered IO-APIC interrupts need different handling, - * so we use two separate IRQ descriptors. Edge triggered IRQs can be - * handled with the level-triggered descriptor, but that one has slightly - * more overhead. Level-triggered interrupts cannot be handled with the - * edge-triggered handler, without risking IRQ storms and other ugly - * races. - */ -static struct hw_interrupt_type ioapic_edge_type __read_mostly = { - .typename = "IO-APIC-edge", - .startup = startup_edge_ioapic, - .shutdown = shutdown_edge_ioapic, - .enable = enable_edge_ioapic, - .disable = disable_edge_ioapic, - .ack = ack_edge_ioapic, - .end = end_edge_ioapic, +static struct irq_chip ioapic_chip __read_mostly = { + .name = "IO-APIC", + .startup = startup_ioapic_irq, + .mask = mask_IO_APIC_irq, + .unmask = unmask_IO_APIC_irq, + .ack = ack_ioapic_irq, + .eoi = ack_ioapic_quirk_irq, #ifdef CONFIG_SMP - .set_affinity = set_ioapic_affinity, + .set_affinity = set_ioapic_affinity_irq, #endif - .retrigger = ioapic_retrigger, + .retrigger = ioapic_retrigger_irq, }; -static struct hw_interrupt_type ioapic_level_type __read_mostly = { - .typename = "IO-APIC-level", - .startup = startup_level_ioapic, - .shutdown = shutdown_level_ioapic, - .enable = enable_level_ioapic, - .disable = disable_level_ioapic, - .ack = mask_and_ack_level_ioapic, - .end = end_level_ioapic, -#ifdef CONFIG_SMP - .set_affinity = set_ioapic_affinity, -#endif - .retrigger = ioapic_retrigger, -}; static inline void init_IO_APIC_traps(void) { @@ -2135,11 +2020,6 @@ static inline void init_IO_APIC_traps(void) */ for (irq = 0; irq < NR_IRQS ; irq++) { int tmp = irq; - if (use_pci_vector()) { - if (!platform_legacy_irq(tmp)) - if ((tmp = vector_to_irq(tmp)) == -1) - continue; - } if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) { /* * Hmm.. We don't have an entry for this, @@ -2150,20 +2030,21 @@ static inline void init_IO_APIC_traps(void) make_8259A_irq(irq); else /* Strange. Oh, well.. */ - irq_desc[irq].chip = &no_irq_type; + irq_desc[irq].chip = &no_irq_chip; } } } -static void enable_lapic_irq (unsigned int irq) -{ - unsigned long v; +/* + * The local APIC irq-chip implementation: + */ - v = apic_read(APIC_LVT0); - apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); +static void ack_apic(unsigned int irq) +{ + ack_APIC_irq(); } -static void disable_lapic_irq (unsigned int irq) +static void mask_lapic_irq (unsigned int irq) { unsigned long v; @@ -2171,21 +2052,19 @@ static void disable_lapic_irq (unsigned int irq) apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); } -static void ack_lapic_irq (unsigned int irq) +static void unmask_lapic_irq (unsigned int irq) { - ack_APIC_irq(); -} + unsigned long v; -static void end_lapic_irq (unsigned int i) { /* nothing */ } + v = apic_read(APIC_LVT0); + apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); +} -static struct hw_interrupt_type lapic_irq_type __read_mostly = { - .typename = "local-APIC-edge", - .startup = NULL, /* startup_irq() not used for IRQ0 */ - .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */ - .enable = enable_lapic_irq, - .disable = disable_lapic_irq, - .ack = ack_lapic_irq, - .end = end_lapic_irq +static struct irq_chip lapic_chip __read_mostly = { + .name = "local-APIC-edge", + .mask = mask_lapic_irq, + .unmask = unmask_lapic_irq, + .eoi = ack_apic, }; static void setup_nmi (void) @@ -2356,7 +2235,7 @@ static inline void check_timer(void) printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); disable_8259A_irq(0); - irq_desc[0].chip = &lapic_irq_type; + set_irq_chip_and_handler(0, &lapic_chip, handle_fasteoi_irq); apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ enable_8259A_irq(0); @@ -2531,6 +2410,238 @@ static int __init ioapic_init_sysfs(void) device_initcall(ioapic_init_sysfs); +/* + * Dynamic irq allocate and deallocation + */ +int create_irq(void) +{ + /* Allocate an unused irq */ + int irq, new, vector; + unsigned long flags; + + irq = -ENOSPC; + spin_lock_irqsave(&vector_lock, flags); + for (new = (NR_IRQS - 1); new >= 0; new--) { + if (platform_legacy_irq(new)) + continue; + if (irq_vector[new] != 0) + continue; + vector = __assign_irq_vector(new); + if (likely(vector > 0)) + irq = new; + break; + } + spin_unlock_irqrestore(&vector_lock, flags); + + if (irq >= 0) { + set_intr_gate(vector, interrupt[irq]); + dynamic_irq_init(irq); + } + return irq; +} + +void destroy_irq(unsigned int irq) +{ + unsigned long flags; + + dynamic_irq_cleanup(irq); + + spin_lock_irqsave(&vector_lock, flags); + irq_vector[irq] = 0; + spin_unlock_irqrestore(&vector_lock, flags); +} + +/* + * MSI mesage composition + */ +#ifdef CONFIG_PCI_MSI +static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) +{ + int vector; + unsigned dest; + + vector = assign_irq_vector(irq); + if (vector >= 0) { + dest = cpu_mask_to_apicid(TARGET_CPUS); + + msg->address_hi = MSI_ADDR_BASE_HI; + msg->address_lo = + MSI_ADDR_BASE_LO | + ((INT_DEST_MODE == 0) ? + MSI_ADDR_DEST_MODE_PHYSICAL: + MSI_ADDR_DEST_MODE_LOGICAL) | + ((INT_DELIVERY_MODE != dest_LowestPrio) ? + MSI_ADDR_REDIRECTION_CPU: + MSI_ADDR_REDIRECTION_LOWPRI) | + MSI_ADDR_DEST_ID(dest); + + msg->data = + MSI_DATA_TRIGGER_EDGE | + MSI_DATA_LEVEL_ASSERT | + ((INT_DELIVERY_MODE != dest_LowestPrio) ? + MSI_DATA_DELIVERY_FIXED: + MSI_DATA_DELIVERY_LOWPRI) | + MSI_DATA_VECTOR(vector); + } + return vector; +} + +#ifdef CONFIG_SMP +static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) +{ + struct msi_msg msg; + unsigned int dest; + cpumask_t tmp; + int vector; + + cpus_and(tmp, mask, cpu_online_map); + if (cpus_empty(tmp)) + tmp = TARGET_CPUS; + + vector = assign_irq_vector(irq); + if (vector < 0) + return; + + dest = cpu_mask_to_apicid(mask); + + read_msi_msg(irq, &msg); + + msg.data &= ~MSI_DATA_VECTOR_MASK; + msg.data |= MSI_DATA_VECTOR(vector); + msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; + msg.address_lo |= MSI_ADDR_DEST_ID(dest); + + write_msi_msg(irq, &msg); + set_native_irq_info(irq, mask); +} +#endif /* CONFIG_SMP */ + +/* + * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, + * which implement the MSI or MSI-X Capability Structure. + */ +static struct irq_chip msi_chip = { + .name = "PCI-MSI", + .unmask = unmask_msi_irq, + .mask = mask_msi_irq, + .ack = ack_ioapic_irq, +#ifdef CONFIG_SMP + .set_affinity = set_msi_irq_affinity, +#endif + .retrigger = ioapic_retrigger_irq, +}; + +int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev) +{ + struct msi_msg msg; + int ret; + ret = msi_compose_msg(dev, irq, &msg); + if (ret < 0) + return ret; + + write_msi_msg(irq, &msg); + + set_irq_chip_and_handler(irq, &msi_chip, handle_edge_irq); + + return 0; +} + +void arch_teardown_msi_irq(unsigned int irq) +{ + return; +} + +#endif /* CONFIG_PCI_MSI */ + +/* + * Hypertransport interrupt support + */ +#ifdef CONFIG_HT_IRQ + +#ifdef CONFIG_SMP + +static void target_ht_irq(unsigned int irq, unsigned int dest) +{ + u32 low, high; + low = read_ht_irq_low(irq); + high = read_ht_irq_high(irq); + + low &= ~(HT_IRQ_LOW_DEST_ID_MASK); + high &= ~(HT_IRQ_HIGH_DEST_ID_MASK); + + low |= HT_IRQ_LOW_DEST_ID(dest); + high |= HT_IRQ_HIGH_DEST_ID(dest); + + write_ht_irq_low(irq, low); + write_ht_irq_high(irq, high); +} + +static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) +{ + unsigned int dest; + cpumask_t tmp; + + cpus_and(tmp, mask, cpu_online_map); + if (cpus_empty(tmp)) + tmp = TARGET_CPUS; + + cpus_and(mask, tmp, CPU_MASK_ALL); + + dest = cpu_mask_to_apicid(mask); + + target_ht_irq(irq, dest); + set_native_irq_info(irq, mask); +} +#endif + +static struct hw_interrupt_type ht_irq_chip = { + .name = "PCI-HT", + .mask = mask_ht_irq, + .unmask = unmask_ht_irq, + .ack = ack_ioapic_irq, +#ifdef CONFIG_SMP + .set_affinity = set_ht_irq_affinity, +#endif + .retrigger = ioapic_retrigger_irq, +}; + +int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) +{ + int vector; + + vector = assign_irq_vector(irq); + if (vector >= 0) { + u32 low, high; + unsigned dest; + cpumask_t tmp; + + cpus_clear(tmp); + cpu_set(vector >> 8, tmp); + dest = cpu_mask_to_apicid(tmp); + + high = HT_IRQ_HIGH_DEST_ID(dest); + + low = HT_IRQ_LOW_BASE | + HT_IRQ_LOW_DEST_ID(dest) | + HT_IRQ_LOW_VECTOR(vector) | + ((INT_DEST_MODE == 0) ? + HT_IRQ_LOW_DM_PHYSICAL : + HT_IRQ_LOW_DM_LOGICAL) | + HT_IRQ_LOW_RQEOI_EDGE | + ((INT_DELIVERY_MODE != dest_LowestPrio) ? + HT_IRQ_LOW_MT_FIXED : + HT_IRQ_LOW_MT_ARBITRATED) | + HT_IRQ_LOW_IRQ_MASKED; + + write_ht_irq_low(irq, low); + write_ht_irq_high(irq, high); + + set_irq_chip_and_handler(irq, &ht_irq_chip, handle_edge_irq); + } + return vector; +} +#endif /* CONFIG_HT_IRQ */ + /* -------------------------------------------------------------------------- ACPI-based IOAPIC Configuration -------------------------------------------------------------------------- */ @@ -2684,7 +2795,7 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int a ioapic_write_entry(ioapic, pin, entry); spin_lock_irqsave(&ioapic_lock, flags); - set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS); + set_native_irq_info(irq, TARGET_CPUS); spin_unlock_irqrestore(&ioapic_lock, flags); return 0; diff --git a/arch/i386/kernel/irq.c b/arch/i386/kernel/irq.c index 5fe547c..3dd2e18 100644 --- a/arch/i386/kernel/irq.c +++ b/arch/i386/kernel/irq.c @@ -55,6 +55,7 @@ fastcall unsigned int do_IRQ(struct pt_regs *regs) { /* high bit used in ret_from_ code */ int irq = ~regs->orig_eax; + struct irq_desc *desc = irq_desc + irq; #ifdef CONFIG_4KSTACKS union irq_ctx *curctx, *irqctx; u32 *isp; @@ -94,7 +95,7 @@ fastcall unsigned int do_IRQ(struct pt_regs *regs) * current stack (which is the irq stack already after all) */ if (curctx != irqctx) { - int arg1, arg2, ebx; + int arg1, arg2, arg3, ebx; /* build the stack frame on the IRQ stack */ isp = (u32*) ((char*)irqctx + sizeof(*irqctx)); @@ -110,16 +111,17 @@ fastcall unsigned int do_IRQ(struct pt_regs *regs) (curctx->tinfo.preempt_count & SOFTIRQ_MASK); asm volatile( - " xchgl %%ebx,%%esp \n" - " call __do_IRQ \n" + " xchgl %%ebx,%%esp \n" + " call *%%edi \n" " movl %%ebx,%%esp \n" - : "=a" (arg1), "=d" (arg2), "=b" (ebx) - : "0" (irq), "1" (regs), "2" (isp) - : "memory", "cc", "ecx" + : "=a" (arg1), "=d" (arg2), "=c" (arg3), "=b" (ebx) + : "0" (irq), "1" (desc), "2" (regs), "3" (isp), + "D" (desc->handle_irq) + : "memory", "cc" ); } else #endif - __do_IRQ(irq, regs); + desc->handle_irq(irq, desc, regs); irq_exit(); @@ -253,7 +255,8 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); #endif - seq_printf(p, " %14s", irq_desc[i].chip->typename); + seq_printf(p, " %8s", irq_desc[i].chip->name); + seq_printf(p, "-%s", handle_irq_name(irq_desc[i].handle_irq)); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) diff --git a/arch/i386/kernel/ldt.c b/arch/i386/kernel/ldt.c index 983f957..445211e 100644 --- a/arch/i386/kernel/ldt.c +++ b/arch/i386/kernel/ldt.c @@ -1,5 +1,5 @@ /* - * linux/kernel/ldt.c + * linux/arch/i386/kernel/ldt.c * * Copyright (C) 1992 Krishna Balasubramanian and Linus Torvalds * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> diff --git a/arch/i386/kernel/smpboot.c b/arch/i386/kernel/smpboot.c index 9d93ecf..4bb8b77 100644 --- a/arch/i386/kernel/smpboot.c +++ b/arch/i386/kernel/smpboot.c @@ -648,7 +648,7 @@ static void map_cpu_to_logical_apicid(void) { int cpu = smp_processor_id(); int apicid = logical_smp_processor_id(); - int node = apicid_to_node(hard_smp_processor_id()); + int node = apicid_to_node(apicid); if (!node_online(node)) node = first_online_node; diff --git a/arch/i386/mach-visws/visws_apic.c b/arch/i386/mach-visws/visws_apic.c index 8285225..5929f884 100644 --- a/arch/i386/mach-visws/visws_apic.c +++ b/arch/i386/mach-visws/visws_apic.c @@ -1,5 +1,5 @@ /* - * linux/arch/i386/mach_visws/visws_apic.c + * linux/arch/i386/mach-visws/visws_apic.c * * Copyright (C) 1999 Bent Hagemark, Ingo Molnar * diff --git a/arch/i386/mm/discontig.c b/arch/i386/mm/discontig.c index 51e3739..455597d 100644 --- a/arch/i386/mm/discontig.c +++ b/arch/i386/mm/discontig.c @@ -153,8 +153,7 @@ static void __init find_max_pfn_node(int nid) */ if (node_start_pfn[nid] > max_pfn) node_start_pfn[nid] = max_pfn; - if (node_start_pfn[nid] > node_end_pfn[nid]) - BUG(); + BUG_ON(node_start_pfn[nid] > node_end_pfn[nid]); } /* diff --git a/arch/i386/mm/init.c b/arch/i386/mm/init.c index 90089c1..1674161 100644 --- a/arch/i386/mm/init.c +++ b/arch/i386/mm/init.c @@ -569,8 +569,7 @@ void __init mem_init(void) int bad_ppro; #ifdef CONFIG_FLATMEM - if (!mem_map) - BUG(); + BUG_ON(!mem_map); #endif bad_ppro = ppro_with_ram_bug(); diff --git a/arch/i386/pci/fixup.c b/arch/i386/pci/fixup.c index 83c3645..b60d7e8 100644 --- a/arch/i386/pci/fixup.c +++ b/arch/i386/pci/fixup.c @@ -393,7 +393,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video); * We pretend to bring them out of full D3 state, and restore the proper * IRQ, PCI cache line size, and BARs, otherwise the device won't function * properly. In some cases, the device will generate an interrupt on - * the wrong IRQ line, causing any devices sharing the the line it's + * the wrong IRQ line, causing any devices sharing the line it's * *supposed* to use to be disabled by the kernel's IRQ debug code. */ static u16 toshiba_line_size; diff --git a/arch/i386/pci/irq.c b/arch/i386/pci/irq.c index 4a8995c..47f02af 100644 --- a/arch/i386/pci/irq.c +++ b/arch/i386/pci/irq.c @@ -981,10 +981,6 @@ static void __init pcibios_fixup_irqs(void) pci_name(bridge), 'A' + pin, irq); } if (irq >= 0) { - if (use_pci_vector() && - !platform_legacy_irq(irq)) - irq = IO_APIC_VECTOR(irq); - printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n", pci_name(dev), 'A' + pin, irq); dev->irq = irq; @@ -1169,33 +1165,3 @@ static int pirq_enable_irq(struct pci_dev *dev) } return 0; } - -int pci_vector_resources(int last, int nr_released) -{ - int count = nr_released; - - int next = last; - int offset = (last % 8); - - while (next < FIRST_SYSTEM_VECTOR) { - next += 8; -#ifdef CONFIG_X86_64 - if (next == IA32_SYSCALL_VECTOR) - continue; -#else - if (next == SYSCALL_VECTOR) - continue; -#endif - count++; - if (next >= FIRST_SYSTEM_VECTOR) { - if (offset%8) { - next = FIRST_DEVICE_VECTOR + offset; - offset++; - continue; - } - count--; - } - } - - return count; -} diff --git a/arch/ia64/kernel/Makefile b/arch/ia64/kernel/Makefile index 3149749..cfa099b 100644 --- a/arch/ia64/kernel/Makefile +++ b/arch/ia64/kernel/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_IA64_MCA_RECOVERY) += mca_recovery.o obj-$(CONFIG_KPROBES) += kprobes.o jprobes.o obj-$(CONFIG_IA64_UNCACHED_ALLOCATOR) += uncached.o obj-$(CONFIG_AUDIT) += audit.o +obj-$(CONFIG_PCI_MSI) += msi_ia64.o mca_recovery-y += mca_drv.o mca_drv_asm.o obj-$(CONFIG_IA64_ESI) += esi.o diff --git a/arch/ia64/kernel/acpi-processor.c b/arch/ia64/kernel/acpi-processor.c index e683630..4d4993a 100644 --- a/arch/ia64/kernel/acpi-processor.c +++ b/arch/ia64/kernel/acpi-processor.c @@ -1,5 +1,5 @@ /* - * arch/ia64/kernel/cpufreq/processor.c + * arch/ia64/kernel/acpi-processor.c * * Copyright (C) 2005 Intel Corporation * Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S index e5b1be5..3390b7c 100644 --- a/arch/ia64/kernel/entry.S +++ b/arch/ia64/kernel/entry.S @@ -1,5 +1,5 @@ /* - * ia64/kernel/entry.S + * arch/ia64/kernel/entry.S * * Kernel entry points. * diff --git a/arch/ia64/kernel/irq_ia64.c b/arch/ia64/kernel/irq_ia64.c index a041367..ab2d19c 100644 --- a/arch/ia64/kernel/irq_ia64.c +++ b/arch/ia64/kernel/irq_ia64.c @@ -1,5 +1,5 @@ /* - * linux/arch/ia64/kernel/irq.c + * linux/arch/ia64/kernel/irq_ia64.c * * Copyright (C) 1998-2001 Hewlett-Packard Co * Stephane Eranian <eranian@hpl.hp.com> @@ -30,6 +30,7 @@ #include <linux/smp_lock.h> #include <linux/threads.h> #include <linux/bitops.h> +#include <linux/irq.h> #include <asm/delay.h> #include <asm/intrinsics.h> @@ -105,6 +106,25 @@ reserve_irq_vector (int vector) return test_and_set_bit(pos, ia64_vector_mask); } +/* + * Dynamic irq allocate and deallocation for MSI + */ +int create_irq(void) +{ + int vector = assign_irq_vector(AUTO_ASSIGN); + + if (vector >= 0) + dynamic_irq_init(vector); + + return vector; +} + +void destroy_irq(unsigned int irq) +{ + dynamic_irq_cleanup(irq); + free_irq_vector(irq); +} + #ifdef CONFIG_SMP # define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE) #else diff --git a/arch/ia64/kernel/msi_ia64.c b/arch/ia64/kernel/msi_ia64.c new file mode 100644 index 0000000..822e59a --- /dev/null +++ b/arch/ia64/kernel/msi_ia64.c @@ -0,0 +1,143 @@ +/* + * MSI hooks for standard x86 apic + */ + +#include <linux/pci.h> +#include <linux/irq.h> +#include <linux/msi.h> +#include <asm/smp.h> + +/* + * Shifts for APIC-based data + */ + +#define MSI_DATA_VECTOR_SHIFT 0 +#define MSI_DATA_VECTOR(v) (((u8)v) << MSI_DATA_VECTOR_SHIFT) + +#define MSI_DATA_DELIVERY_SHIFT 8 +#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_SHIFT) +#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_SHIFT) + +#define MSI_DATA_LEVEL_SHIFT 14 +#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT) +#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT) + +#define MSI_DATA_TRIGGER_SHIFT 15 +#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT) +#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT) + +/* + * Shift/mask fields for APIC-based bus address + */ + +#define MSI_TARGET_CPU_SHIFT 4 +#define MSI_ADDR_HEADER 0xfee00000 + +#define MSI_ADDR_DESTID_MASK 0xfff0000f +#define MSI_ADDR_DESTID_CPU(cpu) ((cpu) << MSI_TARGET_CPU_SHIFT) + +#define MSI_ADDR_DESTMODE_SHIFT 2 +#define MSI_ADDR_DESTMODE_PHYS (0 << MSI_ADDR_DESTMODE_SHIFT) +#define MSI_ADDR_DESTMODE_LOGIC (1 << MSI_ADDR_DESTMODE_SHIFT) + +#define MSI_ADDR_REDIRECTION_SHIFT 3 +#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) +#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) + +static struct irq_chip ia64_msi_chip; + +#ifdef CONFIG_SMP +static void ia64_set_msi_irq_affinity(unsigned int irq, cpumask_t cpu_mask) +{ + struct msi_msg msg; + u32 addr; + + read_msi_msg(irq, &msg); + + addr = msg.address_lo; + addr &= MSI_ADDR_DESTID_MASK; + addr |= MSI_ADDR_DESTID_CPU(cpu_physical_id(first_cpu(cpu_mask))); + msg.address_lo = addr; + + write_msi_msg(irq, &msg); + set_native_irq_info(irq, cpu_mask); +} +#endif /* CONFIG_SMP */ + +int ia64_setup_msi_irq(unsigned int irq, struct pci_dev *pdev) +{ + struct msi_msg msg; + unsigned long dest_phys_id; + unsigned int vector; + + dest_phys_id = cpu_physical_id(first_cpu(cpu_online_map)); + vector = irq; + + msg.address_hi = 0; + msg.address_lo = + MSI_ADDR_HEADER | + MSI_ADDR_DESTMODE_PHYS | + MSI_ADDR_REDIRECTION_CPU | + MSI_ADDR_DESTID_CPU(dest_phys_id); + + msg.data = + MSI_DATA_TRIGGER_EDGE | + MSI_DATA_LEVEL_ASSERT | + MSI_DATA_DELIVERY_FIXED | + MSI_DATA_VECTOR(vector); + + write_msi_msg(irq, &msg); + set_irq_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq); + + return 0; +} + +void ia64_teardown_msi_irq(unsigned int irq) +{ + return; /* no-op */ +} + +static void ia64_ack_msi_irq(unsigned int irq) +{ + move_native_irq(irq); + ia64_eoi(); +} + +static int ia64_msi_retrigger_irq(unsigned int irq) +{ + unsigned int vector = irq; + ia64_resend_irq(vector); + + return 1; +} + +/* + * Generic ops used on most IA64 platforms. + */ +static struct irq_chip ia64_msi_chip = { + .name = "PCI-MSI", + .mask = mask_msi_irq, + .unmask = unmask_msi_irq, + .ack = ia64_ack_msi_irq, +#ifdef CONFIG_SMP + .set_affinity = ia64_set_msi_irq_affinity, +#endif + .retrigger = ia64_msi_retrigger_irq, +}; + + +int arch_setup_msi_irq(unsigned int irq, struct pci_dev *pdev) +{ + if (platform_setup_msi_irq) + return platform_setup_msi_irq(irq, pdev); + + return ia64_setup_msi_irq(irq, pdev); +} + +void arch_teardown_msi_irq(unsigned int irq) +{ + if (platform_teardown_msi_irq) + return platform_teardown_msi_irq(irq); + + return ia64_teardown_msi_irq(irq); +} diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c index 15c7c67..b30be7c 100644 --- a/arch/ia64/pci/pci.c +++ b/arch/ia64/pci/pci.c @@ -810,12 +810,3 @@ pcibios_prep_mwi (struct pci_dev *dev) } return rc; } - -int pci_vector_resources(int last, int nr_released) -{ - int count = nr_released; - - count += (IA64_LAST_DEVICE_VECTOR - last); - - return count; -} diff --git a/arch/ia64/sn/kernel/Makefile b/arch/ia64/sn/kernel/Makefile index ab9c48c..2d78f34 100644 --- a/arch/ia64/sn/kernel/Makefile +++ b/arch/ia64/sn/kernel/Makefile @@ -19,3 +19,4 @@ xp-y := xp_main.o xp_nofault.o obj-$(CONFIG_IA64_SGI_SN_XP) += xpc.o xpc-y := xpc_main.o xpc_channel.o xpc_partition.o obj-$(CONFIG_IA64_SGI_SN_XP) += xpnet.o +obj-$(CONFIG_PCI_MSI) += msi_sn.o diff --git a/arch/ia64/sn/kernel/msi_sn.c b/arch/ia64/sn/kernel/msi_sn.c new file mode 100644 index 0000000..6ffd1f8 --- /dev/null +++ b/arch/ia64/sn/kernel/msi_sn.c @@ -0,0 +1,230 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 Silicon Graphics, Inc. All Rights Reserved. + */ + +#include <linux/types.h> +#include <linux/irq.h> +#include <linux/pci.h> +#include <linux/cpumask.h> +#include <linux/msi.h> + +#include <asm/sn/addrs.h> +#include <asm/sn/intr.h> +#include <asm/sn/pcibus_provider_defs.h> +#include <asm/sn/pcidev.h> +#include <asm/sn/nodepda.h> + +struct sn_msi_info { + u64 pci_addr; + struct sn_irq_info *sn_irq_info; +}; + +static struct sn_msi_info sn_msi_info[NR_IRQS]; + +static struct irq_chip sn_msi_chip; + +void sn_teardown_msi_irq(unsigned int irq) +{ + nasid_t nasid; + int widget; + struct pci_dev *pdev; + struct pcidev_info *sn_pdev; + struct sn_irq_info *sn_irq_info; + struct pcibus_bussoft *bussoft; + struct sn_pcibus_provider *provider; + + sn_irq_info = sn_msi_info[irq].sn_irq_info; + if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0) + return; + + sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; + pdev = sn_pdev->pdi_linux_pcidev; + provider = SN_PCIDEV_BUSPROVIDER(pdev); + + (*provider->dma_unmap)(pdev, + sn_msi_info[irq].pci_addr, + PCI_DMA_FROMDEVICE); + sn_msi_info[irq].pci_addr = 0; + + bussoft = SN_PCIDEV_BUSSOFT(pdev); + nasid = NASID_GET(bussoft->bs_base); + widget = (nasid & 1) ? + TIO_SWIN_WIDGETNUM(bussoft->bs_base) : + SWIN_WIDGETNUM(bussoft->bs_base); + + sn_intr_free(nasid, widget, sn_irq_info); + sn_msi_info[irq].sn_irq_info = NULL; + + return; +} + +int sn_setup_msi_irq(unsigned int irq, struct pci_dev *pdev) +{ + struct msi_msg msg; + struct msi_desc *entry; + int widget; + int status; + nasid_t nasid; + u64 bus_addr; + struct sn_irq_info *sn_irq_info; + struct pcibus_bussoft *bussoft = SN_PCIDEV_BUSSOFT(pdev); + struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); + + entry = get_irq_data(irq); + if (!entry->msi_attrib.is_64) + return -EINVAL; + + if (bussoft == NULL) + return -EINVAL; + + if (provider == NULL || provider->dma_map_consistent == NULL) + return -EINVAL; + + /* + * Set up the vector plumbing. Let the prom (via sn_intr_alloc) + * decide which cpu to direct this msi at by default. + */ + + nasid = NASID_GET(bussoft->bs_base); + widget = (nasid & 1) ? + TIO_SWIN_WIDGETNUM(bussoft->bs_base) : + SWIN_WIDGETNUM(bussoft->bs_base); + + sn_irq_info = kzalloc(sizeof(struct sn_irq_info), GFP_KERNEL); + if (! sn_irq_info) + return -ENOMEM; + + status = sn_intr_alloc(nasid, widget, sn_irq_info, irq, -1, -1); + if (status) { + kfree(sn_irq_info); + return -ENOMEM; + } + + sn_irq_info->irq_int_bit = -1; /* mark this as an MSI irq */ + sn_irq_fixup(pdev, sn_irq_info); + + /* Prom probably should fill these in, but doesn't ... */ + sn_irq_info->irq_bridge_type = bussoft->bs_asic_type; + sn_irq_info->irq_bridge = (void *)bussoft->bs_base; + + /* + * Map the xio address into bus space + */ + bus_addr = (*provider->dma_map_consistent)(pdev, + sn_irq_info->irq_xtalkaddr, + sizeof(sn_irq_info->irq_xtalkaddr), + SN_DMA_MSI|SN_DMA_ADDR_XIO); + if (! bus_addr) { + sn_intr_free(nasid, widget, sn_irq_info); + kfree(sn_irq_info); + return -ENOMEM; + } + + sn_msi_info[irq].sn_irq_info = sn_irq_info; + sn_msi_info[irq].pci_addr = bus_addr; + + msg.address_hi = (u32)(bus_addr >> 32); + msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff); + + /* + * In the SN platform, bit 16 is a "send vector" bit which + * must be present in order to move the vector through the system. + */ + msg.data = 0x100 + irq; + +#ifdef CONFIG_SMP + set_irq_affinity_info(irq, sn_irq_info->irq_cpuid, 0); +#endif + + write_msi_msg(irq, &msg); + set_irq_chip_and_handler(irq, &sn_msi_chip, handle_edge_irq); + + return 0; +} + +#ifdef CONFIG_SMP +static void sn_set_msi_irq_affinity(unsigned int irq, cpumask_t cpu_mask) +{ + struct msi_msg msg; + int slice; + nasid_t nasid; + u64 bus_addr; + struct pci_dev *pdev; + struct pcidev_info *sn_pdev; + struct sn_irq_info *sn_irq_info; + struct sn_irq_info *new_irq_info; + struct sn_pcibus_provider *provider; + unsigned int cpu; + + cpu = first_cpu(cpu_mask); + sn_irq_info = sn_msi_info[irq].sn_irq_info; + if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0) + return; + + /* + * Release XIO resources for the old MSI PCI address + */ + + read_msi_msg(irq, &msg); + sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; + pdev = sn_pdev->pdi_linux_pcidev; + provider = SN_PCIDEV_BUSPROVIDER(pdev); + + bus_addr = (u64)(msg.address_hi) << 32 | (u64)(msg.address_lo); + (*provider->dma_unmap)(pdev, bus_addr, PCI_DMA_FROMDEVICE); + sn_msi_info[irq].pci_addr = 0; + + nasid = cpuid_to_nasid(cpu); + slice = cpuid_to_slice(cpu); + + new_irq_info = sn_retarget_vector(sn_irq_info, nasid, slice); + sn_msi_info[irq].sn_irq_info = new_irq_info; + if (new_irq_info == NULL) + return; + + /* + * Map the xio address into bus space + */ + + bus_addr = (*provider->dma_map_consistent)(pdev, + new_irq_info->irq_xtalkaddr, + sizeof(new_irq_info->irq_xtalkaddr), + SN_DMA_MSI|SN_DMA_ADDR_XIO); + + sn_msi_info[irq].pci_addr = bus_addr; + msg.address_hi = (u32)(bus_addr >> 32); + msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff); + + write_msi_msg(irq, &msg); + set_native_irq_info(irq, cpu_mask); +} +#endif /* CONFIG_SMP */ + +static void sn_ack_msi_irq(unsigned int irq) +{ + move_native_irq(irq); + ia64_eoi(); +} + +static int sn_msi_retrigger_irq(unsigned int irq) +{ + unsigned int vector = irq; + ia64_resend_irq(vector); + + return 1; +} + +static struct irq_chip sn_msi_chip = { + .name = "PCI-MSI", + .mask = mask_msi_irq, + .unmask = unmask_msi_irq, + .ack = sn_ack_msi_irq, +#ifdef CONFIG_SMP + .set_affinity = sn_set_msi_irq_affinity, +#endif + .retrigger = sn_msi_retrigger_irq, +}; diff --git a/arch/ia64/sn/kernel/xpnet.c b/arch/ia64/sn/kernel/xpnet.c index 007703c..c8173db 100644 --- a/arch/ia64/sn/kernel/xpnet.c +++ b/arch/ia64/sn/kernel/xpnet.c @@ -225,7 +225,7 @@ xpnet_receive(partid_t partid, int channel, struct xpnet_message *msg) skb_put(skb, (msg->size - msg->leadin_ignore - msg->tailout_ignore)); /* - * Move the data over from the the other side. + * Move the data over from the other side. */ if ((XPNET_VERSION_MINOR(msg->version) == 1) && (msg->embedded_bytes != 0)) { diff --git a/arch/m68k/mm/motorola.c b/arch/m68k/mm/motorola.c index 49015e3..afcccdc 100644 --- a/arch/m68k/mm/motorola.c +++ b/arch/m68k/mm/motorola.c @@ -1,5 +1,5 @@ /* - * linux/arch/m68k/motorola.c + * linux/arch/m68k/mm/motorola.c * * Routines specific to the Motorola MMU, originally from: * linux/arch/m68k/init.c diff --git a/arch/m68k/sun3/sun3dvma.c b/arch/m68k/sun3/sun3dvma.c index 6c26522..a2bc2da 100644 --- a/arch/m68k/sun3/sun3dvma.c +++ b/arch/m68k/sun3/sun3dvma.c @@ -1,5 +1,5 @@ /* - * linux/arch/m68k/mm/sun3dvma.c + * linux/arch/m68k/sun3/sun3dvma.c * * Copyright (C) 2000 Sam Creasey * diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index e767f2d..6d920d4 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -161,8 +161,8 @@ config CLOCK_FREQ frequency, it may or may not be the same as the external clock crystal fitted to your board. Some processors have an internal PLL and can have their frequency programmed at run time, others - use internal dividers. In gernal the kernel won't setup a PLL - if it is fitted (there are some expections). This value will be + use internal dividers. In general the kernel won't setup a PLL + if it is fitted (there are some exceptions). This value will be specific to the exact CPU that you are using. config CLOCK_DIV @@ -495,7 +495,7 @@ config VECTORBASE hex "Address of the base of system vectors" default "0" help - Define the address of the the system vectors. Commonly this is + Define the address of the system vectors. Commonly this is put at the start of RAM, but it doesn't have to be. On ColdFire platforms this address is programmed into the VBR register, thus actually setting the address to use. diff --git a/arch/m68knommu/platform/68328/head-pilot.S b/arch/m68knommu/platform/68328/head-pilot.S index 9e07faa..aecff53 100644 --- a/arch/m68knommu/platform/68328/head-pilot.S +++ b/arch/m68knommu/platform/68328/head-pilot.S @@ -1,5 +1,5 @@ /* - * linux/arch/m68knommu/platform/68328/head-rom.S + * linux/arch/m68knommu/platform/68328/head-pilot.S * - A startup file for the MC68328 * * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, diff --git a/arch/mips/dec/prom/call_o32.S b/arch/mips/dec/prom/call_o32.S index 0dd56db..e523454 100644 --- a/arch/mips/dec/prom/call_o32.S +++ b/arch/mips/dec/prom/call_o32.S @@ -1,5 +1,5 @@ /* - * arch/mips/dec/call_o32.S + * arch/mips/dec/prom/call_o32.S * * O32 interface for the 64 (or N32) ABI. * diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 375e099..6f8b25c 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1211,7 +1211,7 @@ static void __init build_r4000_tlb_refill_handler(void) * Overflow check: For the 64bit handler, we need at least one * free instruction slot for the wrap-around branch. In worst * case, if the intended insertion point is a delay slot, we - * need three, with the the second nop'ed and the third being + * need three, with the second nop'ed and the third being * unused. */ #ifdef CONFIG_32BIT diff --git a/arch/mips/pci/fixup-vr4133.c b/arch/mips/pci/fixup-vr4133.c index 8e01d0c..597b897 100644 --- a/arch/mips/pci/fixup-vr4133.c +++ b/arch/mips/pci/fixup-vr4133.c @@ -1,5 +1,5 @@ /* - * arch/mips/vr41xx/nec-cmbvr4133/pci_fixup.c + * arch/mips/pci/fixup-vr4133.c * * The NEC CMB-VR4133 Board specific PCI fixups. * diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c index dc30d66..cbfb342 100644 --- a/arch/mips/tx4938/common/irq.c +++ b/arch/mips/tx4938/common/irq.c @@ -1,5 +1,5 @@ /* - * linux/arch/mps/tx4938/common/irq.c + * linux/arch/mips/tx4938/common/irq.c * * Common tx4938 irq handler * Copyright (C) 2000-2001 Toshiba Corporation diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index 95c1b8e..192357a 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -941,8 +941,8 @@ syscall_exit_rfi: * to "proper" values now (otherwise we'll wind up restoring * whatever was last stored in the task structure, which might * be inconsistent if an interrupt occured while on the gateway - * page) Note that we may be "trashing" values the user put in - * them, but we don't support the the user changing them. + * page). Note that we may be "trashing" values the user put in + * them, but we don't support the user changing them. */ STREG %r0,PT_SR2(%r16) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 2587468..8b69104 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -1013,7 +1013,7 @@ config CONSISTENT_START_BOOL depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE help This option allows you to set the base virtual address - of the the consistent memory pool. This pool of virtual + of the consistent memory pool. This pool of virtual memory is used to make consistent memory allocations. config CONSISTENT_START @@ -1024,7 +1024,7 @@ config CONSISTENT_SIZE_BOOL bool "Set custom consistent memory pool size" depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE help - This option allows you to set the size of the the + This option allows you to set the size of the consistent memory pool. This pool of virtual memory is used to make consistent memory allocations. diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index c383d56..003520b 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -113,7 +113,7 @@ endif endif quiet_cmd_wrap = WRAP $@ - cmd_wrap =$(wrapper) -c -o $@ -p $2 $(CROSSWRAP) vmlinux + cmd_wrap =$(CONFIG_SHELL) $(wrapper) -c -o $@ -p $2 $(CROSSWRAP) vmlinux quiet_cmd_wrap_initrd = WRAP $@ cmd_wrap_initrd =$(wrapper) -c -o $@ -p $2 $(CROSSWRAP) \ -i $(obj)/ramdisk.image.gz vmlinux diff --git a/arch/powerpc/kernel/perfmon_fsl_booke.c b/arch/powerpc/kernel/perfmon_fsl_booke.c index bdc3977..e0dcf2b 100644 --- a/arch/powerpc/kernel/perfmon_fsl_booke.c +++ b/arch/powerpc/kernel/perfmon_fsl_booke.c @@ -1,4 +1,4 @@ -/* kernel/perfmon_fsl_booke.c +/* arch/powerpc/kernel/perfmon_fsl_booke.c * Freescale Book-E Performance Monitor code * * Author: Andy Fleming diff --git a/arch/powerpc/oprofile/op_model_7450.c b/arch/powerpc/oprofile/op_model_7450.c index e0491c3..d8ee3ae 100644 --- a/arch/powerpc/oprofile/op_model_7450.c +++ b/arch/powerpc/oprofile/op_model_7450.c @@ -1,5 +1,5 @@ /* - * oprofile/op_model_7450.c + * arch/powerpc/oprofile/op_model_7450.c * * Freescale 745x/744x oprofile support, based on fsl_booke support * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM diff --git a/arch/powerpc/oprofile/op_model_fsl_booke.c b/arch/powerpc/oprofile/op_model_fsl_booke.c index 93d63e6..e29dede 100644 --- a/arch/powerpc/oprofile/op_model_fsl_booke.c +++ b/arch/powerpc/oprofile/op_model_fsl_booke.c @@ -1,5 +1,5 @@ /* - * oprofile/op_model_e500.c + * arch/powerpc/oprofile/op_model_fsl_booke.c * * Freescale Book-E oprofile support, based on ppc64 oprofile support * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM diff --git a/arch/powerpc/platforms/83xx/mpc834x_sys.h b/arch/powerpc/platforms/83xx/mpc834x_sys.h index fedecb7..7d5bbef 100644 --- a/arch/powerpc/platforms/83xx/mpc834x_sys.h +++ b/arch/powerpc/platforms/83xx/mpc834x_sys.h @@ -1,5 +1,5 @@ /* - * arch/powerppc/platforms/83xx/mpc834x_sys.h + * arch/powerpc/platforms/83xx/mpc834x_sys.h * * MPC834X SYS common board definitions * diff --git a/arch/powerpc/platforms/85xx/mpc8540_ads.h b/arch/powerpc/platforms/85xx/mpc8540_ads.h index c0d56d2..da82f4c 100644 --- a/arch/powerpc/platforms/85xx/mpc8540_ads.h +++ b/arch/powerpc/platforms/85xx/mpc8540_ads.h @@ -1,5 +1,5 @@ /* - * arch/ppc/platforms/85xx/mpc8540_ads.h + * arch/powerpc/platforms/85xx/mpc8540_ads.h * * MPC8540ADS board definitions * diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h index b44db62..83415db 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx.h +++ b/arch/powerpc/platforms/85xx/mpc85xx.h @@ -1,5 +1,5 @@ /* - * arch/ppc/platforms/85xx/mpc85xx.h + * arch/powerpc/platforms/85xx/mpc85xx.h * * MPC85xx soc definitions/function decls * diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.h b/arch/powerpc/platforms/85xx/mpc85xx_cds.h index 671f54f..b251c9f 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.h +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.h @@ -1,5 +1,5 @@ /* - * arch/ppc/platforms/85xx/mpc85xx_cds_common.h + * arch/powerpc/platforms/85xx/mpc85xx_cds.h * * MPC85xx CDS board definitions * diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c index 0251b7c..6ebdae8 100644 --- a/arch/powerpc/sysdev/ipic.c +++ b/arch/powerpc/sysdev/ipic.c @@ -1,5 +1,5 @@ /* - * include/asm-ppc/ipic.c + * arch/powerpc/sysdev/ipic.c * * IPIC routines implementations. * diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 723972b..3ee03a9 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -341,7 +341,7 @@ static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); if (id == PCI_CAP_ID_HT) { id = readb(devbase + pos + 3); - if (id == 0x80) + if (id == HT_CAPTYPE_IRQ) break; } } diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig index fdd9e7b..077711e 100644 --- a/arch/ppc/Kconfig +++ b/arch/ppc/Kconfig @@ -1345,7 +1345,7 @@ config CONSISTENT_START_BOOL depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE help This option allows you to set the base virtual address - of the the consistent memory pool. This pool of virtual + of the consistent memory pool. This pool of virtual memory is used to make consistent memory allocations. config CONSISTENT_START @@ -1356,7 +1356,7 @@ config CONSISTENT_SIZE_BOOL bool "Set custom consistent memory pool size" depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE help - This option allows you to set the size of the the + This option allows you to set the size of the consistent memory pool. This pool of virtual memory is used to make consistent memory allocations. diff --git a/arch/ppc/boot/include/mpsc_defs.h b/arch/ppc/boot/include/mpsc_defs.h index 2ce7bbb..9f37e13 100644 --- a/arch/ppc/boot/include/mpsc_defs.h +++ b/arch/ppc/boot/include/mpsc_defs.h @@ -1,5 +1,5 @@ /* - * drivers/serial/mpsc/mpsc_defs.h + * arch/ppc/boot/include/mpsc_defs.h * * Register definitions for the Marvell Multi-Protocol Serial Controller (MPSC), * Serial DMA Controller (SDMA), and Baud Rate Generator (BRG). diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h index cd7d0e7..66ec5f3 100644 --- a/arch/ppc/platforms/4xx/xparameters/xparameters.h +++ b/arch/ppc/platforms/4xx/xparameters/xparameters.h @@ -1,5 +1,5 @@ /* - * include/asm-ppc/xparameters.h + * arch/ppc/platforms/4xx/xparameters/xparameters.h * * This file includes the correct xparameters.h for the CONFIG'ed board plus * fixups to translate board specific XPAR values to a common set of names diff --git a/arch/ppc/platforms/85xx/Kconfig b/arch/ppc/platforms/85xx/Kconfig index 7ddd331..6f2d0ad 100644 --- a/arch/ppc/platforms/85xx/Kconfig +++ b/arch/ppc/platforms/85xx/Kconfig @@ -24,12 +24,12 @@ config MPC8540_ADS config MPC8548_CDS bool "Freescale MPC8548 CDS" help - This option enablese support for the MPC8548 CDS evaluation board. + This option enables support for the MPC8548 CDS evaluation board. config MPC8555_CDS bool "Freescale MPC8555 CDS" help - This option enablese support for the MPC8555 CDS evaluation board. + This option enables support for the MPC8555 CDS evaluation board. config MPC8560_ADS bool "Freescale MPC8560 ADS" @@ -51,22 +51,22 @@ config STX_GP3 config TQM8540 bool "TQ Components TQM8540" help - This option enablese support for the TQ Components TQM8540 board. + This option enables support for the TQ Components TQM8540 board. config TQM8541 bool "TQ Components TQM8541" help - This option enablese support for the TQ Components TQM8541 board. + This option enables support for the TQ Components TQM8541 board. config TQM8555 bool "TQ Components TQM8555" help - This option enablese support for the TQ Components TQM8555 board. + This option enables support for the TQ Components TQM8555 board. config TQM8560 bool "TQ Components TQM8560" help - This option enablese support for the TQ Components TQM8560 board. + This option enables support for the TQ Components TQM8560 board. endchoice @@ -94,7 +94,7 @@ config MPC8560 default y config 85xx_PCI2 - bool "Supprt for 2nd PCI host controller" + bool "Support for 2nd PCI host controller" depends on MPC8555_CDS default y diff --git a/arch/ppc/platforms/lopec.h b/arch/ppc/platforms/lopec.h index 5490edb..d597b68 100644 --- a/arch/ppc/platforms/lopec.h +++ b/arch/ppc/platforms/lopec.h @@ -1,5 +1,5 @@ /* - * include/asm-ppc/lopec_serial.h + * arch/ppc/platforms/lopec.h * * Definitions for Motorola LoPEC board. * diff --git a/arch/ppc/platforms/mpc8272ads_setup.c b/arch/ppc/platforms/mpc8272ads_setup.c index d5d36c3..d7b3a6a 100644 --- a/arch/ppc/platforms/mpc8272ads_setup.c +++ b/arch/ppc/platforms/mpc8272ads_setup.c @@ -1,5 +1,5 @@ /* - * arch/ppc/platforms/82xx/pq2ads_pd.c + * arch/ppc/platforms/mpc8272ads_setup.c * * MPC82xx Board-specific PlatformDevice descriptions * diff --git a/arch/ppc/platforms/mpc885ads_setup.c b/arch/ppc/platforms/mpc885ads_setup.c index bf388ed..0229314 100644 --- a/arch/ppc/platforms/mpc885ads_setup.c +++ b/arch/ppc/platforms/mpc885ads_setup.c @@ -1,4 +1,4 @@ -/*arch/ppc/platforms/mpc885ads-setup.c +/*arch/ppc/platforms/mpc885ads_setup.c * * Platform setup for the Freescale mpc885ads board * diff --git a/arch/ppc/platforms/mvme5100.h b/arch/ppc/platforms/mvme5100.h index edd4794..9e2a09e 100644 --- a/arch/ppc/platforms/mvme5100.h +++ b/arch/ppc/platforms/mvme5100.h @@ -1,5 +1,5 @@ /* - * include/asm-ppc/platforms/mvme5100.h + * arch/ppc/platforms/mvme5100.h * * Definitions for Motorola MVME5100. * diff --git a/arch/ppc/platforms/powerpmc250.h b/arch/ppc/platforms/powerpmc250.h index 41a6dc8..d33ad8dc 100644 --- a/arch/ppc/platforms/powerpmc250.h +++ b/arch/ppc/platforms/powerpmc250.h @@ -1,5 +1,5 @@ /* - * include/asm-ppc/platforms/powerpmc250.h + * arch/ppc/platforms/powerpmc250.h * * Definitions for Force PowerPMC-250 board support * diff --git a/arch/ppc/platforms/prpmc750.h b/arch/ppc/platforms/prpmc750.h index 015b4f5..4c7adcc 100644 --- a/arch/ppc/platforms/prpmc750.h +++ b/arch/ppc/platforms/prpmc750.h @@ -1,5 +1,5 @@ /* - * include/asm-ppc/platforms/prpmc750.h + * arch/ppc/platforms/prpmc750.h * * Definitions for Motorola PrPMC750 board support * diff --git a/arch/ppc/platforms/prpmc800.h b/arch/ppc/platforms/prpmc800.h index e53ec9b..26f604e 100644 --- a/arch/ppc/platforms/prpmc800.h +++ b/arch/ppc/platforms/prpmc800.h @@ -1,5 +1,5 @@ /* - * include/asm-ppc/platforms/prpmc800.h + * arch/ppc/platforms/prpmc800.h * * Definitions for Motorola PrPMC800 board support * diff --git a/arch/ppc/platforms/spruce.h b/arch/ppc/platforms/spruce.h index a31ff7e..f1f96f1 100644 --- a/arch/ppc/platforms/spruce.h +++ b/arch/ppc/platforms/spruce.h @@ -1,5 +1,5 @@ /* - * include/asm-ppc/platforms/spruce.h + * arch/ppc/platforms/spruce.h * * Definitions for IBM Spruce reference board support * diff --git a/arch/sh/boards/bigsur/io.c b/arch/sh/boards/bigsur/io.c index 6835381..23071f9 100644 --- a/arch/sh/boards/bigsur/io.c +++ b/arch/sh/boards/bigsur/io.c @@ -1,5 +1,5 @@ /* - * include/asm-sh/io_bigsur.c + * arch/sh/boards/bigsur/io.c * * By Dustin McIntire (dustin@sensoria.com) (c)2001 * Derived from io_hd64465.h, which bore the message: diff --git a/arch/sh/boards/bigsur/led.c b/arch/sh/boards/bigsur/led.c index 6b08c0e..d221439 100644 --- a/arch/sh/boards/bigsur/led.c +++ b/arch/sh/boards/bigsur/led.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/led_bigsur.c + * linux/arch/sh/boards/bigsur/led.c * * By Dustin McIntire (dustin@sensoria.com) (c)2001 * Derived from led_se.c and led.c, which bore the message: diff --git a/arch/sh/boards/ec3104/io.c b/arch/sh/boards/ec3104/io.c index a70928c..2f86394 100644 --- a/arch/sh/boards/ec3104/io.c +++ b/arch/sh/boards/ec3104/io.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/io_ec3104.c + * linux/arch/sh/boards/ec3104/io.c * EC3104 companion chip support * * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> diff --git a/arch/sh/boards/hp6xx/setup.c b/arch/sh/boards/hp6xx/setup.c index 60ab17a..2d3a5b4 100644 --- a/arch/sh/boards/hp6xx/setup.c +++ b/arch/sh/boards/hp6xx/setup.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/boards/hp6xx/hp680/setup.c + * linux/arch/sh/boards/hp6xx/setup.c * * Copyright (C) 2002 Andriy Skulysh * diff --git a/arch/sh/boards/mpc1211/led.c b/arch/sh/boards/mpc1211/led.c index 1fe3692..8df1591 100644 --- a/arch/sh/boards/mpc1211/led.c +++ b/arch/sh/boards/mpc1211/led.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/led_mpc1211.c + * linux/arch/sh/boards/mpc1211/led.c * * Copyright (C) 2001 Saito.K & Jeanne * diff --git a/arch/sh/boards/mpc1211/setup.c b/arch/sh/boards/mpc1211/setup.c index 8eb5d43..01c10fa 100644 --- a/arch/sh/boards/mpc1211/setup.c +++ b/arch/sh/boards/mpc1211/setup.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/board/mpc1211/setup.c + * linux/arch/sh/boards/mpc1211/setup.c * * Copyright (C) 2002 Saito.K & Jeanne, Fujii.Y * diff --git a/arch/sh/boards/renesas/hs7751rvoip/io.c b/arch/sh/boards/renesas/hs7751rvoip/io.c index 9ea1136..51f3f65 100644 --- a/arch/sh/boards/renesas/hs7751rvoip/io.c +++ b/arch/sh/boards/renesas/hs7751rvoip/io.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/io_hs7751rvoip.c + * linux/arch/sh/boards/renesas/hs7751rvoip/io.c * * Copyright (C) 2001 Ian da Silva, Jeremy Siegel * Based largely on io_se.c. diff --git a/arch/sh/boards/renesas/hs7751rvoip/pci.c b/arch/sh/boards/renesas/hs7751rvoip/pci.c index 7e5786b..1c0ddee 100644 --- a/arch/sh/boards/renesas/hs7751rvoip/pci.c +++ b/arch/sh/boards/renesas/hs7751rvoip/pci.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/pci-hs7751rvoip.c + * linux/arch/sh/boards/renesas/hs7751rvoip/pci.c * * Author: Ian DaSilva (idasilva@mvista.com) * diff --git a/arch/sh/boards/renesas/rts7751r2d/led.c b/arch/sh/boards/renesas/rts7751r2d/led.c index e14a13d..a7ce66c 100644 --- a/arch/sh/boards/renesas/rts7751r2d/led.c +++ b/arch/sh/boards/renesas/rts7751r2d/led.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/led_rts7751r2d.c + * linux/arch/sh/boards/renesas/rts7751r2d/led.c * * Copyright (C) Atom Create Engineering Co., Ltd. * diff --git a/arch/sh/boards/renesas/systemh/io.c b/arch/sh/boards/renesas/systemh/io.c index cde6e5d..1b767e1 100644 --- a/arch/sh/boards/renesas/systemh/io.c +++ b/arch/sh/boards/renesas/systemh/io.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/boards/systemh/io.c + * linux/arch/sh/boards/renesas/systemh/io.c * * Copyright (C) 2001 Ian da Silva, Jeremy Siegel * Based largely on io_se.c. diff --git a/arch/sh/boards/renesas/systemh/irq.c b/arch/sh/boards/renesas/systemh/irq.c index 8d016da..0ba2fe6 100644 --- a/arch/sh/boards/renesas/systemh/irq.c +++ b/arch/sh/boards/renesas/systemh/irq.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/boards/systemh/irq.c + * linux/arch/sh/boards/renesas/systemh/irq.c * * Copyright (C) 2000 Kazumoto Kojima * diff --git a/arch/sh/boards/renesas/systemh/setup.c b/arch/sh/boards/renesas/systemh/setup.c index bab7d3c..9361176 100644 --- a/arch/sh/boards/renesas/systemh/setup.c +++ b/arch/sh/boards/renesas/systemh/setup.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/boards/systemh/setup.c + * linux/arch/sh/boards/renesas/systemh/setup.c * * Copyright (C) 2000 Kazumoto Kojima * Copyright (C) 2003 Paul Mundt diff --git a/arch/sh/boards/se/770x/led.c b/arch/sh/boards/se/770x/led.c index daf7b1e..d93dd83 100644 --- a/arch/sh/boards/se/770x/led.c +++ b/arch/sh/boards/se/770x/led.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/led_se.c + * linux/arch/sh/boards/se/770x/led.c * * Copyright (C) 2000 Stuart Menefy <stuart.menefy@st.com> * diff --git a/arch/sh/boards/se/7751/led.c b/arch/sh/boards/se/7751/led.c index ff0355d..de4194d 100644 --- a/arch/sh/boards/se/7751/led.c +++ b/arch/sh/boards/se/7751/led.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/led_se.c + * linux/arch/sh/boards/se/7751/led.c * * Copyright (C) 2000 Stuart Menefy <stuart.menefy@st.com> * diff --git a/arch/sh/boards/se/7751/pci.c b/arch/sh/boards/se/7751/pci.c index 3ee0301..203b292 100644 --- a/arch/sh/boards/se/7751/pci.c +++ b/arch/sh/boards/se/7751/pci.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/pci-7751se.c + * linux/arch/sh/boards/se/7751/pci.c * * Author: Ian DaSilva (idasilva@mvista.com) * diff --git a/arch/sh/boards/superh/microdev/io.c b/arch/sh/boards/superh/microdev/io.c index 4836b94..83419bf 100644 --- a/arch/sh/boards/superh/microdev/io.c +++ b/arch/sh/boards/superh/microdev/io.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/io_microdev.c + * linux/arch/sh/boards/superh/microdev/io.c * * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) * Copyright (C) 2003, 2004 SuperH, Inc. diff --git a/arch/sh/boards/superh/microdev/led.c b/arch/sh/boards/superh/microdev/led.c index a38f535..36e54b4 100644 --- a/arch/sh/boards/superh/microdev/led.c +++ b/arch/sh/boards/superh/microdev/led.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/led_microdev.c + * linux/arch/sh/boards/superh/microdev/led.c * * Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com> * Copyright (C) 2003 Richard Curnow (Richard.Curnow@superh.com) diff --git a/arch/sh/drivers/dma/dma-pvr2.c b/arch/sh/drivers/dma/dma-pvr2.c index 3b0b0f6..c1b6bc2 100644 --- a/arch/sh/drivers/dma/dma-pvr2.c +++ b/arch/sh/drivers/dma/dma-pvr2.c @@ -1,5 +1,5 @@ /* - * arch/sh/boards/dreamcast/dma-pvr2.c + * arch/sh/drivers/dma/dma-pvr2.c * * NEC PowerVR 2 (Dreamcast) DMA support * diff --git a/arch/sh/drivers/pci/dma-dreamcast.c b/arch/sh/drivers/pci/dma-dreamcast.c index 6acf02b..230d6ec 100644 --- a/arch/sh/drivers/pci/dma-dreamcast.c +++ b/arch/sh/drivers/pci/dma-dreamcast.c @@ -1,5 +1,5 @@ /* - * arch/sh/pci/dma-dreamcast.c + * arch/sh/drivers/pci/dma-dreamcast.c * * PCI DMA support for the Sega Dreamcast * diff --git a/arch/sh/drivers/pci/fixups-dreamcast.c b/arch/sh/drivers/pci/fixups-dreamcast.c index c0af5f7..6f53f82 100644 --- a/arch/sh/drivers/pci/fixups-dreamcast.c +++ b/arch/sh/drivers/pci/fixups-dreamcast.c @@ -1,5 +1,5 @@ /* - * arch/sh/pci/fixups-dreamcast.c + * arch/sh/drivers/pci/fixups-dreamcast.c * * PCI fixups for the Sega Dreamcast * diff --git a/arch/sh/drivers/pci/ops-bigsur.c b/arch/sh/drivers/pci/ops-bigsur.c index 5da501b..eb31be7 100644 --- a/arch/sh/drivers/pci/ops-bigsur.c +++ b/arch/sh/drivers/pci/ops-bigsur.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/pci-bigsur.c + * linux/arch/sh/drivers/pci/ops-bigsur.c * * By Dustin McIntire (dustin@sensoria.com) (c)2001 * diff --git a/arch/sh/drivers/pci/ops-dreamcast.c b/arch/sh/drivers/pci/ops-dreamcast.c index 23d5279..381306c 100644 --- a/arch/sh/drivers/pci/ops-dreamcast.c +++ b/arch/sh/drivers/pci/ops-dreamcast.c @@ -1,5 +1,5 @@ /* - * arch/sh/pci/ops-dreamcast.c + * arch/sh/drivers/pci/ops-dreamcast.c * * PCI operations for the Sega Dreamcast * diff --git a/arch/sh/drivers/pci/ops-rts7751r2d.c b/arch/sh/drivers/pci/ops-rts7751r2d.c index 88f44e2..b68824c 100644 --- a/arch/sh/drivers/pci/ops-rts7751r2d.c +++ b/arch/sh/drivers/pci/ops-rts7751r2d.c @@ -1,5 +1,5 @@ /* - * linux/arch/sh/kernel/pci-rts7751r2d.c + * linux/arch/sh/drivers/pci/ops-rts7751r2d.c * * Author: Ian DaSilva (idasilva@mvista.com) * diff --git a/arch/sh/kernel/cpu/ubc.S b/arch/sh/kernel/cpu/ubc.S index 0c569b2..8192307 100644 --- a/arch/sh/kernel/cpu/ubc.S +++ b/arch/sh/kernel/cpu/ubc.S @@ -1,5 +1,5 @@ /* - * arch/sh/kernel/ubc.S + * arch/sh/kernel/cpu/ubc.S * * Set of management routines for the User Break Controller (UBC) * diff --git a/arch/sh64/boot/compressed/misc.c b/arch/sh64/boot/compressed/misc.c index ee7a1b6..aea00c5 100644 --- a/arch/sh64/boot/compressed/misc.c +++ b/arch/sh64/boot/compressed/misc.c @@ -1,5 +1,5 @@ /* - * arch/shmedia/boot/compressed/misc.c + * arch/sh64/boot/compressed/misc.c * * This is a collection of several routines from gzip-1.0.3 * adapted for Linux. diff --git a/arch/sh64/kernel/alphanum.c b/arch/sh64/kernel/alphanum.c index 9079d1e..91707c1 100644 --- a/arch/sh64/kernel/alphanum.c +++ b/arch/sh64/kernel/alphanum.c @@ -1,5 +1,5 @@ /* - * arch/sh64/kernel/alpanum.c + * arch/sh64/kernel/alphanum.c * * Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com> * diff --git a/arch/sh64/lib/c-checksum.c b/arch/sh64/lib/c-checksum.c index 53c1cab..0e8a742 100644 --- a/arch/sh64/lib/c-checksum.c +++ b/arch/sh64/lib/c-checksum.c @@ -1,5 +1,5 @@ /* - * arch/sh/lib/csum_parial.c + * arch/sh64/lib/c-checksum.c * * This file contains network checksum routines that are better done * in an architecture-specific manner due to speed.. diff --git a/arch/sh64/mach-cayman/led.c b/arch/sh64/mach-cayman/led.c index 8b3cc4c..b4e122f 100644 --- a/arch/sh64/mach-cayman/led.c +++ b/arch/sh64/mach-cayman/led.c @@ -1,5 +1,5 @@ /* - * arch/sh64/kernel/led_cayman.c + * arch/sh64/mach-cayman/led.c * * Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com> * diff --git a/arch/sh64/oprofile/op_model_null.c b/arch/sh64/oprofile/op_model_null.c index a845b08..a750ea1 100644 --- a/arch/sh64/oprofile/op_model_null.c +++ b/arch/sh64/oprofile/op_model_null.c @@ -1,5 +1,5 @@ /* - * arch/sh/oprofile/op_model_null.c + * arch/sh64/oprofile/op_model_null.c * * Copyright (C) 2003 Paul Mundt * diff --git a/arch/sparc/kernel/sys_solaris.c b/arch/sparc/kernel/sys_solaris.c index c09afd9..01b07bb 100644 --- a/arch/sparc/kernel/sys_solaris.c +++ b/arch/sparc/kernel/sys_solaris.c @@ -1,5 +1,5 @@ /* - * linux/arch/sparc/sys_solaris.c + * linux/arch/sparc/kernel/sys_solaris.c * * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) */ diff --git a/arch/um/Kconfig b/arch/um/Kconfig index 76e85bb..d753075 100644 --- a/arch/um/Kconfig +++ b/arch/um/Kconfig @@ -257,7 +257,7 @@ config UML_REAL_TIME_CLOCK UML and spend long times with UML stopped at a breakpoint. In this case, when UML is restarted, it will call the timer enough times to make up for the time spent at the breakpoint. This could result in a - noticable lag. If this is a problem, then disable this option. + noticeable lag. If this is a problem, then disable this option. endmenu diff --git a/arch/um/Makefile b/arch/um/Makefile index f6ad832..c8016a9 100644 --- a/arch/um/Makefile +++ b/arch/um/Makefile @@ -102,7 +102,7 @@ linux: vmlinux define archhelp echo '* linux - Binary kernel image (./linux) - for backward' echo ' compatibility only, this creates a hard link to the' - echo ' real kernel binary, the the "vmlinux" binary you' + echo ' real kernel binary, the "vmlinux" binary you' echo ' find in the kernel root.' endef diff --git a/arch/um/drivers/line.c b/arch/um/drivers/line.c index 24747a4..cfd9f01 100644 --- a/arch/um/drivers/line.c +++ b/arch/um/drivers/line.c @@ -497,7 +497,7 @@ void close_lines(struct line *lines, int nlines) } /* Common setup code for both startup command line and mconsole initialization. - * @lines contains the the array (of size @num) to modify; + * @lines contains the array (of size @num) to modify; * @init is the setup string; */ diff --git a/arch/um/include/sysdep-x86_64/ptrace_user.h b/arch/um/include/sysdep-x86_64/ptrace_user.h index 128faf0..4cd61a8 100644 --- a/arch/um/include/sysdep-x86_64/ptrace_user.h +++ b/arch/um/include/sysdep-x86_64/ptrace_user.h @@ -55,7 +55,7 @@ #define PTRACE_OLDSETOPTIONS 21 #endif -/* These are before the system call, so the the system call number is RAX +/* These are before the system call, so the system call number is RAX * rather than ORIG_RAX, and arg4 is R10 rather than RCX */ #define REGS_SYSCALL_NR PT_INDEX(RAX) diff --git a/arch/v850/kernel/entry.S b/arch/v850/kernel/entry.S index d991e45..8bc521c 100644 --- a/arch/v850/kernel/entry.S +++ b/arch/v850/kernel/entry.S @@ -195,7 +195,7 @@ sst.w lp, PTO+PT_GPR(GPR_LP)[ep]; \ type ## _STATE_SAVER /* Pop a register state pushed by PUSH_STATE, except for the stack pointer, - from the the stack. */ + from the stack. */ #define POP_STATE(type) \ mov sp, ep; \ type ## _STATE_RESTORER; \ diff --git a/arch/x86_64/Kconfig b/arch/x86_64/Kconfig index 0a5d8e6..010d226 100644 --- a/arch/x86_64/Kconfig +++ b/arch/x86_64/Kconfig @@ -310,7 +310,7 @@ config K8_NUMA help Enable K8 NUMA node topology detection. You should say Y here if you have a multi processor AMD K8 system. This uses an old - method to read the NUMA configurtion directly from the builtin + method to read the NUMA configuration directly from the builtin Northbridge of Opteron. It is recommended to use X86_64_ACPI_NUMA instead, which also takes priority if both are compiled in. diff --git a/arch/x86_64/kernel/i8259.c b/arch/x86_64/kernel/i8259.c index 2dd51f3..0612a33 100644 --- a/arch/x86_64/kernel/i8259.c +++ b/arch/x86_64/kernel/i8259.c @@ -43,17 +43,10 @@ BI(x,8) BI(x,9) BI(x,a) BI(x,b) \ BI(x,c) BI(x,d) BI(x,e) BI(x,f) -#define BUILD_15_IRQS(x) \ - BI(x,0) BI(x,1) BI(x,2) BI(x,3) \ - BI(x,4) BI(x,5) BI(x,6) BI(x,7) \ - BI(x,8) BI(x,9) BI(x,a) BI(x,b) \ - BI(x,c) BI(x,d) BI(x,e) - /* * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: * (these are usually mapped to vectors 0x20-0x2f) */ -BUILD_16_IRQS(0x0) /* * The IO-APIC gives us many more interrupt sources. Most of these @@ -65,17 +58,12 @@ BUILD_16_IRQS(0x0) * * (these are usually mapped into the 0x30-0xff vector range) */ - BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3) + BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3) BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7) BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb) -BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) - -#ifdef CONFIG_PCI_MSI - BUILD_15_IRQS(0xe) -#endif +BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf) #undef BUILD_16_IRQS -#undef BUILD_15_IRQS #undef BI @@ -88,29 +76,15 @@ BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \ IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f) -#define IRQLIST_15(x) \ - IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \ - IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \ - IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \ - IRQ(x,c), IRQ(x,d), IRQ(x,e) - void (*interrupt[NR_IRQS])(void) = { - IRQLIST_16(0x0), - - IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3), + IRQLIST_16(0x2), IRQLIST_16(0x3), IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7), IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb), - IRQLIST_16(0xc), IRQLIST_16(0xd) - -#ifdef CONFIG_PCI_MSI - , IRQLIST_15(0xe) -#endif - + IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf) }; #undef IRQ #undef IRQLIST_16 -#undef IRQLIST_14 /* * This is the 'legacy' 8259A Programmable Interrupt Controller, @@ -121,42 +95,15 @@ void (*interrupt[NR_IRQS])(void) = { * moves to arch independent land */ -DEFINE_SPINLOCK(i8259A_lock); - static int i8259A_auto_eoi; - -static void end_8259A_irq (unsigned int irq) -{ - if (irq > 256) { - char var; - printk("return %p stack %p ti %p\n", __builtin_return_address(0), &var, task_thread_info(current)); - - BUG(); - } - - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) && - irq_desc[irq].action) - enable_8259A_irq(irq); -} - -#define shutdown_8259A_irq disable_8259A_irq - +DEFINE_SPINLOCK(i8259A_lock); static void mask_and_ack_8259A(unsigned int); -static unsigned int startup_8259A_irq(unsigned int irq) -{ - enable_8259A_irq(irq); - return 0; /* never anything pending */ -} - -static struct hw_interrupt_type i8259A_irq_type = { - .typename = "XT-PIC", - .startup = startup_8259A_irq, - .shutdown = shutdown_8259A_irq, - .enable = enable_8259A_irq, - .disable = disable_8259A_irq, - .ack = mask_and_ack_8259A, - .end = end_8259A_irq, +static struct irq_chip i8259A_chip = { + .name = "XT-PIC", + .mask = disable_8259A_irq, + .unmask = enable_8259A_irq, + .mask_ack = mask_and_ack_8259A, }; /* @@ -231,7 +178,7 @@ void make_8259A_irq(unsigned int irq) { disable_irq_nosync(irq); io_apic_irqs &= ~(1<<irq); - irq_desc[irq].chip = &i8259A_irq_type; + set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq); enable_irq(irq); } @@ -367,9 +314,9 @@ void init_8259A(int auto_eoi) * in AEOI mode we just have to mask the interrupt * when acking. */ - i8259A_irq_type.ack = disable_8259A_irq; + i8259A_chip.mask_ack = disable_8259A_irq; else - i8259A_irq_type.ack = mask_and_ack_8259A; + i8259A_chip.mask_ack = mask_and_ack_8259A; udelay(100); /* wait for 8259A to initialize */ @@ -447,6 +394,26 @@ device_initcall(i8259A_init_sysfs); */ static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL}; +DEFINE_PER_CPU(vector_irq_t, vector_irq) = { + [0 ... FIRST_EXTERNAL_VECTOR - 1] = -1, + [FIRST_EXTERNAL_VECTOR + 0] = 0, + [FIRST_EXTERNAL_VECTOR + 1] = 1, + [FIRST_EXTERNAL_VECTOR + 2] = 2, + [FIRST_EXTERNAL_VECTOR + 3] = 3, + [FIRST_EXTERNAL_VECTOR + 4] = 4, + [FIRST_EXTERNAL_VECTOR + 5] = 5, + [FIRST_EXTERNAL_VECTOR + 6] = 6, + [FIRST_EXTERNAL_VECTOR + 7] = 7, + [FIRST_EXTERNAL_VECTOR + 8] = 8, + [FIRST_EXTERNAL_VECTOR + 9] = 9, + [FIRST_EXTERNAL_VECTOR + 10] = 10, + [FIRST_EXTERNAL_VECTOR + 11] = 11, + [FIRST_EXTERNAL_VECTOR + 12] = 12, + [FIRST_EXTERNAL_VECTOR + 13] = 13, + [FIRST_EXTERNAL_VECTOR + 14] = 14, + [FIRST_EXTERNAL_VECTOR + 15] = 15, + [FIRST_EXTERNAL_VECTOR + 16 ... NR_VECTORS - 1] = -1 +}; void __init init_ISA_irqs (void) { @@ -464,12 +431,13 @@ void __init init_ISA_irqs (void) /* * 16 old-style INTA-cycle interrupts: */ - irq_desc[i].chip = &i8259A_irq_type; + set_irq_chip_and_handler(i, &i8259A_chip, + handle_level_irq); } else { /* * 'high' PCI IRQs filled in on demand */ - irq_desc[i].chip = &no_irq_type; + irq_desc[i].chip = &no_irq_chip; } } } @@ -543,8 +511,6 @@ void __init init_IRQ(void) */ for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) { int vector = FIRST_EXTERNAL_VECTOR + i; - if (i >= NR_IRQS) - break; if (vector != IA32_SYSCALL_VECTOR) set_intr_gate(vector, interrupt[i]); } @@ -554,7 +520,7 @@ void __init init_IRQ(void) * IRQ0 must be given a fixed assignment and initialized, * because it's used before the IO-APIC is set up. */ - set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); + __get_cpu_var(vector_irq)[FIRST_DEVICE_VECTOR] = 0; /* * The reschedule interrupt is a CPU-to-CPU reschedule-helper diff --git a/arch/x86_64/kernel/io_apic.c b/arch/x86_64/kernel/io_apic.c index 0491019..91728d9 100644 --- a/arch/x86_64/kernel/io_apic.c +++ b/arch/x86_64/kernel/io_apic.c @@ -26,9 +26,12 @@ #include <linux/delay.h> #include <linux/sched.h> #include <linux/smp_lock.h> +#include <linux/pci.h> #include <linux/mc146818rtc.h> #include <linux/acpi.h> #include <linux/sysdev.h> +#include <linux/msi.h> +#include <linux/htirq.h> #ifdef CONFIG_ACPI #include <acpi/acpi_bus.h> #endif @@ -41,6 +44,10 @@ #include <asm/acpi.h> #include <asm/dma.h> #include <asm/nmi.h> +#include <asm/msidef.h> +#include <asm/hypertransport.h> + +static int assign_irq_vector(int irq, cpumask_t mask); #define __apicdebuginit __init @@ -81,14 +88,6 @@ static struct irq_pin_list { short apic, pin, next; } irq_2_pin[PIN_MAP_SIZE]; -int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1}; -#ifdef CONFIG_PCI_MSI -#define vector_to_irq(vector) \ - (platform_legacy_irq(vector) ? vector : vector_irq[vector]) -#else -#define vector_to_irq(vector) (vector) -#endif - #define __DO_ACTION(R, ACTION, FINAL) \ \ { \ @@ -139,11 +138,35 @@ static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) } #ifdef CONFIG_SMP +static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector) +{ + int apic, pin; + struct irq_pin_list *entry = irq_2_pin + irq; + + BUG_ON(irq >= NR_IRQS); + for (;;) { + unsigned int reg; + apic = entry->apic; + pin = entry->pin; + if (pin == -1) + break; + io_apic_write(apic, 0x11 + pin*2, dest); + reg = io_apic_read(apic, 0x10 + pin*2); + reg &= ~0x000000ff; + reg |= vector; + io_apic_modify(apic, reg); + if (!entry->next) + break; + entry = irq_2_pin + entry->next; + } +} + static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) { unsigned long flags; unsigned int dest; cpumask_t tmp; + int vector; cpus_and(tmp, mask, cpu_online_map); if (cpus_empty(tmp)) @@ -151,7 +174,13 @@ static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) cpus_and(mask, tmp, CPU_MASK_ALL); - dest = cpu_mask_to_apicid(mask); + vector = assign_irq_vector(irq, mask); + if (vector < 0) + return; + + cpus_clear(tmp); + cpu_set(vector >> 8, tmp); + dest = cpu_mask_to_apicid(tmp); /* * Only the high 8 bits are valid. @@ -159,14 +188,12 @@ static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) dest = SET_APIC_LOGICAL_ID(dest); spin_lock_irqsave(&ioapic_lock, flags); - __DO_ACTION(1, = dest, ) - set_irq_info(irq, mask); + __target_IO_APIC_irq(irq, dest, vector & 0xff); + set_native_irq_info(irq, mask); spin_unlock_irqrestore(&ioapic_lock, flags); } #endif -static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF }; - /* * The common case is 1:1 IRQ<->pin mappings. Sometimes there are * shared ISA-space IRQs, so we have to support them. We are super @@ -492,64 +519,6 @@ static inline int irq_trigger(int idx) return MPBIOS_trigger(idx); } -static int next_irq = 16; - -/* - * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ - * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number - * from ACPI, which can reach 800 in large boxen. - * - * Compact the sparse GSI space into a sequential IRQ series and reuse - * vectors if possible. - */ -int gsi_irq_sharing(int gsi) -{ - int i, tries, vector; - - BUG_ON(gsi >= NR_IRQ_VECTORS); - - if (platform_legacy_irq(gsi)) - return gsi; - - if (gsi_2_irq[gsi] != 0xFF) - return (int)gsi_2_irq[gsi]; - - tries = NR_IRQS; - try_again: - vector = assign_irq_vector(gsi); - - /* - * Sharing vectors means sharing IRQs, so scan irq_vectors for previous - * use of vector and if found, return that IRQ. However, we never want - * to share legacy IRQs, which usually have a different trigger mode - * than PCI. - */ - for (i = 0; i < NR_IRQS; i++) - if (IO_APIC_VECTOR(i) == vector) - break; - if (platform_legacy_irq(i)) { - if (--tries >= 0) { - IO_APIC_VECTOR(i) = 0; - goto try_again; - } - panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi); - } - if (i < NR_IRQS) { - gsi_2_irq[gsi] = i; - printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n", - gsi, vector, i); - return i; - } - - i = next_irq++; - BUG_ON(i >= NR_IRQS); - gsi_2_irq[gsi] = i; - IO_APIC_VECTOR(i) = vector; - printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n", - gsi, vector, i); - return i; -} - static int pin_2_irq(int idx, int apic, int pin) { int irq, i; @@ -571,7 +540,6 @@ static int pin_2_irq(int idx, int apic, int pin) while (i < apic) irq += nr_ioapic_registers[i++]; irq += pin; - irq = gsi_irq_sharing(irq); } BUG_ON(irq >= NR_IRQS); return irq; @@ -595,46 +563,83 @@ static inline int IO_APIC_irq_trigger(int irq) } /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ -u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }; +unsigned int irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_EXTERNAL_VECTOR, 0 }; -int assign_irq_vector(int irq) +static int __assign_irq_vector(int irq, cpumask_t mask) { - static int current_vector = FIRST_DEVICE_VECTOR, offset = 0; - unsigned long flags; - int vector; - - BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS); - - spin_lock_irqsave(&vector_lock, flags); - - if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) { - spin_unlock_irqrestore(&vector_lock, flags); - return IO_APIC_VECTOR(irq); + /* + * NOTE! The local APIC isn't very good at handling + * multiple interrupts at the same interrupt level. + * As the interrupt level is determined by taking the + * vector number and shifting that right by 4, we + * want to spread these out a bit so that they don't + * all fall in the same interrupt level. + * + * Also, we've got to be careful not to trash gate + * 0x80, because int 0x80 is hm, kind of importantish. ;) + */ + static struct { + int vector; + int offset; + } pos[NR_CPUS] = { [ 0 ... NR_CPUS - 1] = {FIRST_DEVICE_VECTOR, 0} }; + int old_vector = -1; + int cpu; + + BUG_ON((unsigned)irq >= NR_IRQ_VECTORS); + + if (IO_APIC_VECTOR(irq) > 0) + old_vector = IO_APIC_VECTOR(irq); + if ((old_vector > 0) && cpu_isset(old_vector >> 8, mask)) { + return old_vector; } + + for_each_cpu_mask(cpu, mask) { + int vector, offset; + vector = pos[cpu].vector; + offset = pos[cpu].offset; next: - current_vector += 8; - if (current_vector == IA32_SYSCALL_VECTOR) - goto next; - - if (current_vector >= FIRST_SYSTEM_VECTOR) { - /* If we run out of vectors on large boxen, must share them. */ - offset = (offset + 1) % 8; - current_vector = FIRST_DEVICE_VECTOR + offset; + vector += 8; + if (vector >= FIRST_SYSTEM_VECTOR) { + /* If we run out of vectors on large boxen, must share them. */ + offset = (offset + 1) % 8; + vector = FIRST_DEVICE_VECTOR + offset; + } + if (unlikely(pos[cpu].vector == vector)) + continue; + if (vector == IA32_SYSCALL_VECTOR) + goto next; + if (per_cpu(vector_irq, cpu)[vector] != -1) + goto next; + /* Found one! */ + pos[cpu].vector = vector; + pos[cpu].offset = offset; + if (old_vector >= 0) { + int old_cpu = old_vector >> 8; + old_vector &= 0xff; + per_cpu(vector_irq, old_cpu)[old_vector] = -1; + } + per_cpu(vector_irq, cpu)[vector] = irq; + vector |= cpu << 8; + IO_APIC_VECTOR(irq) = vector; + return vector; } + return -ENOSPC; +} - vector = current_vector; - vector_irq[vector] = irq; - if (irq != AUTO_ASSIGN) - IO_APIC_VECTOR(irq) = vector; +static int assign_irq_vector(int irq, cpumask_t mask) +{ + int vector; + unsigned long flags; + spin_lock_irqsave(&vector_lock, flags); + vector = __assign_irq_vector(irq, mask); spin_unlock_irqrestore(&vector_lock, flags); - return vector; } extern void (*interrupt[NR_IRQS])(void); -static struct hw_interrupt_type ioapic_level_type; -static struct hw_interrupt_type ioapic_edge_type; + +static struct irq_chip ioapic_chip; #define IOAPIC_AUTO -1 #define IOAPIC_EDGE 0 @@ -642,16 +647,13 @@ static struct hw_interrupt_type ioapic_edge_type; static void ioapic_register_intr(int irq, int vector, unsigned long trigger) { - unsigned idx; - - idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq; - if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || trigger == IOAPIC_LEVEL) - irq_desc[idx].chip = &ioapic_level_type; + set_irq_chip_and_handler(irq, &ioapic_chip, + handle_fasteoi_irq); else - irq_desc[idx].chip = &ioapic_edge_type; - set_intr_gate(vector, interrupt[idx]); + set_irq_chip_and_handler(irq, &ioapic_chip, + handle_edge_irq); } static void __init setup_IO_APIC_irqs(void) @@ -701,8 +703,15 @@ static void __init setup_IO_APIC_irqs(void) continue; if (IO_APIC_IRQ(irq)) { - vector = assign_irq_vector(irq); - entry.vector = vector; + cpumask_t mask; + vector = assign_irq_vector(irq, TARGET_CPUS); + if (vector < 0) + continue; + + cpus_clear(mask); + cpu_set(vector >> 8, mask); + entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask); + entry.vector = vector & 0xff; ioapic_register_intr(irq, vector, IOAPIC_AUTO); if (!apic && (irq < 16)) @@ -752,7 +761,7 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in * The timer IRQ doesn't have to know that behind the * scene we have a 8259A-master in AEOI mode ... */ - irq_desc[0].chip = &ioapic_edge_type; + set_irq_chip_and_handler(0, &ioapic_chip, handle_edge_irq); /* * Add it to the IO-APIC irq-routing table: @@ -868,17 +877,12 @@ void __apicdebuginit print_IO_APIC(void) ); } } - if (use_pci_vector()) - printk(KERN_INFO "Using vector-based indexing\n"); printk(KERN_DEBUG "IRQ to pin mappings:\n"); for (i = 0; i < NR_IRQS; i++) { struct irq_pin_list *entry = irq_2_pin + i; if (entry->pin < 0) continue; - if (use_pci_vector() && !platform_legacy_irq(i)) - printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i)); - else - printk(KERN_DEBUG "IRQ%d ", i); + printk(KERN_DEBUG "IRQ%d ", i); for (;;) { printk("-> %d:%d", entry->apic, entry->pin); if (!entry->next) @@ -1185,7 +1189,7 @@ static int __init timer_irq_works(void) * an edge even if it isn't on the 8259A... */ -static unsigned int startup_edge_ioapic_irq(unsigned int irq) +static unsigned int startup_ioapic_irq(unsigned int irq) { int was_pending = 0; unsigned long flags; @@ -1202,107 +1206,16 @@ static unsigned int startup_edge_ioapic_irq(unsigned int irq) return was_pending; } -/* - * Once we have recorded IRQ_PENDING already, we can mask the - * interrupt for real. This prevents IRQ storms from unhandled - * devices. - */ -static void ack_edge_ioapic_irq(unsigned int irq) -{ - move_irq(irq); - if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED)) - == (IRQ_PENDING | IRQ_DISABLED)) - mask_IO_APIC_irq(irq); - ack_APIC_irq(); -} - -/* - * Level triggered interrupts can just be masked, - * and shutting down and starting up the interrupt - * is the same as enabling and disabling them -- except - * with a startup need to return a "was pending" value. - * - * Level triggered interrupts are special because we - * do not touch any IO-APIC register while handling - * them. We ack the APIC in the end-IRQ handler, not - * in the start-IRQ-handler. Protection against reentrance - * from the same interrupt is still provided, both by the - * generic IRQ layer and by the fact that an unacked local - * APIC does not accept IRQs. - */ -static unsigned int startup_level_ioapic_irq (unsigned int irq) -{ - unmask_IO_APIC_irq(irq); - - return 0; /* don't check for pending */ -} - -static void end_level_ioapic_irq (unsigned int irq) -{ - move_irq(irq); - ack_APIC_irq(); -} - -#ifdef CONFIG_PCI_MSI -static unsigned int startup_edge_ioapic_vector(unsigned int vector) -{ - int irq = vector_to_irq(vector); - - return startup_edge_ioapic_irq(irq); -} - -static void ack_edge_ioapic_vector(unsigned int vector) -{ - int irq = vector_to_irq(vector); - - move_native_irq(vector); - ack_edge_ioapic_irq(irq); -} - -static unsigned int startup_level_ioapic_vector (unsigned int vector) +static int ioapic_retrigger_irq(unsigned int irq) { - int irq = vector_to_irq(vector); + cpumask_t mask; + unsigned vector; - return startup_level_ioapic_irq (irq); -} - -static void end_level_ioapic_vector (unsigned int vector) -{ - int irq = vector_to_irq(vector); - - move_native_irq(vector); - end_level_ioapic_irq(irq); -} - -static void mask_IO_APIC_vector (unsigned int vector) -{ - int irq = vector_to_irq(vector); - - mask_IO_APIC_irq(irq); -} + vector = irq_vector[irq]; + cpus_clear(mask); + cpu_set(vector >> 8, mask); -static void unmask_IO_APIC_vector (unsigned int vector) -{ - int irq = vector_to_irq(vector); - - unmask_IO_APIC_irq(irq); -} - -#ifdef CONFIG_SMP -static void set_ioapic_affinity_vector (unsigned int vector, - cpumask_t cpu_mask) -{ - int irq = vector_to_irq(vector); - - set_native_irq_info(vector, cpu_mask); - set_ioapic_affinity_irq(irq, cpu_mask); -} -#endif // CONFIG_SMP -#endif // CONFIG_PCI_MSI - -static int ioapic_retrigger(unsigned int irq) -{ - send_IPI_self(IO_APIC_VECTOR(irq)); + send_IPI_mask(mask, vector & 0xff); return 1; } @@ -1316,32 +1229,47 @@ static int ioapic_retrigger(unsigned int irq) * races. */ -static struct hw_interrupt_type ioapic_edge_type __read_mostly = { - .typename = "IO-APIC-edge", - .startup = startup_edge_ioapic, - .shutdown = shutdown_edge_ioapic, - .enable = enable_edge_ioapic, - .disable = disable_edge_ioapic, - .ack = ack_edge_ioapic, - .end = end_edge_ioapic, -#ifdef CONFIG_SMP - .set_affinity = set_ioapic_affinity, +static void ack_apic_edge(unsigned int irq) +{ + move_native_irq(irq); + ack_APIC_irq(); +} + +static void ack_apic_level(unsigned int irq) +{ + int do_unmask_irq = 0; + +#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE) + /* If we are moving the irq we need to mask it */ + if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) { + do_unmask_irq = 1; + mask_IO_APIC_irq(irq); + } #endif - .retrigger = ioapic_retrigger, -}; -static struct hw_interrupt_type ioapic_level_type __read_mostly = { - .typename = "IO-APIC-level", - .startup = startup_level_ioapic, - .shutdown = shutdown_level_ioapic, - .enable = enable_level_ioapic, - .disable = disable_level_ioapic, - .ack = mask_and_ack_level_ioapic, - .end = end_level_ioapic, + /* + * We must acknowledge the irq before we move it or the acknowledge will + * not propogate properly. + */ + ack_APIC_irq(); + + /* Now we can move and renable the irq */ + move_masked_irq(irq); + if (unlikely(do_unmask_irq)) + unmask_IO_APIC_irq(irq); +} + +static struct irq_chip ioapic_chip __read_mostly = { + .name = "IO-APIC", + .startup = startup_ioapic_irq, + .mask = mask_IO_APIC_irq, + .unmask = unmask_IO_APIC_irq, + .ack = ack_apic_edge, + .eoi = ack_apic_level, #ifdef CONFIG_SMP - .set_affinity = set_ioapic_affinity, + .set_affinity = set_ioapic_affinity_irq, #endif - .retrigger = ioapic_retrigger, + .retrigger = ioapic_retrigger_irq, }; static inline void init_IO_APIC_traps(void) @@ -1361,11 +1289,6 @@ static inline void init_IO_APIC_traps(void) */ for (irq = 0; irq < NR_IRQS ; irq++) { int tmp = irq; - if (use_pci_vector()) { - if (!platform_legacy_irq(tmp)) - if ((tmp = vector_to_irq(tmp)) == -1) - continue; - } if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) { /* * Hmm.. We don't have an entry for this, @@ -1376,7 +1299,7 @@ static inline void init_IO_APIC_traps(void) make_8259A_irq(irq); else /* Strange. Oh, well.. */ - irq_desc[irq].chip = &no_irq_type; + irq_desc[irq].chip = &no_irq_chip; } } } @@ -1495,8 +1418,6 @@ static inline void unlock_ExtINT_logic(void) spin_unlock_irqrestore(&ioapic_lock, flags); } -int timer_uses_ioapic_pin_0; - /* * This code may look a bit paranoid, but it's supposed to cooperate with * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ @@ -1514,8 +1435,7 @@ static inline void check_timer(void) * get/set the timer IRQ vector: */ disable_8259A_irq(0); - vector = assign_irq_vector(0); - set_intr_gate(vector, interrupt[0]); + vector = assign_irq_vector(0, TARGET_CPUS); /* * Subtle, code in do_timer_interrupt() expects an AEOI @@ -1534,9 +1454,6 @@ static inline void check_timer(void) pin2 = ioapic_i8259.pin; apic2 = ioapic_i8259.apic; - if (pin1 == 0) - timer_uses_ioapic_pin_0 = 1; - apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", vector, apic1, pin1, apic2, pin2); @@ -1740,6 +1657,253 @@ static int __init ioapic_init_sysfs(void) device_initcall(ioapic_init_sysfs); +/* + * Dynamic irq allocate and deallocation + */ +int create_irq(void) +{ + /* Allocate an unused irq */ + int irq; + int new; + int vector = 0; + unsigned long flags; + + irq = -ENOSPC; + spin_lock_irqsave(&vector_lock, flags); + for (new = (NR_IRQS - 1); new >= 0; new--) { + if (platform_legacy_irq(new)) + continue; + if (irq_vector[new] != 0) + continue; + vector = __assign_irq_vector(new, TARGET_CPUS); + if (likely(vector > 0)) + irq = new; + break; + } + spin_unlock_irqrestore(&vector_lock, flags); + + if (irq >= 0) { + dynamic_irq_init(irq); + } + return irq; +} + +void destroy_irq(unsigned int irq) +{ + unsigned long flags; + + dynamic_irq_cleanup(irq); + + spin_lock_irqsave(&vector_lock, flags); + irq_vector[irq] = 0; + spin_unlock_irqrestore(&vector_lock, flags); +} + +/* + * MSI mesage composition + */ +#ifdef CONFIG_PCI_MSI +static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) +{ + int vector; + unsigned dest; + + vector = assign_irq_vector(irq, TARGET_CPUS); + if (vector >= 0) { + cpumask_t tmp; + + cpus_clear(tmp); + cpu_set(vector >> 8, tmp); + dest = cpu_mask_to_apicid(tmp); + + msg->address_hi = MSI_ADDR_BASE_HI; + msg->address_lo = + MSI_ADDR_BASE_LO | + ((INT_DEST_MODE == 0) ? + MSI_ADDR_DEST_MODE_PHYSICAL: + MSI_ADDR_DEST_MODE_LOGICAL) | + ((INT_DELIVERY_MODE != dest_LowestPrio) ? + MSI_ADDR_REDIRECTION_CPU: + MSI_ADDR_REDIRECTION_LOWPRI) | + MSI_ADDR_DEST_ID(dest); + + msg->data = + MSI_DATA_TRIGGER_EDGE | + MSI_DATA_LEVEL_ASSERT | + ((INT_DELIVERY_MODE != dest_LowestPrio) ? + MSI_DATA_DELIVERY_FIXED: + MSI_DATA_DELIVERY_LOWPRI) | + MSI_DATA_VECTOR(vector); + } + return vector; +} + +#ifdef CONFIG_SMP +static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) +{ + struct msi_msg msg; + unsigned int dest; + cpumask_t tmp; + int vector; + + cpus_and(tmp, mask, cpu_online_map); + if (cpus_empty(tmp)) + tmp = TARGET_CPUS; + + cpus_and(mask, tmp, CPU_MASK_ALL); + + vector = assign_irq_vector(irq, mask); + if (vector < 0) + return; + + cpus_clear(tmp); + cpu_set(vector >> 8, tmp); + dest = cpu_mask_to_apicid(tmp); + + read_msi_msg(irq, &msg); + + msg.data &= ~MSI_DATA_VECTOR_MASK; + msg.data |= MSI_DATA_VECTOR(vector); + msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; + msg.address_lo |= MSI_ADDR_DEST_ID(dest); + + write_msi_msg(irq, &msg); + set_native_irq_info(irq, mask); +} +#endif /* CONFIG_SMP */ + +/* + * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, + * which implement the MSI or MSI-X Capability Structure. + */ +static struct irq_chip msi_chip = { + .name = "PCI-MSI", + .unmask = unmask_msi_irq, + .mask = mask_msi_irq, + .ack = ack_apic_edge, +#ifdef CONFIG_SMP + .set_affinity = set_msi_irq_affinity, +#endif + .retrigger = ioapic_retrigger_irq, +}; + +int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev) +{ + struct msi_msg msg; + int ret; + ret = msi_compose_msg(dev, irq, &msg); + if (ret < 0) + return ret; + + write_msi_msg(irq, &msg); + + set_irq_chip_and_handler(irq, &msi_chip, handle_edge_irq); + + return 0; +} + +void arch_teardown_msi_irq(unsigned int irq) +{ + return; +} + +#endif /* CONFIG_PCI_MSI */ + +/* + * Hypertransport interrupt support + */ +#ifdef CONFIG_HT_IRQ + +#ifdef CONFIG_SMP + +static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) +{ + u32 low, high; + low = read_ht_irq_low(irq); + high = read_ht_irq_high(irq); + + low &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); + high &= ~(HT_IRQ_HIGH_DEST_ID_MASK); + + low |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); + high |= HT_IRQ_HIGH_DEST_ID(dest); + + write_ht_irq_low(irq, low); + write_ht_irq_high(irq, high); +} + +static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) +{ + unsigned int dest; + cpumask_t tmp; + int vector; + + cpus_and(tmp, mask, cpu_online_map); + if (cpus_empty(tmp)) + tmp = TARGET_CPUS; + + cpus_and(mask, tmp, CPU_MASK_ALL); + + vector = assign_irq_vector(irq, mask); + if (vector < 0) + return; + + cpus_clear(tmp); + cpu_set(vector >> 8, tmp); + dest = cpu_mask_to_apicid(tmp); + + target_ht_irq(irq, dest, vector & 0xff); + set_native_irq_info(irq, mask); +} +#endif + +static struct hw_interrupt_type ht_irq_chip = { + .name = "PCI-HT", + .mask = mask_ht_irq, + .unmask = unmask_ht_irq, + .ack = ack_apic_edge, +#ifdef CONFIG_SMP + .set_affinity = set_ht_irq_affinity, +#endif + .retrigger = ioapic_retrigger_irq, +}; + +int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) +{ + int vector; + + vector = assign_irq_vector(irq, TARGET_CPUS); + if (vector >= 0) { + u32 low, high; + unsigned dest; + cpumask_t tmp; + + cpus_clear(tmp); + cpu_set(vector >> 8, tmp); + dest = cpu_mask_to_apicid(tmp); + + high = HT_IRQ_HIGH_DEST_ID(dest); + + low = HT_IRQ_LOW_BASE | + HT_IRQ_LOW_DEST_ID(dest) | + HT_IRQ_LOW_VECTOR(vector) | + ((INT_DEST_MODE == 0) ? + HT_IRQ_LOW_DM_PHYSICAL : + HT_IRQ_LOW_DM_LOGICAL) | + HT_IRQ_LOW_RQEOI_EDGE | + ((INT_DELIVERY_MODE != dest_LowestPrio) ? + HT_IRQ_LOW_MT_FIXED : + HT_IRQ_LOW_MT_ARBITRATED); + + write_ht_irq_low(irq, low); + write_ht_irq_high(irq, high); + + set_irq_chip_and_handler(irq, &ht_irq_chip, handle_edge_irq); + } + return vector; +} +#endif /* CONFIG_HT_IRQ */ + /* -------------------------------------------------------------------------- ACPI-based IOAPIC Configuration -------------------------------------------------------------------------- */ @@ -1765,6 +1929,8 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int p { struct IO_APIC_route_entry entry; unsigned long flags; + int vector; + cpumask_t mask; if (!IO_APIC_IRQ(irq)) { apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", @@ -1773,6 +1939,20 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int p } /* + * IRQs < 16 are already in the irq_2_pin[] map + */ + if (irq >= 16) + add_pin_to_irq(irq, ioapic, pin); + + + vector = assign_irq_vector(irq, TARGET_CPUS); + if (vector < 0) + return vector; + + cpus_clear(mask); + cpu_set(vector >> 8, mask); + + /* * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. * Note that we mask (disable) IRQs now -- these get enabled when the * corresponding device driver registers for this IRQ. @@ -1782,19 +1962,11 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int p entry.delivery_mode = INT_DELIVERY_MODE; entry.dest_mode = INT_DEST_MODE; - entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); + entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask); entry.trigger = triggering; entry.polarity = polarity; entry.mask = 1; /* Disabled (masked) */ - - irq = gsi_irq_sharing(irq); - /* - * IRQs < 16 are already in the irq_2_pin[] map - */ - if (irq >= 16) - add_pin_to_irq(irq, ioapic, pin); - - entry.vector = assign_irq_vector(irq); + entry.vector = vector & 0xff; apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> " "IRQ %d Mode:%i Active:%i)\n", ioapic, @@ -1809,7 +1981,7 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int p ioapic_write_entry(ioapic, pin, entry); spin_lock_irqsave(&ioapic_lock, flags); - set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS); + set_native_irq_info(irq, TARGET_CPUS); spin_unlock_irqrestore(&ioapic_lock, flags); return 0; diff --git a/arch/x86_64/kernel/irq.c b/arch/x86_64/kernel/irq.c index b3677e6..506f27c 100644 --- a/arch/x86_64/kernel/irq.c +++ b/arch/x86_64/kernel/irq.c @@ -74,7 +74,8 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); #endif - seq_printf(p, " %14s", irq_desc[i].chip->typename); + seq_printf(p, " %8s", irq_desc[i].chip->name); + seq_printf(p, "-%s", handle_irq_name(irq_desc[i].handle_irq)); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) @@ -104,7 +105,12 @@ skip: asmlinkage unsigned int do_IRQ(struct pt_regs *regs) { /* high bit used in ret_from_ code */ - unsigned irq = ~regs->orig_rax; + unsigned vector = ~regs->orig_rax; + unsigned irq; + + exit_idle(); + irq_enter(); + irq = __get_cpu_var(vector_irq)[vector]; if (unlikely(irq >= NR_IRQS)) { printk(KERN_EMERG "%s: cannot handle IRQ %d\n", @@ -112,12 +118,10 @@ asmlinkage unsigned int do_IRQ(struct pt_regs *regs) BUG(); } - exit_idle(); - irq_enter(); #ifdef CONFIG_DEBUG_STACKOVERFLOW stack_overflow_check(regs); #endif - __do_IRQ(irq, regs); + generic_handle_irq(irq, regs); irq_exit(); return 1; diff --git a/arch/x86_64/kernel/mpparse.c b/arch/x86_64/kernel/mpparse.c index b8d53df..b147ab1 100644 --- a/arch/x86_64/kernel/mpparse.c +++ b/arch/x86_64/kernel/mpparse.c @@ -790,20 +790,11 @@ void __init mp_config_acpi_legacy_irqs(void) } } -#define MAX_GSI_NUM 4096 - int mp_register_gsi(u32 gsi, int triggering, int polarity) { int ioapic = -1; int ioapic_pin = 0; int idx, bit = 0; - static int pci_irq = 16; - /* - * Mapping between Global System Interrupts, which - * represent all possible interrupts, to the IRQs - * assigned to actual devices. - */ - static int gsi_to_irq[MAX_GSI_NUM]; if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) return gsi; @@ -836,42 +827,11 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity) if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", mp_ioapic_routing[ioapic].apic_id, ioapic_pin); - return gsi_to_irq[gsi]; + return gsi; } mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); - if (triggering == ACPI_LEVEL_SENSITIVE) { - /* - * For PCI devices assign IRQs in order, avoiding gaps - * due to unused I/O APIC pins. - */ - int irq = gsi; - if (gsi < MAX_GSI_NUM) { - /* - * Retain the VIA chipset work-around (gsi > 15), but - * avoid a problem where the 8254 timer (IRQ0) is setup - * via an override (so it's not on pin 0 of the ioapic), - * and at the same time, the pin 0 interrupt is a PCI - * type. The gsi > 15 test could cause these two pins - * to be shared as IRQ0, and they are not shareable. - * So test for this condition, and if necessary, avoid - * the pin collision. - */ - if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0)) - gsi = pci_irq++; - /* - * Don't assign IRQ used by ACPI SCI - */ - if (gsi == acpi_fadt.sci_int) - gsi = pci_irq++; - gsi_to_irq[irq] = gsi; - } else { - printk(KERN_ERR "GSI %u is too high\n", gsi); - return gsi; - } - } - io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, polarity == ACPI_ACTIVE_HIGH ? 0 : 1); diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 848f173..c1e69a1 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -206,7 +206,7 @@ source "drivers/pci/hotplug/Kconfig" endmenu -menu "Exectuable file formats" +menu "Executable file formats" # only elf supported config KCORE_ELF @@ -241,7 +241,7 @@ menu "Xtensa initrd options" bool "Embed root filesystem ramdisk into the kernel" config EMBEDDED_RAMDISK_IMAGE - string "Filename of gziped ramdisk image" + string "Filename of gzipped ramdisk image" depends on EMBEDDED_RAMDISK default "ramdisk.gz" help diff --git a/arch/xtensa/kernel/module.c b/arch/xtensa/kernel/module.c index d1683cf..2ea1755 100644 --- a/arch/xtensa/kernel/module.c +++ b/arch/xtensa/kernel/module.c @@ -1,5 +1,5 @@ /* - * arch/xtensa/kernel/platform.c + * arch/xtensa/kernel/module.c * * Module support. * diff --git a/arch/xtensa/kernel/pci-dma.c b/arch/xtensa/kernel/pci-dma.c index 1ff8226..6648fa9 100644 --- a/arch/xtensa/kernel/pci-dma.c +++ b/arch/xtensa/kernel/pci-dma.c @@ -1,5 +1,5 @@ /* - * arch/xtensa/pci-dma.c + * arch/xtensa/kernel/pci-dma.c * * DMA coherent memory allocation. * diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c index 8709f82..45571cc 100644 --- a/arch/xtensa/kernel/pci.c +++ b/arch/xtensa/kernel/pci.c @@ -1,5 +1,5 @@ /* - * arch/xtensa/pcibios.c + * arch/xtensa/kernel/pci.c * * PCI bios-type initialisation for PCI machines * diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c index 82684d0..c99ab72 100644 --- a/arch/xtensa/kernel/setup.c +++ b/arch/xtensa/kernel/setup.c @@ -1,5 +1,5 @@ /* - * arch/xtensa/setup.c + * arch/xtensa/kernel/setup.c * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff --git a/arch/xtensa/kernel/syscalls.c b/arch/xtensa/kernel/syscalls.c index d9285d4..f49cb23 100644 --- a/arch/xtensa/kernel/syscalls.c +++ b/arch/xtensa/kernel/syscalls.c @@ -1,5 +1,5 @@ /* - * arch/xtensa/kernel/syscall.c + * arch/xtensa/kernel/syscalls.c * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff --git a/arch/xtensa/lib/pci-auto.c b/arch/xtensa/lib/pci-auto.c index 90c790f..a71733a 100644 --- a/arch/xtensa/lib/pci-auto.c +++ b/arch/xtensa/lib/pci-auto.c @@ -1,5 +1,5 @@ /* - * arch/xtensa/kernel/pci-auto.c + * arch/xtensa/lib/pci-auto.c * * PCI autoconfiguration library * diff --git a/arch/xtensa/lib/usercopy.S b/arch/xtensa/lib/usercopy.S index 265db26..4641ef5 100644 --- a/arch/xtensa/lib/usercopy.S +++ b/arch/xtensa/lib/usercopy.S @@ -5,10 +5,10 @@ * * DO NOT COMBINE this function with <arch/xtensa/lib/hal/memcopy.S>. * It needs to remain separate and distinct. The hal files are part - * of the the Xtensa link-time HAL, and those files may differ per + * of the Xtensa link-time HAL, and those files may differ per * processor configuration. Patching the kernel for another * processor configuration includes replacing the hal files, and we - * could loose the special functionality for accessing user-space + * could lose the special functionality for accessing user-space * memory during such a patch. We sacrifice a little code space here * in favor to simplify code maintenance. * diff --git a/arch/xtensa/mm/pgtable.c b/arch/xtensa/mm/pgtable.c index 7d28914..6979927 100644 --- a/arch/xtensa/mm/pgtable.c +++ b/arch/xtensa/mm/pgtable.c @@ -1,5 +1,5 @@ /* - * arch/xtensa/mm/fault.c + * arch/xtensa/mm/pgtable.c * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff --git a/arch/xtensa/mm/tlb.c b/arch/xtensa/mm/tlb.c index d3bd3bf..0fefb866 100644 --- a/arch/xtensa/mm/tlb.c +++ b/arch/xtensa/mm/tlb.c @@ -1,5 +1,5 @@ /* - * arch/xtensa/mm/mmu.c + * arch/xtensa/mm/tlb.c * * Logic that manipulates the Xtensa MMU. Derived from MIPS. * |