diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen_cs.c')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen_cs.c | 1655 |
1 files changed, 165 insertions, 1490 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c index a58b37a..23d3641 100644 --- a/drivers/gpu/drm/radeon/evergreen_cs.c +++ b/drivers/gpu/drm/radeon/evergreen_cs.c @@ -31,9 +31,6 @@ #include "evergreen_reg_safe.h" #include "cayman_reg_safe.h" -#define MAX(a,b) (((a)>(b))?(a):(b)) -#define MIN(a,b) (((a)<(b))?(a):(b)) - static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, struct radeon_cs_reloc **cs_reloc); @@ -41,72 +38,45 @@ struct evergreen_cs_track { u32 group_size; u32 nbanks; u32 npipes; - u32 row_size; /* value we track */ - u32 nsamples; /* unused */ + u32 nsamples; + u32 cb_color_base_last[12]; struct radeon_bo *cb_color_bo[12]; u32 cb_color_bo_offset[12]; - struct radeon_bo *cb_color_fmask_bo[8]; /* unused */ - struct radeon_bo *cb_color_cmask_bo[8]; /* unused */ + struct radeon_bo *cb_color_fmask_bo[8]; + struct radeon_bo *cb_color_cmask_bo[8]; u32 cb_color_info[12]; u32 cb_color_view[12]; + u32 cb_color_pitch_idx[12]; + u32 cb_color_slice_idx[12]; + u32 cb_color_dim_idx[12]; + u32 cb_color_dim[12]; u32 cb_color_pitch[12]; u32 cb_color_slice[12]; - u32 cb_color_attrib[12]; - u32 cb_color_cmask_slice[8];/* unused */ - u32 cb_color_fmask_slice[8];/* unused */ + u32 cb_color_cmask_slice[8]; + u32 cb_color_fmask_slice[8]; u32 cb_target_mask; - u32 cb_shader_mask; /* unused */ + u32 cb_shader_mask; u32 vgt_strmout_config; u32 vgt_strmout_buffer_config; - struct radeon_bo *vgt_strmout_bo[4]; - u32 vgt_strmout_bo_offset[4]; - u32 vgt_strmout_size[4]; u32 db_depth_control; u32 db_depth_view; - u32 db_depth_slice; u32 db_depth_size; + u32 db_depth_size_idx; u32 db_z_info; + u32 db_z_idx; u32 db_z_read_offset; u32 db_z_write_offset; struct radeon_bo *db_z_read_bo; struct radeon_bo *db_z_write_bo; u32 db_s_info; + u32 db_s_idx; u32 db_s_read_offset; u32 db_s_write_offset; struct radeon_bo *db_s_read_bo; struct radeon_bo *db_s_write_bo; - bool sx_misc_kill_all_prims; - bool cb_dirty; - bool db_dirty; - bool streamout_dirty; }; -static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) -{ - if (tiling_flags & RADEON_TILING_MACRO) - return ARRAY_2D_TILED_THIN1; - else if (tiling_flags & RADEON_TILING_MICRO) - return ARRAY_1D_TILED_THIN1; - else - return ARRAY_LINEAR_GENERAL; -} - -static u32 evergreen_cs_get_num_banks(u32 nbanks) -{ - switch (nbanks) { - case 2: - return ADDR_SURF_2_BANK; - case 4: - return ADDR_SURF_4_BANK; - case 8: - default: - return ADDR_SURF_8_BANK; - case 16: - return ADDR_SURF_16_BANK; - } -} - static void evergreen_cs_track_init(struct evergreen_cs_track *track) { int i; @@ -119,745 +89,56 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track) } for (i = 0; i < 12; i++) { + track->cb_color_base_last[i] = 0; track->cb_color_bo[i] = NULL; track->cb_color_bo_offset[i] = 0xFFFFFFFF; track->cb_color_info[i] = 0; - track->cb_color_view[i] = 0xFFFFFFFF; + track->cb_color_view[i] = 0; + track->cb_color_pitch_idx[i] = 0; + track->cb_color_slice_idx[i] = 0; + track->cb_color_dim[i] = 0; track->cb_color_pitch[i] = 0; track->cb_color_slice[i] = 0; + track->cb_color_dim[i] = 0; } track->cb_target_mask = 0xFFFFFFFF; track->cb_shader_mask = 0xFFFFFFFF; - track->cb_dirty = true; track->db_depth_view = 0xFFFFC000; track->db_depth_size = 0xFFFFFFFF; + track->db_depth_size_idx = 0; track->db_depth_control = 0xFFFFFFFF; track->db_z_info = 0xFFFFFFFF; + track->db_z_idx = 0xFFFFFFFF; track->db_z_read_offset = 0xFFFFFFFF; track->db_z_write_offset = 0xFFFFFFFF; track->db_z_read_bo = NULL; track->db_z_write_bo = NULL; track->db_s_info = 0xFFFFFFFF; + track->db_s_idx = 0xFFFFFFFF; track->db_s_read_offset = 0xFFFFFFFF; track->db_s_write_offset = 0xFFFFFFFF; track->db_s_read_bo = NULL; track->db_s_write_bo = NULL; - track->db_dirty = true; - - for (i = 0; i < 4; i++) { - track->vgt_strmout_size[i] = 0; - track->vgt_strmout_bo[i] = NULL; - track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; - } - track->streamout_dirty = true; - track->sx_misc_kill_all_prims = false; -} - -struct eg_surface { - /* value gathered from cs */ - unsigned nbx; - unsigned nby; - unsigned format; - unsigned mode; - unsigned nbanks; - unsigned bankw; - unsigned bankh; - unsigned tsplit; - unsigned mtilea; - unsigned nsamples; - /* output value */ - unsigned bpe; - unsigned layer_size; - unsigned palign; - unsigned halign; - unsigned long base_align; -}; - -static int evergreen_surface_check_linear(struct radeon_cs_parser *p, - struct eg_surface *surf, - const char *prefix) -{ - surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; - surf->base_align = surf->bpe; - surf->palign = 1; - surf->halign = 1; - return 0; -} - -static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p, - struct eg_surface *surf, - const char *prefix) -{ - struct evergreen_cs_track *track = p->track; - unsigned palign; - - palign = MAX(64, track->group_size / surf->bpe); - surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; - surf->base_align = track->group_size; - surf->palign = palign; - surf->halign = 1; - if (surf->nbx & (palign - 1)) { - if (prefix) { - dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", - __func__, __LINE__, prefix, surf->nbx, palign); - } - return -EINVAL; - } - return 0; -} - -static int evergreen_surface_check_1d(struct radeon_cs_parser *p, - struct eg_surface *surf, - const char *prefix) -{ - struct evergreen_cs_track *track = p->track; - unsigned palign; - - palign = track->group_size / (8 * surf->bpe * surf->nsamples); - palign = MAX(8, palign); - surf->layer_size = surf->nbx * surf->nby * surf->bpe; - surf->base_align = track->group_size; - surf->palign = palign; - surf->halign = 8; - if ((surf->nbx & (palign - 1))) { - if (prefix) { - dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n", - __func__, __LINE__, prefix, surf->nbx, palign, - track->group_size, surf->bpe, surf->nsamples); - } - return -EINVAL; - } - if ((surf->nby & (8 - 1))) { - if (prefix) { - dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n", - __func__, __LINE__, prefix, surf->nby); - } - return -EINVAL; - } - return 0; -} - -static int evergreen_surface_check_2d(struct radeon_cs_parser *p, - struct eg_surface *surf, - const char *prefix) -{ - struct evergreen_cs_track *track = p->track; - unsigned palign, halign, tileb, slice_pt; - - tileb = 64 * surf->bpe * surf->nsamples; - palign = track->group_size / (8 * surf->bpe * surf->nsamples); - palign = MAX(8, palign); - slice_pt = 1; - if (tileb > surf->tsplit) { - slice_pt = tileb / surf->tsplit; - } - tileb = tileb / slice_pt; - /* macro tile width & height */ - palign = (8 * surf->bankw * track->npipes) * surf->mtilea; - halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea; - surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt; - surf->base_align = (palign / 8) * (halign / 8) * tileb; - surf->palign = palign; - surf->halign = halign; - - if ((surf->nbx & (palign - 1))) { - if (prefix) { - dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", - __func__, __LINE__, prefix, surf->nbx, palign); - } - return -EINVAL; - } - if ((surf->nby & (halign - 1))) { - if (prefix) { - dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n", - __func__, __LINE__, prefix, surf->nby, halign); - } - return -EINVAL; - } - - return 0; -} - -static int evergreen_surface_check(struct radeon_cs_parser *p, - struct eg_surface *surf, - const char *prefix) -{ - /* some common value computed here */ - surf->bpe = r600_fmt_get_blocksize(surf->format); - - switch (surf->mode) { - case ARRAY_LINEAR_GENERAL: - return evergreen_surface_check_linear(p, surf, prefix); - case ARRAY_LINEAR_ALIGNED: - return evergreen_surface_check_linear_aligned(p, surf, prefix); - case ARRAY_1D_TILED_THIN1: - return evergreen_surface_check_1d(p, surf, prefix); - case ARRAY_2D_TILED_THIN1: - return evergreen_surface_check_2d(p, surf, prefix); - default: - dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", - __func__, __LINE__, prefix, surf->mode); - return -EINVAL; - } - return -EINVAL; -} - -static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p, - struct eg_surface *surf, - const char *prefix) -{ - switch (surf->mode) { - case ARRAY_2D_TILED_THIN1: - break; - case ARRAY_LINEAR_GENERAL: - case ARRAY_LINEAR_ALIGNED: - case ARRAY_1D_TILED_THIN1: - return 0; - default: - dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", - __func__, __LINE__, prefix, surf->mode); - return -EINVAL; - } - - switch (surf->nbanks) { - case 0: surf->nbanks = 2; break; - case 1: surf->nbanks = 4; break; - case 2: surf->nbanks = 8; break; - case 3: surf->nbanks = 16; break; - default: - dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n", - __func__, __LINE__, prefix, surf->nbanks); - return -EINVAL; - } - switch (surf->bankw) { - case 0: surf->bankw = 1; break; - case 1: surf->bankw = 2; break; - case 2: surf->bankw = 4; break; - case 3: surf->bankw = 8; break; - default: - dev_warn(p->dev, "%s:%d %s invalid bankw %d\n", - __func__, __LINE__, prefix, surf->bankw); - return -EINVAL; - } - switch (surf->bankh) { - case 0: surf->bankh = 1; break; - case 1: surf->bankh = 2; break; - case 2: surf->bankh = 4; break; - case 3: surf->bankh = 8; break; - default: - dev_warn(p->dev, "%s:%d %s invalid bankh %d\n", - __func__, __LINE__, prefix, surf->bankh); - return -EINVAL; - } - switch (surf->mtilea) { - case 0: surf->mtilea = 1; break; - case 1: surf->mtilea = 2; break; - case 2: surf->mtilea = 4; break; - case 3: surf->mtilea = 8; break; - default: - dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n", - __func__, __LINE__, prefix, surf->mtilea); - return -EINVAL; - } - switch (surf->tsplit) { - case 0: surf->tsplit = 64; break; - case 1: surf->tsplit = 128; break; - case 2: surf->tsplit = 256; break; - case 3: surf->tsplit = 512; break; - case 4: surf->tsplit = 1024; break; - case 5: surf->tsplit = 2048; break; - case 6: surf->tsplit = 4096; break; - default: - dev_warn(p->dev, "%s:%d %s invalid tile split %d\n", - __func__, __LINE__, prefix, surf->tsplit); - return -EINVAL; - } - return 0; } -static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id) +static inline int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, int i) { - struct evergreen_cs_track *track = p->track; - struct eg_surface surf; - unsigned pitch, slice, mslice; - unsigned long offset; - int r; - - mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1; - pitch = track->cb_color_pitch[id]; - slice = track->cb_color_slice[id]; - surf.nbx = (pitch + 1) * 8; - surf.nby = ((slice + 1) * 64) / surf.nbx; - surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]); - surf.format = G_028C70_FORMAT(track->cb_color_info[id]); - surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]); - surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]); - surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); - surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]); - surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]); - surf.nsamples = 1; - - if (!r600_fmt_is_valid_color(surf.format)) { - dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n", - __func__, __LINE__, surf.format, - id, track->cb_color_info[id]); - return -EINVAL; - } - - r = evergreen_surface_value_conv_check(p, &surf, "cb"); - if (r) { - return r; - } - - r = evergreen_surface_check(p, &surf, "cb"); - if (r) { - dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", - __func__, __LINE__, id, track->cb_color_pitch[id], - track->cb_color_slice[id], track->cb_color_attrib[id], - track->cb_color_info[id]); - return r; - } - - offset = track->cb_color_bo_offset[id] << 8; - if (offset & (surf.base_align - 1)) { - dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n", - __func__, __LINE__, id, offset, surf.base_align); - return -EINVAL; - } - - offset += surf.layer_size * mslice; - if (offset > radeon_bo_size(track->cb_color_bo[id])) { - dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, " - "offset %d, max layer %d, bo size %ld, slice %d)\n", - __func__, __LINE__, id, surf.layer_size, - track->cb_color_bo_offset[id] << 8, mslice, - radeon_bo_size(track->cb_color_bo[id]), slice); - dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", - __func__, __LINE__, surf.nbx, surf.nby, - surf.mode, surf.bpe, surf.nsamples, - surf.bankw, surf.bankh, - surf.tsplit, surf.mtilea); - return -EINVAL; - } - - return 0; -} - -static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p) -{ - struct evergreen_cs_track *track = p->track; - struct eg_surface surf; - unsigned pitch, slice, mslice; - unsigned long offset; - int r; - - mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; - pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); - slice = track->db_depth_slice; - surf.nbx = (pitch + 1) * 8; - surf.nby = ((slice + 1) * 64) / surf.nbx; - surf.mode = G_028040_ARRAY_MODE(track->db_z_info); - surf.format = G_028044_FORMAT(track->db_s_info); - surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info); - surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); - surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); - surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); - surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); - surf.nsamples = 1; - - if (surf.format != 1) { - dev_warn(p->dev, "%s:%d stencil invalid format %d\n", - __func__, __LINE__, surf.format); - return -EINVAL; - } - /* replace by color format so we can use same code */ - surf.format = V_028C70_COLOR_8; - - r = evergreen_surface_value_conv_check(p, &surf, "stencil"); - if (r) { - return r; - } - - r = evergreen_surface_check(p, &surf, NULL); - if (r) { - /* old userspace doesn't compute proper depth/stencil alignment - * check that alignment against a bigger byte per elements and - * only report if that alignment is wrong too. - */ - surf.format = V_028C70_COLOR_8_8_8_8; - r = evergreen_surface_check(p, &surf, "stencil"); - if (r) { - dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", - __func__, __LINE__, track->db_depth_size, - track->db_depth_slice, track->db_s_info, track->db_z_info); - } - return r; - } - - offset = track->db_s_read_offset << 8; - if (offset & (surf.base_align - 1)) { - dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n", - __func__, __LINE__, offset, surf.base_align); - return -EINVAL; - } - offset += surf.layer_size * mslice; - if (offset > radeon_bo_size(track->db_s_read_bo)) { - dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, " - "offset %ld, max layer %d, bo size %ld)\n", - __func__, __LINE__, surf.layer_size, - (unsigned long)track->db_s_read_offset << 8, mslice, - radeon_bo_size(track->db_s_read_bo)); - dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", - __func__, __LINE__, track->db_depth_size, - track->db_depth_slice, track->db_s_info, track->db_z_info); - return -EINVAL; - } - - offset = track->db_s_write_offset << 8; - if (offset & (surf.base_align - 1)) { - dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n", - __func__, __LINE__, offset, surf.base_align); - return -EINVAL; - } - offset += surf.layer_size * mslice; - if (offset > radeon_bo_size(track->db_s_write_bo)) { - dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, " - "offset %ld, max layer %d, bo size %ld)\n", - __func__, __LINE__, surf.layer_size, - (unsigned long)track->db_s_write_offset << 8, mslice, - radeon_bo_size(track->db_s_write_bo)); - return -EINVAL; - } - - return 0; -} - -static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p) -{ - struct evergreen_cs_track *track = p->track; - struct eg_surface surf; - unsigned pitch, slice, mslice; - unsigned long offset; - int r; - - mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; - pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); - slice = track->db_depth_slice; - surf.nbx = (pitch + 1) * 8; - surf.nby = ((slice + 1) * 64) / surf.nbx; - surf.mode = G_028040_ARRAY_MODE(track->db_z_info); - surf.format = G_028040_FORMAT(track->db_z_info); - surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info); - surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); - surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); - surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); - surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); - surf.nsamples = 1; - - switch (surf.format) { - case V_028040_Z_16: - surf.format = V_028C70_COLOR_16; - break; - case V_028040_Z_24: - case V_028040_Z_32_FLOAT: - surf.format = V_028C70_COLOR_8_8_8_8; - break; - default: - dev_warn(p->dev, "%s:%d depth invalid format %d\n", - __func__, __LINE__, surf.format); - return -EINVAL; - } - - r = evergreen_surface_value_conv_check(p, &surf, "depth"); - if (r) { - dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", - __func__, __LINE__, track->db_depth_size, - track->db_depth_slice, track->db_z_info); - return r; - } - - r = evergreen_surface_check(p, &surf, "depth"); - if (r) { - dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", - __func__, __LINE__, track->db_depth_size, - track->db_depth_slice, track->db_z_info); - return r; - } - - offset = track->db_z_read_offset << 8; - if (offset & (surf.base_align - 1)) { - dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n", - __func__, __LINE__, offset, surf.base_align); - return -EINVAL; - } - offset += surf.layer_size * mslice; - if (offset > radeon_bo_size(track->db_z_read_bo)) { - dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, " - "offset %ld, max layer %d, bo size %ld)\n", - __func__, __LINE__, surf.layer_size, - (unsigned long)track->db_z_read_offset << 8, mslice, - radeon_bo_size(track->db_z_read_bo)); - return -EINVAL; - } - - offset = track->db_z_write_offset << 8; - if (offset & (surf.base_align - 1)) { - dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n", - __func__, __LINE__, offset, surf.base_align); - return -EINVAL; - } - offset += surf.layer_size * mslice; - if (offset > radeon_bo_size(track->db_z_write_bo)) { - dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, " - "offset %ld, max layer %d, bo size %ld)\n", - __func__, __LINE__, surf.layer_size, - (unsigned long)track->db_z_write_offset << 8, mslice, - radeon_bo_size(track->db_z_write_bo)); - return -EINVAL; - } - - return 0; -} - -static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p, - struct radeon_bo *texture, - struct radeon_bo *mipmap, - unsigned idx) -{ - struct eg_surface surf; - unsigned long toffset, moffset; - unsigned dim, llevel, mslice, width, height, depth, i; - u32 texdw[8]; - int r; - - texdw[0] = radeon_get_ib_value(p, idx + 0); - texdw[1] = radeon_get_ib_value(p, idx + 1); - texdw[2] = radeon_get_ib_value(p, idx + 2); - texdw[3] = radeon_get_ib_value(p, idx + 3); - texdw[4] = radeon_get_ib_value(p, idx + 4); - texdw[5] = radeon_get_ib_value(p, idx + 5); - texdw[6] = radeon_get_ib_value(p, idx + 6); - texdw[7] = radeon_get_ib_value(p, idx + 7); - dim = G_030000_DIM(texdw[0]); - llevel = G_030014_LAST_LEVEL(texdw[5]); - mslice = G_030014_LAST_ARRAY(texdw[5]) + 1; - width = G_030000_TEX_WIDTH(texdw[0]) + 1; - height = G_030004_TEX_HEIGHT(texdw[1]) + 1; - depth = G_030004_TEX_DEPTH(texdw[1]) + 1; - surf.format = G_03001C_DATA_FORMAT(texdw[7]); - surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8; - surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx); - surf.nby = r600_fmt_get_nblocksy(surf.format, height); - surf.mode = G_030004_ARRAY_MODE(texdw[1]); - surf.tsplit = G_030018_TILE_SPLIT(texdw[6]); - surf.nbanks = G_03001C_NUM_BANKS(texdw[7]); - surf.bankw = G_03001C_BANK_WIDTH(texdw[7]); - surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]); - surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]); - surf.nsamples = 1; - toffset = texdw[2] << 8; - moffset = texdw[3] << 8; - - if (!r600_fmt_is_valid_texture(surf.format, p->family)) { - dev_warn(p->dev, "%s:%d texture invalid format %d\n", - __func__, __LINE__, surf.format); - return -EINVAL; - } - switch (dim) { - case V_030000_SQ_TEX_DIM_1D: - case V_030000_SQ_TEX_DIM_2D: - case V_030000_SQ_TEX_DIM_CUBEMAP: - case V_030000_SQ_TEX_DIM_1D_ARRAY: - case V_030000_SQ_TEX_DIM_2D_ARRAY: - depth = 1; - case V_030000_SQ_TEX_DIM_3D: - break; - default: - dev_warn(p->dev, "%s:%d texture invalid dimension %d\n", - __func__, __LINE__, dim); - return -EINVAL; - } - - r = evergreen_surface_value_conv_check(p, &surf, "texture"); - if (r) { - return r; - } - - /* align height */ - evergreen_surface_check(p, &surf, NULL); - surf.nby = ALIGN(surf.nby, surf.halign); - - r = evergreen_surface_check(p, &surf, "texture"); - if (r) { - dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", - __func__, __LINE__, texdw[0], texdw[1], texdw[4], - texdw[5], texdw[6], texdw[7]); - return r; - } - - /* check texture size */ - if (toffset & (surf.base_align - 1)) { - dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n", - __func__, __LINE__, toffset, surf.base_align); - return -EINVAL; - } - if (moffset & (surf.base_align - 1)) { - dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n", - __func__, __LINE__, moffset, surf.base_align); - return -EINVAL; - } - if (dim == SQ_TEX_DIM_3D) { - toffset += surf.layer_size * depth; - } else { - toffset += surf.layer_size * mslice; - } - if (toffset > radeon_bo_size(texture)) { - dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, " - "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n", - __func__, __LINE__, surf.layer_size, - (unsigned long)texdw[2] << 8, mslice, - depth, radeon_bo_size(texture), - surf.nbx, surf.nby); - return -EINVAL; - } - - /* check mipmap size */ - for (i = 1; i <= llevel; i++) { - unsigned w, h, d; - - w = r600_mip_minify(width, i); - h = r600_mip_minify(height, i); - d = r600_mip_minify(depth, i); - surf.nbx = r600_fmt_get_nblocksx(surf.format, w); - surf.nby = r600_fmt_get_nblocksy(surf.format, h); - - switch (surf.mode) { - case ARRAY_2D_TILED_THIN1: - if (surf.nbx < surf.palign || surf.nby < surf.halign) { - surf.mode = ARRAY_1D_TILED_THIN1; - } - /* recompute alignment */ - evergreen_surface_check(p, &surf, NULL); - break; - case ARRAY_LINEAR_GENERAL: - case ARRAY_LINEAR_ALIGNED: - case ARRAY_1D_TILED_THIN1: - break; - default: - dev_warn(p->dev, "%s:%d invalid array mode %d\n", - __func__, __LINE__, surf.mode); - return -EINVAL; - } - surf.nbx = ALIGN(surf.nbx, surf.palign); - surf.nby = ALIGN(surf.nby, surf.halign); - - r = evergreen_surface_check(p, &surf, "mipmap"); - if (r) { - return r; - } - - if (dim == SQ_TEX_DIM_3D) { - moffset += surf.layer_size * d; - } else { - moffset += surf.layer_size * mslice; - } - if (moffset > radeon_bo_size(mipmap)) { - dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, " - "offset %ld, coffset %ld, max layer %d, depth %d, " - "bo size %ld) level0 (%d %d %d)\n", - __func__, __LINE__, i, surf.layer_size, - (unsigned long)texdw[3] << 8, moffset, mslice, - d, radeon_bo_size(mipmap), - width, height, depth); - dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", - __func__, __LINE__, surf.nbx, surf.nby, - surf.mode, surf.bpe, surf.nsamples, - surf.bankw, surf.bankh, - surf.tsplit, surf.mtilea); - return -EINVAL; - } - } - + /* XXX fill in */ return 0; } static int evergreen_cs_track_check(struct radeon_cs_parser *p) { struct evergreen_cs_track *track = p->track; - unsigned tmp, i; - int r; - unsigned buffer_mask = 0; - /* check streamout */ - if (track->streamout_dirty && track->vgt_strmout_config) { - for (i = 0; i < 4; i++) { - if (track->vgt_strmout_config & (1 << i)) { - buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf; - } - } - - for (i = 0; i < 4; i++) { - if (buffer_mask & (1 << i)) { - if (track->vgt_strmout_bo[i]) { - u64 offset = (u64)track->vgt_strmout_bo_offset[i] + - (u64)track->vgt_strmout_size[i]; - if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { - DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n", - i, offset, - radeon_bo_size(track->vgt_strmout_bo[i])); - return -EINVAL; - } - } else { - dev_warn(p->dev, "No buffer for streamout %d\n", i); - return -EINVAL; - } - } - } - track->streamout_dirty = false; - } - - if (track->sx_misc_kill_all_prims) - return 0; - - /* check that we have a cb for each enabled target - */ - if (track->cb_dirty) { - tmp = track->cb_target_mask; - for (i = 0; i < 8; i++) { - if ((tmp >> (i * 4)) & 0xF) { - /* at least one component is enabled */ - if (track->cb_color_bo[i] == NULL) { - dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", - __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); - return -EINVAL; - } - /* check cb */ - r = evergreen_cs_track_validate_cb(p, i); - if (r) { - return r; - } - } - } - track->cb_dirty = false; - } - - if (track->db_dirty) { - /* Check stencil buffer */ - if (G_028800_STENCIL_ENABLE(track->db_depth_control)) { - r = evergreen_cs_track_validate_stencil(p); - if (r) - return r; - } - /* Check depth buffer */ - if (G_028800_Z_WRITE_ENABLE(track->db_depth_control)) { - r = evergreen_cs_track_validate_depth(p); - if (r) - return r; - } - track->db_dirty = false; + /* we don't support stream out buffer yet */ + if (track->vgt_strmout_config || track->vgt_strmout_buffer_config) { + dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n"); + return -EINVAL; } + /* XXX fill in */ return 0; } @@ -955,6 +236,28 @@ static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, } /** + * evergreen_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc + * @parser: parser structure holding parsing context. + * + * Check next packet is relocation packet3, do bo validation and compute + * GPU offset using the provided start. + **/ +static inline int evergreen_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) +{ + struct radeon_cs_packet p3reloc; + int r; + + r = evergreen_cs_packet_parse(p, &p3reloc, p->idx); + if (r) { + return 0; + } + if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { + return 0; + } + return 1; +} + +/** * evergreen_cs_packet_next_vline() - parse userspace VLINE packet * @parser: parser structure holding parsing context. * @@ -1111,7 +414,7 @@ static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p, * if register is safe. If register is not flag as safe this function * will test it against a list of register needind special handling. */ -static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) { struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track; struct radeon_cs_reloc *reloc; @@ -1125,7 +428,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) last_reg = ARRAY_SIZE(evergreen_reg_safe_bm); i = (reg >> 7); - if (i >= last_reg) { + if (i > last_reg) { dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); return -EINVAL; } @@ -1189,7 +492,6 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) break; case DB_DEPTH_CONTROL: track->db_depth_control = radeon_get_ib_value(p, idx); - track->db_dirty = true; break; case CAYMAN_DB_EQAA: if (p->rdev->family < CHIP_CAYMAN) { @@ -1206,48 +508,32 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) } break; case DB_Z_INFO: + r = evergreen_cs_packet_next_reloc(p, &reloc); + if (r) { + dev_warn(p->dev, "bad SET_CONTEXT_REG " + "0x%04X\n", reg); + return -EINVAL; + } track->db_z_info = radeon_get_ib_value(p, idx); - if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - dev_warn(p->dev, "bad SET_CONTEXT_REG " - "0x%04X\n", reg); - return -EINVAL; - } - ib[idx] &= ~Z_ARRAY_MODE(0xf); - track->db_z_info &= ~Z_ARRAY_MODE(0xf); - ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); - track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { - unsigned bankw, bankh, mtaspect, tile_split; - - evergreen_tiling_fields(reloc->lobj.tiling_flags, - &bankw, &bankh, &mtaspect, - &tile_split); - ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); - ib[idx] |= DB_TILE_SPLIT(tile_split) | - DB_BANK_WIDTH(bankw) | - DB_BANK_HEIGHT(bankh) | - DB_MACRO_TILE_ASPECT(mtaspect); - } + ib[idx] &= ~Z_ARRAY_MODE(0xf); + track->db_z_info &= ~Z_ARRAY_MODE(0xf); + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { + ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1); + track->db_z_info |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1); + } else { + ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1); + track->db_z_info |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1); } - track->db_dirty = true; break; case DB_STENCIL_INFO: track->db_s_info = radeon_get_ib_value(p, idx); - track->db_dirty = true; break; case DB_DEPTH_VIEW: track->db_depth_view = radeon_get_ib_value(p, idx); - track->db_dirty = true; break; case DB_DEPTH_SIZE: track->db_depth_size = radeon_get_ib_value(p, idx); - track->db_dirty = true; - break; - case R_02805C_DB_DEPTH_SLICE: - track->db_depth_slice = radeon_get_ib_value(p, idx); - track->db_dirty = true; + track->db_depth_size_idx = idx; break; case DB_Z_READ_BASE: r = evergreen_cs_packet_next_reloc(p, &reloc); @@ -1259,7 +545,6 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) track->db_z_read_offset = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); track->db_z_read_bo = reloc->robj; - track->db_dirty = true; break; case DB_Z_WRITE_BASE: r = evergreen_cs_packet_next_reloc(p, &reloc); @@ -1271,7 +556,6 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) track->db_z_write_offset = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); track->db_z_write_bo = reloc->robj; - track->db_dirty = true; break; case DB_STENCIL_READ_BASE: r = evergreen_cs_packet_next_reloc(p, &reloc); @@ -1283,7 +567,6 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) track->db_s_read_offset = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); track->db_s_read_bo = reloc->robj; - track->db_dirty = true; break; case DB_STENCIL_WRITE_BASE: r = evergreen_cs_packet_next_reloc(p, &reloc); @@ -1295,56 +578,18 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) track->db_s_write_offset = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); track->db_s_write_bo = reloc->robj; - track->db_dirty = true; break; case VGT_STRMOUT_CONFIG: track->vgt_strmout_config = radeon_get_ib_value(p, idx); - track->streamout_dirty = true; break; case VGT_STRMOUT_BUFFER_CONFIG: track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); - track->streamout_dirty = true; break; - case VGT_STRMOUT_BUFFER_BASE_0: - case VGT_STRMOUT_BUFFER_BASE_1: - case VGT_STRMOUT_BUFFER_BASE_2: - case VGT_STRMOUT_BUFFER_BASE_3: - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - dev_warn(p->dev, "bad SET_CONTEXT_REG " - "0x%04X\n", reg); - return -EINVAL; - } - tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; - track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); - track->vgt_strmout_bo[tmp] = reloc->robj; - track->streamout_dirty = true; - break; - case VGT_STRMOUT_BUFFER_SIZE_0: - case VGT_STRMOUT_BUFFER_SIZE_1: - case VGT_STRMOUT_BUFFER_SIZE_2: - case VGT_STRMOUT_BUFFER_SIZE_3: - tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16; - /* size in register is DWs, convert to bytes */ - track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; - track->streamout_dirty = true; - break; - case CP_COHER_BASE: - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - dev_warn(p->dev, "missing reloc for CP_COHER_BASE " - "0x%04X\n", reg); - return -EINVAL; - } - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); case CB_TARGET_MASK: track->cb_target_mask = radeon_get_ib_value(p, idx); - track->cb_dirty = true; break; case CB_SHADER_MASK: track->cb_shader_mask = radeon_get_ib_value(p, idx); - track->cb_dirty = true; break; case PA_SC_AA_CONFIG: if (p->rdev->family >= CHIP_CAYMAN) { @@ -1374,7 +619,6 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) case CB_COLOR7_VIEW: tmp = (reg - CB_COLOR0_VIEW) / 0x3c; track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); - track->cb_dirty = true; break; case CB_COLOR8_VIEW: case CB_COLOR9_VIEW: @@ -1382,7 +626,6 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) case CB_COLOR11_VIEW: tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8; track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); - track->cb_dirty = true; break; case CB_COLOR0_INFO: case CB_COLOR1_INFO: @@ -1392,37 +635,41 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) case CB_COLOR5_INFO: case CB_COLOR6_INFO: case CB_COLOR7_INFO: + r = evergreen_cs_packet_next_reloc(p, &reloc); + if (r) { + dev_warn(p->dev, "bad SET_CONTEXT_REG " + "0x%04X\n", reg); + return -EINVAL; + } tmp = (reg - CB_COLOR0_INFO) / 0x3c; track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); - if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - dev_warn(p->dev, "bad SET_CONTEXT_REG " - "0x%04X\n", reg); - return -EINVAL; - } - ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); - track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { + ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1); + track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1); + } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { + ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1); + track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1); } - track->cb_dirty = true; break; case CB_COLOR8_INFO: case CB_COLOR9_INFO: case CB_COLOR10_INFO: case CB_COLOR11_INFO: + r = evergreen_cs_packet_next_reloc(p, &reloc); + if (r) { + dev_warn(p->dev, "bad SET_CONTEXT_REG " + "0x%04X\n", reg); + return -EINVAL; + } tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8; track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); - if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - dev_warn(p->dev, "bad SET_CONTEXT_REG " - "0x%04X\n", reg); - return -EINVAL; - } - ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); - track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { + ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1); + track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1); + } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { + ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1); + track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1); } - track->cb_dirty = true; break; case CB_COLOR0_PITCH: case CB_COLOR1_PITCH: @@ -1434,7 +681,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) case CB_COLOR7_PITCH: tmp = (reg - CB_COLOR0_PITCH) / 0x3c; track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); - track->cb_dirty = true; + track->cb_color_pitch_idx[tmp] = idx; break; case CB_COLOR8_PITCH: case CB_COLOR9_PITCH: @@ -1442,7 +689,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) case CB_COLOR11_PITCH: tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8; track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); - track->cb_dirty = true; + track->cb_color_pitch_idx[tmp] = idx; break; case CB_COLOR0_SLICE: case CB_COLOR1_SLICE: @@ -1454,7 +701,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) case CB_COLOR7_SLICE: tmp = (reg - CB_COLOR0_SLICE) / 0x3c; track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); - track->cb_dirty = true; + track->cb_color_slice_idx[tmp] = idx; break; case CB_COLOR8_SLICE: case CB_COLOR9_SLICE: @@ -1462,7 +709,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) case CB_COLOR11_SLICE: tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8; track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); - track->cb_dirty = true; + track->cb_color_slice_idx[tmp] = idx; break; case CB_COLOR0_ATTRIB: case CB_COLOR1_ATTRIB: @@ -1472,57 +719,30 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) case CB_COLOR5_ATTRIB: case CB_COLOR6_ATTRIB: case CB_COLOR7_ATTRIB: - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - dev_warn(p->dev, "bad SET_CONTEXT_REG " - "0x%04X\n", reg); - return -EINVAL; - } - if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { - unsigned bankw, bankh, mtaspect, tile_split; - - evergreen_tiling_fields(reloc->lobj.tiling_flags, - &bankw, &bankh, &mtaspect, - &tile_split); - ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); - ib[idx] |= CB_TILE_SPLIT(tile_split) | - CB_BANK_WIDTH(bankw) | - CB_BANK_HEIGHT(bankh) | - CB_MACRO_TILE_ASPECT(mtaspect); - } - } - tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c); - track->cb_color_attrib[tmp] = ib[idx]; - track->cb_dirty = true; - break; case CB_COLOR8_ATTRIB: case CB_COLOR9_ATTRIB: case CB_COLOR10_ATTRIB: case CB_COLOR11_ATTRIB: - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - dev_warn(p->dev, "bad SET_CONTEXT_REG " - "0x%04X\n", reg); - return -EINVAL; - } - if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { - unsigned bankw, bankh, mtaspect, tile_split; - - evergreen_tiling_fields(reloc->lobj.tiling_flags, - &bankw, &bankh, &mtaspect, - &tile_split); - ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); - ib[idx] |= CB_TILE_SPLIT(tile_split) | - CB_BANK_WIDTH(bankw) | - CB_BANK_HEIGHT(bankh) | - CB_MACRO_TILE_ASPECT(mtaspect); - } - } - tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8; - track->cb_color_attrib[tmp] = ib[idx]; - track->cb_dirty = true; + break; + case CB_COLOR0_DIM: + case CB_COLOR1_DIM: + case CB_COLOR2_DIM: + case CB_COLOR3_DIM: + case CB_COLOR4_DIM: + case CB_COLOR5_DIM: + case CB_COLOR6_DIM: + case CB_COLOR7_DIM: + tmp = (reg - CB_COLOR0_DIM) / 0x3c; + track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx); + track->cb_color_dim_idx[tmp] = idx; + break; + case CB_COLOR8_DIM: + case CB_COLOR9_DIM: + case CB_COLOR10_DIM: + case CB_COLOR11_DIM: + tmp = ((reg - CB_COLOR8_DIM) / 0x1c) + 8; + track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx); + track->cb_color_dim_idx[tmp] = idx; break; case CB_COLOR0_FMASK: case CB_COLOR1_FMASK: @@ -1597,8 +817,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) tmp = (reg - CB_COLOR0_BASE) / 0x3c; track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + track->cb_color_base_last[tmp] = ib[idx]; track->cb_color_bo[tmp] = reloc->robj; - track->cb_dirty = true; break; case CB_COLOR8_BASE: case CB_COLOR9_BASE: @@ -1613,8 +833,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8; track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + track->cb_color_base_last[tmp] = ib[idx]; track->cb_color_bo[tmp] = reloc->robj; - track->cb_dirty = true; break; case CB_IMMED0_BASE: case CB_IMMED1_BASE: @@ -1636,6 +856,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) case SQ_PGM_START_PS: case SQ_PGM_START_HS: case SQ_PGM_START_LS: + case GDS_ADDR_BASE: case SQ_CONST_MEM_BASE: case SQ_ALU_CONST_CACHE_GS_0: case SQ_ALU_CONST_CACHE_GS_1: @@ -1725,37 +946,6 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) } ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); break; - case SX_MEMORY_EXPORT_BASE: - if (p->rdev->family >= CHIP_CAYMAN) { - dev_warn(p->dev, "bad SET_CONFIG_REG " - "0x%04X\n", reg); - return -EINVAL; - } - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - dev_warn(p->dev, "bad SET_CONFIG_REG " - "0x%04X\n", reg); - return -EINVAL; - } - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); - break; - case CAYMAN_SX_SCATTER_EXPORT_BASE: - if (p->rdev->family < CHIP_CAYMAN) { - dev_warn(p->dev, "bad SET_CONTEXT_REG " - "0x%04X\n", reg); - return -EINVAL; - } - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - dev_warn(p->dev, "bad SET_CONTEXT_REG " - "0x%04X\n", reg); - return -EINVAL; - } - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); - break; - case SX_MISC: - track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; - break; default: dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); return -EINVAL; @@ -1763,30 +953,22 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) return 0; } -static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +/** + * evergreen_check_texture_resource() - check if register is authorized or not + * @p: parser structure holding parsing context + * @idx: index into the cs buffer + * @texture: texture's bo structure + * @mipmap: mipmap's bo structure + * + * This function will check that the resource has valid field and that + * the texture and mipmap bo object are big enough to cover this resource. + */ +static inline int evergreen_check_texture_resource(struct radeon_cs_parser *p, u32 idx, + struct radeon_bo *texture, + struct radeon_bo *mipmap) { - u32 last_reg, m, i; - - if (p->rdev->family >= CHIP_CAYMAN) - last_reg = ARRAY_SIZE(cayman_reg_safe_bm); - else - last_reg = ARRAY_SIZE(evergreen_reg_safe_bm); - - i = (reg >> 7); - if (i >= last_reg) { - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); - return false; - } - m = 1 << ((reg >> 2) & 31); - if (p->rdev->family >= CHIP_CAYMAN) { - if (!(cayman_reg_safe_bm[i] & m)) - return true; - } else { - if (!(evergreen_reg_safe_bm[i] & m)) - return true; - } - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); - return false; + /* XXX fill in */ + return 0; } static int evergreen_packet3_check(struct radeon_cs_parser *p, @@ -1811,8 +993,6 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, { int pred_op; int tmp; - uint64_t offset; - if (pkt->count != 1) { DRM_ERROR("bad SET PREDICATION\n"); return -EINVAL; @@ -1836,12 +1016,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } - offset = reloc->lobj.gpu_offset + - (idx_value & 0xfffffff0) + - ((u64)(tmp & 0xff) << 32); - - ib[idx + 0] = offset; - ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); + ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx + 1] = tmp + (upper_32_bits(reloc->lobj.gpu_offset) & 0xff); } break; case PACKET3_CONTEXT_CONTROL: @@ -1869,9 +1045,6 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, } break; case PACKET3_INDEX_BASE: - { - uint64_t offset; - if (pkt->count != 1) { DRM_ERROR("bad INDEX_BASE\n"); return -EINVAL; @@ -1881,24 +1054,15 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, DRM_ERROR("bad INDEX_BASE\n"); return -EINVAL; } - - offset = reloc->lobj.gpu_offset + - idx_value + - ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); - - ib[idx+0] = offset; - ib[idx+1] = upper_32_bits(offset) & 0xff; - + ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; r = evergreen_cs_track_check(p); if (r) { dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); return r; } break; - } case PACKET3_DRAW_INDEX: - { - uint64_t offset; if (pkt->count != 3) { DRM_ERROR("bad DRAW_INDEX\n"); return -EINVAL; @@ -1908,25 +1072,15 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, DRM_ERROR("bad DRAW_INDEX\n"); return -EINVAL; } - - offset = reloc->lobj.gpu_offset + - idx_value + - ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); - - ib[idx+0] = offset; - ib[idx+1] = upper_32_bits(offset) & 0xff; - + ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; r = evergreen_cs_track_check(p); if (r) { dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); return r; } break; - } case PACKET3_DRAW_INDEX_2: - { - uint64_t offset; - if (pkt->count != 4) { DRM_ERROR("bad DRAW_INDEX_2\n"); return -EINVAL; @@ -1936,21 +1090,14 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, DRM_ERROR("bad DRAW_INDEX_2\n"); return -EINVAL; } - - offset = reloc->lobj.gpu_offset + - radeon_get_ib_value(p, idx+1) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); - - ib[idx+1] = offset; - ib[idx+2] = upper_32_bits(offset) & 0xff; - + ib[idx+1] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; r = evergreen_cs_track_check(p); if (r) { dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); return r; } break; - } case PACKET3_DRAW_INDEX_AUTO: if (pkt->count != 1) { DRM_ERROR("bad DRAW_INDEX_AUTO\n"); @@ -2006,34 +1153,6 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, return r; } break; - case PACKET3_DISPATCH_DIRECT: - if (pkt->count != 3) { - DRM_ERROR("bad DISPATCH_DIRECT\n"); - return -EINVAL; - } - r = evergreen_cs_track_check(p); - if (r) { - dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); - return r; - } - break; - case PACKET3_DISPATCH_INDIRECT: - if (pkt->count != 1) { - DRM_ERROR("bad DISPATCH_INDIRECT\n"); - return -EINVAL; - } - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("bad DISPATCH_INDIRECT\n"); - return -EINVAL; - } - ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); - r = evergreen_cs_track_check(p); - if (r) { - dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); - return r; - } - break; case PACKET3_WAIT_REG_MEM: if (pkt->count != 5) { DRM_ERROR("bad WAIT_REG_MEM\n"); @@ -2041,20 +1160,13 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, } /* bit 4 is reg (0) or mem (1) */ if (idx_value & 0x10) { - uint64_t offset; - r = evergreen_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("bad WAIT_REG_MEM\n"); return -EINVAL; } - - offset = reloc->lobj.gpu_offset + - (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); - - ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); - ib[idx+2] = upper_32_bits(offset) & 0xff; + ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; } break; case PACKET3_SURFACE_SYNC: @@ -2079,25 +1191,16 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } if (pkt->count) { - uint64_t offset; - r = evergreen_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("bad EVENT_WRITE\n"); return -EINVAL; } - offset = reloc->lobj.gpu_offset + - (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); - - ib[idx+1] = offset & 0xfffffff8; - ib[idx+2] = upper_32_bits(offset) & 0xff; + ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; } break; case PACKET3_EVENT_WRITE_EOP: - { - uint64_t offset; - if (pkt->count != 4) { DRM_ERROR("bad EVENT_WRITE_EOP\n"); return -EINVAL; @@ -2107,19 +1210,10 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, DRM_ERROR("bad EVENT_WRITE_EOP\n"); return -EINVAL; } - - offset = reloc->lobj.gpu_offset + - (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); - - ib[idx+1] = offset & 0xfffffffc; - ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); + ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; break; - } case PACKET3_EVENT_WRITE_EOS: - { - uint64_t offset; - if (pkt->count != 3) { DRM_ERROR("bad EVENT_WRITE_EOS\n"); return -EINVAL; @@ -2129,15 +1223,9 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, DRM_ERROR("bad EVENT_WRITE_EOS\n"); return -EINVAL; } - - offset = reloc->lobj.gpu_offset + - (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); - - ib[idx+1] = offset & 0xfffffffc; - ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); + ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; break; - } case PACKET3_SET_CONFIG_REG: start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; end_reg = 4 * pkt->count + start_reg - 4; @@ -2185,7 +1273,6 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, } for (i = 0; i < (pkt->count / 8); i++) { struct radeon_bo *texture, *mipmap; - u32 toffset, moffset; u32 size, offset; switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { @@ -2196,42 +1283,26 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, DRM_ERROR("bad SET_RESOURCE (tex)\n"); return -EINVAL; } - if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { - ib[idx+1+(i*8)+1] |= - TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { - unsigned bankw, bankh, mtaspect, tile_split; - - evergreen_tiling_fields(reloc->lobj.tiling_flags, - &bankw, &bankh, &mtaspect, - &tile_split); - ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); - ib[idx+1+(i*8)+7] |= - TEX_BANK_WIDTH(bankw) | - TEX_BANK_HEIGHT(bankh) | - MACRO_TILE_ASPECT(mtaspect) | - TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); - } - } + ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) + ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1); + else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) + ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1); texture = reloc->robj; - toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); /* tex mip base */ r = evergreen_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("bad SET_RESOURCE (tex)\n"); return -EINVAL; } - moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); mipmap = reloc->robj; - r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); + r = evergreen_check_texture_resource(p, idx+1+(i*8), + texture, mipmap); if (r) return r; - ib[idx+1+(i*8)+2] += toffset; - ib[idx+1+(i*8)+3] += moffset; break; case SQ_TEX_VTX_VALID_BUFFER: - { - uint64_t offset64; /* vtx base */ r = evergreen_cs_packet_next_reloc(p, &reloc); if (r) { @@ -2243,15 +1314,11 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { /* force size to size of the buffer */ dev_warn(p->dev, "vbo resource seems too big for the bo\n"); - ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; + ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj); } - - offset64 = reloc->lobj.gpu_offset + offset; - ib[idx+1+(i*8)+0] = offset64; - ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | - (upper_32_bits(offset64) & 0xff); + ib[idx+1+(i*8)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); + ib[idx+1+(i*8)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; break; - } case SQ_TEX_VTX_INVALID_TEXTURE: case SQ_TEX_VTX_INVALID_BUFFER: default: @@ -2307,104 +1374,6 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } break; - case PACKET3_STRMOUT_BUFFER_UPDATE: - if (pkt->count != 4) { - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); - return -EINVAL; - } - /* Updating memory at DST_ADDRESS. */ - if (idx_value & 0x1) { - u64 offset; - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); - return -EINVAL; - } - offset = radeon_get_ib_value(p, idx+1); - offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; - if ((offset + 4) > radeon_bo_size(reloc->robj)) { - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n", - offset + 4, radeon_bo_size(reloc->robj)); - return -EINVAL; - } - offset += reloc->lobj.gpu_offset; - ib[idx+1] = offset; - ib[idx+2] = upper_32_bits(offset) & 0xff; - } - /* Reading data from SRC_ADDRESS. */ - if (((idx_value >> 1) & 0x3) == 2) { - u64 offset; - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); - return -EINVAL; - } - offset = radeon_get_ib_value(p, idx+3); - offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; - if ((offset + 4) > radeon_bo_size(reloc->robj)) { - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n", - offset + 4, radeon_bo_size(reloc->robj)); - return -EINVAL; - } - offset += reloc->lobj.gpu_offset; - ib[idx+3] = offset; - ib[idx+4] = upper_32_bits(offset) & 0xff; - } - break; - case PACKET3_COPY_DW: - if (pkt->count != 4) { - DRM_ERROR("bad COPY_DW (invalid count)\n"); - return -EINVAL; - } - if (idx_value & 0x1) { - u64 offset; - /* SRC is memory. */ - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("bad COPY_DW (missing src reloc)\n"); - return -EINVAL; - } - offset = radeon_get_ib_value(p, idx+1); - offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; - if ((offset + 4) > radeon_bo_size(reloc->robj)) { - DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n", - offset + 4, radeon_bo_size(reloc->robj)); - return -EINVAL; - } - offset += reloc->lobj.gpu_offset; - ib[idx+1] = offset; - ib[idx+2] = upper_32_bits(offset) & 0xff; - } else { - /* SRC is a reg. */ - reg = radeon_get_ib_value(p, idx+1) << 2; - if (!evergreen_is_safe_reg(p, reg, idx+1)) - return -EINVAL; - } - if (idx_value & 0x2) { - u64 offset; - /* DST is memory. */ - r = evergreen_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); - return -EINVAL; - } - offset = radeon_get_ib_value(p, idx+3); - offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; - if ((offset + 4) > radeon_bo_size(reloc->robj)) { - DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n", - offset + 4, radeon_bo_size(reloc->robj)); - return -EINVAL; - } - offset += reloc->lobj.gpu_offset; - ib[idx+3] = offset; - ib[idx+4] = upper_32_bits(offset) & 0xff; - } else { - /* DST is a reg. */ - reg = radeon_get_ib_value(p, idx+3) << 2; - if (!evergreen_is_safe_reg(p, reg, idx+3)) - return -EINVAL; - } - break; case PACKET3_NOP: break; default: @@ -2418,7 +1387,6 @@ int evergreen_cs_parse(struct radeon_cs_parser *p) { struct radeon_cs_packet pkt; struct evergreen_cs_track *track; - u32 tmp; int r; if (p->track == NULL) { @@ -2427,63 +1395,9 @@ int evergreen_cs_parse(struct radeon_cs_parser *p) if (track == NULL) return -ENOMEM; evergreen_cs_track_init(track); - if (p->rdev->family >= CHIP_CAYMAN) - tmp = p->rdev->config.cayman.tile_config; - else - tmp = p->rdev->config.evergreen.tile_config; - - switch (tmp & 0xf) { - case 0: - track->npipes = 1; - break; - case 1: - default: - track->npipes = 2; - break; - case 2: - track->npipes = 4; - break; - case 3: - track->npipes = 8; - break; - } - - switch ((tmp & 0xf0) >> 4) { - case 0: - track->nbanks = 4; - break; - case 1: - default: - track->nbanks = 8; - break; - case 2: - track->nbanks = 16; - break; - } - - switch ((tmp & 0xf00) >> 8) { - case 0: - track->group_size = 256; - break; - case 1: - default: - track->group_size = 512; - break; - } - - switch ((tmp & 0xf000) >> 12) { - case 0: - track->row_size = 1; - break; - case 1: - default: - track->row_size = 2; - break; - case 2: - track->row_size = 4; - break; - } - + track->npipes = p->rdev->config.evergreen.tiling_npipes; + track->nbanks = p->rdev->config.evergreen.tiling_nbanks; + track->group_size = p->rdev->config.evergreen.tiling_group_size; p->track = track; } do { @@ -2526,242 +1440,3 @@ int evergreen_cs_parse(struct radeon_cs_parser *p) return 0; } -/* vm parser */ -static bool evergreen_vm_reg_valid(u32 reg) -{ - /* context regs are fine */ - if (reg >= 0x28000) - return true; - - /* check config regs */ - switch (reg) { - case GRBM_GFX_INDEX: - case VGT_VTX_VECT_EJECT_REG: - case VGT_CACHE_INVALIDATION: - case VGT_GS_VERTEX_REUSE: - case VGT_PRIMITIVE_TYPE: - case VGT_INDEX_TYPE: - case VGT_NUM_INDICES: - case VGT_NUM_INSTANCES: - case VGT_COMPUTE_DIM_X: - case VGT_COMPUTE_DIM_Y: - case VGT_COMPUTE_DIM_Z: - case VGT_COMPUTE_START_X: - case VGT_COMPUTE_START_Y: - case VGT_COMPUTE_START_Z: - case VGT_COMPUTE_INDEX: - case VGT_COMPUTE_THREAD_GROUP_SIZE: - case VGT_HS_OFFCHIP_PARAM: - case PA_CL_ENHANCE: - case PA_SU_LINE_STIPPLE_VALUE: - case PA_SC_LINE_STIPPLE_STATE: - case PA_SC_ENHANCE: - case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ: - case SQ_DYN_GPR_SIMD_LOCK_EN: - case SQ_CONFIG: - case SQ_GPR_RESOURCE_MGMT_1: - case SQ_GLOBAL_GPR_RESOURCE_MGMT_1: - case SQ_GLOBAL_GPR_RESOURCE_MGMT_2: - case SQ_CONST_MEM_BASE: - case SQ_STATIC_THREAD_MGMT_1: - case SQ_STATIC_THREAD_MGMT_2: - case SQ_STATIC_THREAD_MGMT_3: - case SPI_CONFIG_CNTL: - case SPI_CONFIG_CNTL_1: - case TA_CNTL_AUX: - case DB_DEBUG: - case DB_DEBUG2: - case DB_DEBUG3: - case DB_DEBUG4: - case DB_WATERMARKS: - case TD_PS_BORDER_COLOR_INDEX: - case TD_PS_BORDER_COLOR_RED: - case TD_PS_BORDER_COLOR_GREEN: - case TD_PS_BORDER_COLOR_BLUE: - case TD_PS_BORDER_COLOR_ALPHA: - case TD_VS_BORDER_COLOR_INDEX: - case TD_VS_BORDER_COLOR_RED: - case TD_VS_BORDER_COLOR_GREEN: - case TD_VS_BORDER_COLOR_BLUE: - case TD_VS_BORDER_COLOR_ALPHA: - case TD_GS_BORDER_COLOR_INDEX: - case TD_GS_BORDER_COLOR_RED: - case TD_GS_BORDER_COLOR_GREEN: - case TD_GS_BORDER_COLOR_BLUE: - case TD_GS_BORDER_COLOR_ALPHA: - case TD_HS_BORDER_COLOR_INDEX: - case TD_HS_BORDER_COLOR_RED: - case TD_HS_BORDER_COLOR_GREEN: - case TD_HS_BORDER_COLOR_BLUE: - case TD_HS_BORDER_COLOR_ALPHA: - case TD_LS_BORDER_COLOR_INDEX: - case TD_LS_BORDER_COLOR_RED: - case TD_LS_BORDER_COLOR_GREEN: - case TD_LS_BORDER_COLOR_BLUE: - case TD_LS_BORDER_COLOR_ALPHA: - case TD_CS_BORDER_COLOR_INDEX: - case TD_CS_BORDER_COLOR_RED: - case TD_CS_BORDER_COLOR_GREEN: - case TD_CS_BORDER_COLOR_BLUE: - case TD_CS_BORDER_COLOR_ALPHA: - case SQ_ESGS_RING_SIZE: - case SQ_GSVS_RING_SIZE: - case SQ_ESTMP_RING_SIZE: - case SQ_GSTMP_RING_SIZE: - case SQ_HSTMP_RING_SIZE: - case SQ_LSTMP_RING_SIZE: - case SQ_PSTMP_RING_SIZE: - case SQ_VSTMP_RING_SIZE: - case SQ_ESGS_RING_ITEMSIZE: - case SQ_ESTMP_RING_ITEMSIZE: - case SQ_GSTMP_RING_ITEMSIZE: - case SQ_GSVS_RING_ITEMSIZE: - case SQ_GS_VERT_ITEMSIZE: - case SQ_GS_VERT_ITEMSIZE_1: - case SQ_GS_VERT_ITEMSIZE_2: - case SQ_GS_VERT_ITEMSIZE_3: - case SQ_GSVS_RING_OFFSET_1: - case SQ_GSVS_RING_OFFSET_2: - case SQ_GSVS_RING_OFFSET_3: - case SQ_HSTMP_RING_ITEMSIZE: - case SQ_LSTMP_RING_ITEMSIZE: - case SQ_PSTMP_RING_ITEMSIZE: - case SQ_VSTMP_RING_ITEMSIZE: - case VGT_TF_RING_SIZE: - case SQ_ESGS_RING_BASE: - case SQ_GSVS_RING_BASE: - case SQ_ESTMP_RING_BASE: - case SQ_GSTMP_RING_BASE: - case SQ_HSTMP_RING_BASE: - case SQ_LSTMP_RING_BASE: - case SQ_PSTMP_RING_BASE: - case SQ_VSTMP_RING_BASE: - case CAYMAN_VGT_OFFCHIP_LDS_BASE: - case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS: - return true; - default: - return false; - } -} - -static int evergreen_vm_packet3_check(struct radeon_device *rdev, - u32 *ib, struct radeon_cs_packet *pkt) -{ - u32 idx = pkt->idx + 1; - u32 idx_value = ib[idx]; - u32 start_reg, end_reg, reg, i; - - switch (pkt->opcode) { - case PACKET3_NOP: - case PACKET3_SET_BASE: - case PACKET3_CLEAR_STATE: - case PACKET3_INDEX_BUFFER_SIZE: - case PACKET3_DISPATCH_DIRECT: - case PACKET3_DISPATCH_INDIRECT: - case PACKET3_MODE_CONTROL: - case PACKET3_SET_PREDICATION: - case PACKET3_COND_EXEC: - case PACKET3_PRED_EXEC: - case PACKET3_DRAW_INDIRECT: - case PACKET3_DRAW_INDEX_INDIRECT: - case PACKET3_INDEX_BASE: - case PACKET3_DRAW_INDEX_2: - case PACKET3_CONTEXT_CONTROL: - case PACKET3_DRAW_INDEX_OFFSET: - case PACKET3_INDEX_TYPE: - case PACKET3_DRAW_INDEX: - case PACKET3_DRAW_INDEX_AUTO: - case PACKET3_DRAW_INDEX_IMMD: - case PACKET3_NUM_INSTANCES: - case PACKET3_DRAW_INDEX_MULTI_AUTO: - case PACKET3_STRMOUT_BUFFER_UPDATE: - case PACKET3_DRAW_INDEX_OFFSET_2: - case PACKET3_DRAW_INDEX_MULTI_ELEMENT: - case PACKET3_MPEG_INDEX: - case PACKET3_WAIT_REG_MEM: - case PACKET3_MEM_WRITE: - case PACKET3_SURFACE_SYNC: - case PACKET3_EVENT_WRITE: - case PACKET3_EVENT_WRITE_EOP: - case PACKET3_EVENT_WRITE_EOS: - case PACKET3_SET_CONTEXT_REG: - case PACKET3_SET_BOOL_CONST: - case PACKET3_SET_LOOP_CONST: - case PACKET3_SET_RESOURCE: - case PACKET3_SET_SAMPLER: - case PACKET3_SET_CTL_CONST: - case PACKET3_SET_RESOURCE_OFFSET: - case PACKET3_SET_CONTEXT_REG_INDIRECT: - case PACKET3_SET_RESOURCE_INDIRECT: - case CAYMAN_PACKET3_DEALLOC_STATE: - break; - case PACKET3_COND_WRITE: - if (idx_value & 0x100) { - reg = ib[idx + 5] * 4; - if (!evergreen_vm_reg_valid(reg)) - return -EINVAL; - } - break; - case PACKET3_COPY_DW: - if (idx_value & 0x2) { - reg = ib[idx + 3] * 4; - if (!evergreen_vm_reg_valid(reg)) - return -EINVAL; - } - break; - case PACKET3_SET_CONFIG_REG: - start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; - end_reg = 4 * pkt->count + start_reg - 4; - if ((start_reg < PACKET3_SET_CONFIG_REG_START) || - (start_reg >= PACKET3_SET_CONFIG_REG_END) || - (end_reg >= PACKET3_SET_CONFIG_REG_END)) { - DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); - return -EINVAL; - } - for (i = 0; i < pkt->count; i++) { - reg = start_reg + (4 * i); - if (!evergreen_vm_reg_valid(reg)) - return -EINVAL; - } - break; - default: - return -EINVAL; - } - return 0; -} - -int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) -{ - int ret = 0; - u32 idx = 0; - struct radeon_cs_packet pkt; - - do { - pkt.idx = idx; - pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]); - pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]); - pkt.one_reg_wr = 0; - switch (pkt.type) { - case PACKET_TYPE0: - dev_err(rdev->dev, "Packet0 not allowed!\n"); - ret = -EINVAL; - break; - case PACKET_TYPE2: - idx += 1; - break; - case PACKET_TYPE3: - pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]); - ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt); - idx += pkt.count + 2; - break; - default: - dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); - ret = -EINVAL; - break; - } - if (ret) - break; - } while (idx < ib->length_dw); - - return ret; -} |