diff options
Diffstat (limited to 'drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c')
| -rw-r--r-- | drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c | 54 |
1 files changed, 21 insertions, 33 deletions
diff --git a/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c b/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c index 8fc26cd..a08bc97 100644 --- a/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c +++ b/drivers/media/video/samsung/mali/platform/pegasus-m400/mali_platform.c @@ -33,7 +33,8 @@ #if MALI_INTERNAL_TIMELINE_PROFILING_ENABLED #include "mali_osk_profiling.h" -#include "cinstr/mali_cinstr_profiling_events_m200.h" +unsigned long gFreq = 366; +int gVolt = 5000; #endif #include <asm/io.h> @@ -58,7 +59,7 @@ typedef struct mali_runtime_resumeTag{ int vol; }mali_runtime_resume_table; -mali_runtime_resume_table mali_runtime_resume = {350, 950000}; +mali_runtime_resume_table mali_runtime_resume = {266, 900000}; /* lock/unlock CPU freq by Mali */ extern int cpufreq_lock_by_mali(unsigned int freq); @@ -84,11 +85,11 @@ static struct clk *mali_clock = 0; static unsigned int GPU_MHZ = 1000000; -int mali_gpu_clk = 350; -int mali_gpu_vol = 950000; +int mali_gpu_clk = 266; +int mali_gpu_vol = 900000; #if MALI_DVFS_ENABLED -#define MALI_DVFS_DEFAULT_STEP 2 +#define MALI_DVFS_DEFAULT_STEP 1 #endif #if MALI_VOLTAGE_LOCK int mali_lock_vol = 0; @@ -204,21 +205,15 @@ void mali_regulator_set_voltage(int min_uV, int max_uV) MALI_DEBUG_PRINT(2, ("= regulator_set_voltage: %d, %d \n",min_uV, max_uV)); -#if MALI_INTERNAL_TIMELINE_PROFILING_ENABLED - _mali_osk_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE | - MALI_PROFILING_EVENT_CHANNEL_SOFTWARE | - MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_VOLTS, - min_uV, max_uV, 1, 0, 0); -#endif - regulator_set_voltage(g3d_regulator,min_uV,max_uV); voltage = regulator_get_voltage(g3d_regulator); #if MALI_INTERNAL_TIMELINE_PROFILING_ENABLED - _mali_osk_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE | - MALI_PROFILING_EVENT_CHANNEL_SOFTWARE | - MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_VOLTS, - voltage, 0, 2, 0, 0); + gVolt = voltage/1000; + _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | + MALI_PROFILING_EVENT_CHANNEL_GPU | + MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, gFreq, gVolt, + 0, 0, 0); #endif mali_gpu_vol = voltage; @@ -379,7 +374,7 @@ mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz) #if !MALI_DVFS_ENABLED clk = mali_gpu_clk; #endif - + trace_printk("SPI_GPUFREQ_%uMHz\n", mali_gpu_clk); _mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW); if (mali_clk_get(bis_vpll) == MALI_FALSE) @@ -406,23 +401,16 @@ mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz) if (clk_enable(mali_clock) < 0) return MALI_FALSE; -#if MALI_INTERNAL_TIMELINE_PROFILING_ENABLED - unsigned long previous_rate = 0; - previous_rate = clk_get_rate(mali_clock); - _mali_osk_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE | - MALI_PROFILING_EVENT_CHANNEL_SOFTWARE | - MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ, - previous_rate, 0, 0, 0, 0); -#endif clk_set_rate(mali_clock, rate); rate = clk_get_rate(mali_clock); #if MALI_INTERNAL_TIMELINE_PROFILING_ENABLED - _mali_osk_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE | - MALI_PROFILING_EVENT_CHANNEL_SOFTWARE | - MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ, - rate, 1, 0, 0, 0); + gFreq = rate/1000000; + _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | + MALI_PROFILING_EVENT_CHANNEL_GPU | + MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, + gFreq, gVolt, 0, 0, 0); #endif if (bis_vpll) @@ -539,7 +527,7 @@ static _mali_osk_errcode_t enable_mali_clocks(void) } #if CPUFREQ_LOCK_DURING_440 /* lock/unlock CPU freq by Mali */ - if (mali_gpu_clk == 440) + if (mali_gpu_clk >= 440) err = cpufreq_lock_by_mali(1200); #endif #else @@ -557,7 +545,7 @@ static _mali_osk_errcode_t disable_mali_clocks(void) clk_disable(mali_clock); MALI_DEBUG_PRINT(3,("disable_mali_clocks mali_clock %p \n", mali_clock)); -#if MALI_DVFS_ENABLED +#if MALI_DVFS_ENABLED && CPUFREQ_LOCK_DURING_440 /* lock/unlock CPU freq by Mali */ cpufreq_unlock_by_mali(); #endif @@ -598,7 +586,6 @@ _mali_osk_errcode_t g3d_power_domain_control(int bpower_on) timeout--; _mali_osk_time_ubusydelay(100); } - MALI_PRINTF(("MALI Power domain enabled")); #endif //MALI_PMM_RUNTIME_JOB_CONTROL_ON } else @@ -623,7 +610,6 @@ _mali_osk_errcode_t g3d_power_domain_control(int bpower_on) timeout--; _mali_osk_time_ubusydelay( 100); } - MALI_PRINTF(("MALI Power domain disabled")); #endif //MALI_PMM_RUNTIME_JOB_CONTROL_ON } @@ -665,6 +651,7 @@ _mali_osk_errcode_t mali_platform_deinit() _mali_osk_errcode_t mali_platform_powerdown(u32 cores) { + trace_printk("SPI_GPU_PWR Idle\n"); MALI_DEBUG_PRINT(3,("power down is called in mali_platform_powerdown state %x core %x \n", gpu_power_state, cores)); if (gpu_power_state != 0) // power down after state is 0 @@ -686,6 +673,7 @@ _mali_osk_errcode_t mali_platform_powerdown(u32 cores) _mali_osk_errcode_t mali_platform_powerup(u32 cores) { + trace_printk("SPI_GPU_PWR Start\n"); MALI_DEBUG_PRINT(3,("power up is called in mali_platform_powerup state %x core %x \n", gpu_power_state, cores)); if (gpu_power_state == 0) // power up only before state is 0 |