1 files changed, 21 insertions, 11 deletions

diff --git a/drivers/media/video/samsung/mfc5x/mfc_enc.c b/drivers/media/video/samsung/mfc5x/mfc_enc.c
index 65d7b6b..f2dc039 100644
--- a/drivers/media/video/samsung/mfc5x/mfc_enc.c
+++ b/drivers/media/video/samsung/mfc5x/mfc_enc.c
@@ -55,10 +55,6 @@ static LIST_HEAD(mfc_encoders);
 	ctx->ctxbufofs = mfc_mem_base_ofs(alloc->real) >> 11;
 	ctx->ctxbufsize = alloc->size;
 
-	memset((void *)alloc->addr, 0, alloc->size);
-
-	mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
-
 	return 0;
 }
 
@@ -101,7 +97,7 @@ int get_init_arg(struct mfc_inst_ctx *ctx, void *arg)
 		write_reg((1 << 1) | 0x1, MFC_ENC_MSLICE_CTRL);
 		if (init_arg->cmn.in_ms_arg < 1900)
 			init_arg->cmn.in_ms_arg = 1900;
-		write_reg(init_arg->cmn.in_ms_arg, MFC_ENC_MSLICE_BIT);
+		write_reg(init_arg->cmn.in_ms_arg * 8, MFC_ENC_MSLICE_BIT);
 	} else {
 		write_reg(0, MFC_ENC_MSLICE_CTRL);
 		write_reg(0, MFC_ENC_MSLICE_MB);
@@ -586,8 +582,7 @@ static int h264_pre_seq_start(struct mfc_inst_ctx *ctx)
 
 	if (h264->sps_pps_gen == 1) {
 		write_shm(ctx,
-			((h264->sps_pps_gen << 8) |
-				read_shm(ctx, EXT_ENC_CONTROL)),
+			((h264->sps_pps_gen << 8) | read_shm(ctx, EXT_ENC_CONTROL)),
 			EXT_ENC_CONTROL);
 	}
 
@@ -1066,10 +1061,8 @@ static int h264_set_codec_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
 	case MFC_ENC_SETCONF_SPS_PPS_GEN:
 		mfc_dbg("MFC_ENC_SETCONF_SPS_PPS_GEN : %d\n", ctx->state);
 
-		if ((ctx->state < INST_STATE_CREATE) ||
-					(ctx->state > INST_STATE_EXE)) {
-			mfc_err("MFC_ENC_SETCONF_SPS_PPS_GEN : "
-						" state is invalid\n");
+		if ((ctx->state < INST_STATE_CREATE) || (ctx->state > INST_STATE_EXE)) {
+			mfc_err("MFC_ENC_SETCONF_SPS_PPS_GEN : state is invalid\n");
 			return MFC_STATE_INVALID;
 		}
 
@@ -1079,6 +1072,7 @@ static int h264_set_codec_cfg(struct mfc_inst_ctx *ctx, int type, void *arg)
 			h264->sps_pps_gen = 0;
 
 		break;
+
 	default:
 		mfc_dbg("invalid set cfg type: 0x%08x\n", type);
 		ret = -2;
@@ -1548,6 +1542,22 @@ int mfc_init_encoding(struct mfc_inst_ctx *ctx, union mfc_args *args)
 	}
 #endif
 
+#if defined(CONFIG_MACH_GC1) && defined(CONFIG_EXYNOS4_CPUFREQ)
+	if ((ctx->width >= 1280 && ctx->height >= 720)
+		|| (ctx->width >= 720 && ctx->height >= 1280)) {
+		if (atomic_read(&ctx->dev->cpufreq_lock_cnt) == 0) {
+			if (0 == ctx->dev->cpufreq_level) /* 800MHz */
+				exynos_cpufreq_get_level(800000,
+						&ctx->dev->cpufreq_level);
+			exynos_cpufreq_lock(DVFS_LOCK_ID_MFC,
+					ctx->dev->cpufreq_level);
+			mfc_dbg("[%s] CPU Freq Locked 800MHz!\n", __func__);
+		}
+		atomic_inc(&ctx->dev->cpufreq_lock_cnt);
+		ctx->cpufreq_flag = true;
+	}
+#endif
+
 #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_EXYNOS4_CPUFREQ)
 	if ((ctx->width >= 320 && ctx->height >= 240)
 		|| (ctx->width >= 240 && ctx->height >= 320)) {