diff options
Diffstat (limited to 'drivers/net/wireless/bcmdhd/include/hndsoc.h')
| -rw-r--r-- | drivers/net/wireless/bcmdhd/include/hndsoc.h | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/net/wireless/bcmdhd/include/hndsoc.h b/drivers/net/wireless/bcmdhd/include/hndsoc.h index f5c161b..7726a8a 100644 --- a/drivers/net/wireless/bcmdhd/include/hndsoc.h +++ b/drivers/net/wireless/bcmdhd/include/hndsoc.h @@ -1,7 +1,7 @@ /* * Broadcom HND chip & on-chip-interconnect-related definitions. * - * Copyright (C) 1999-2012, Broadcom Corporation + * Copyright (C) 1999-2014, Broadcom Corporation * * Unless you and Broadcom execute a separate written software license * agreement governing use of this software, this software is licensed to you @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: hndsoc.h 365041 2012-10-26 09:10:35Z $ + * $Id: hndsoc.h 432420 2013-10-28 14:14:02Z $ */ #ifndef _HNDSOC_H @@ -47,7 +47,9 @@ #define SI_WRAP_BASE 0x18100000 /* Wrapper space base */ #define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ +#ifndef SI_MAXCORES #define SI_MAXCORES 32 /* NorthStar has more cores */ +#endif /* SI_MAXCORES */ #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */ #define SI_FASTRAM_SWAPPED 0x19800000 @@ -80,7 +82,6 @@ #define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 * (2 ZettaBytes), high 32 bits */ - /* core codes */ #define NODEV_CORE_ID 0x700 /* Invalid coreid */ #define CC_CORE_ID 0x800 /* chipcommon core */ @@ -143,6 +144,7 @@ #define PCIE2_CORE_ID 0x83c /* pci express Gen2 core */ #define USB30D_CORE_ID 0x83d /* usb 3.0 device core */ #define ARMCR4_CORE_ID 0x83e /* ARM CR4 CPU */ +#define GCI_CORE_ID 0x840 /* GCI Core */ #define APB_BRIDGE_CORE_ID 0x135 /* APB bridge core ID */ #define AXI_CORE_ID 0x301 /* AXI/GPV core ID */ #define EROM_CORE_ID 0x366 /* EROM core ID */ @@ -186,7 +188,6 @@ * and chipcommon being the first core: */ #define SI_CC_IDX 0 - /* SOC Interconnect types (aka chip types) */ #define SOCI_SB 0 #define SOCI_AI 1 @@ -219,6 +220,7 @@ * communicate w/PMU regarding clock control. */ #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */ +#define SI_PWR_CTL_ST 0x1e8 /* For memory clock gating */ /* clk_ctl_st register */ #define CCS_FORCEALP 0x00000001 /* force ALP request */ @@ -229,12 +231,15 @@ #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ #define CCS_HQCLKREQ 0x00000040 /* HQ Clock Required */ #define CCS_USBCLKREQ 0x00000100 /* USB Clock Req */ +#define CCS_SECICLKREQ 0x00000100 /* SECI Clock Req */ +#define CCS_ARMFASTCLOCKREQ 0x00000100 /* ARM CR4 fast clock request */ #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */ #define CCS_ERSRC_REQ_SHIFT 8 #define CCS_ALPAVAIL 0x00010000 /* ALP is available */ #define CCS_HTAVAIL 0x00020000 /* HT is available */ #define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */ #define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */ +#define CCS_ARMFASTCLOCKSTATUS 0x01000000 /* Fast CPU clock is running */ #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */ #define CCS_ERSRC_STS_SHIFT 24 |