diff options
Diffstat (limited to 'drivers/net/wireless/bcmdhd/include')
38 files changed, 2283 insertions, 755 deletions
diff --git a/drivers/net/wireless/bcmdhd/include/Makefile b/drivers/net/wireless/bcmdhd/include/Makefile index eca939f..bcc12677 100755..100644 --- a/drivers/net/wireless/bcmdhd/include/Makefile +++ b/drivers/net/wireless/bcmdhd/include/Makefile @@ -10,10 +10,10 @@ # # Copyright 2005, Broadcom, Inc. # -# $Id: Makefile 241686 2011-02-19 00:22:45Z prakashd $ +# $Id: Makefile 347587 2012-07-27 09:13:31Z prakashd $ # -SRCBASE := .. +export SRCBASE:=.. TARGETS := epivers.h @@ -23,11 +23,11 @@ endif all release: epivers compvers -# Generate epivers.h for native branch version +# Generate epivers.h for native branch url epivers: bash epivers.sh -# Generate epivers.h for native branch version +# Generate component versions based on component url compvers: @if [ -s "compvers.sh" ]; then \ echo "Generating component versions, if any"; \ diff --git a/drivers/net/wireless/bcmdhd/include/bcmdefs.h b/drivers/net/wireless/bcmdhd/include/bcmdefs.h index a35ed72..0462f81 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmdefs.h +++ b/drivers/net/wireless/bcmdhd/include/bcmdefs.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: bcmdefs.h 316830 2012-02-23 20:29:22Z $ + * $Id: bcmdefs.h 366265 2012-11-01 20:08:27Z $ */ #ifndef _bcmdefs_h_ @@ -54,8 +54,13 @@ #define BCMNMIATTACHDATA(_data) _data #define CONST const #ifndef BCMFASTPATH +#if defined(__ARM_ARCH_7A__) +#define BCMFASTPATH __attribute__ ((__section__ (".text.fastpath"))) +#define BCMFASTPATH_HOST __attribute__ ((__section__ (".text.fastpath_host"))) +#else #define BCMFASTPATH #define BCMFASTPATH_HOST +#endif #endif @@ -177,9 +182,9 @@ typedef struct { #if defined(BCM_RPC_NOCOPY) || defined(BCM_RCP_TXNOCOPY) -#define BCMEXTRAHDROOM 220 +#define BCMEXTRAHDROOM 260 #else -#define BCMEXTRAHDROOM 172 +#define BCMEXTRAHDROOM 204 #endif diff --git a/drivers/net/wireless/bcmdhd/include/bcmdevs.h b/drivers/net/wireless/bcmdhd/include/bcmdevs.h index c7e06ff..50e693a 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmdevs.h +++ b/drivers/net/wireless/bcmdhd/include/bcmdevs.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: bcmdevs.h 329854 2012-04-27 01:42:28Z $ + * $Id: bcmdevs.h 368924 2012-11-15 08:12:59Z $ */ #ifndef _BCMDEVS_H @@ -63,6 +63,12 @@ #define BCM_DNGL_BL_PID_43239 0xbd1b #define BCM_DNGL_BL_PID_4324 0xbd1c #define BCM_DNGL_BL_PID_4360 0xbd1d +#define BCM_DNGL_BL_PID_43143 0xbd1e +#define BCM_DNGL_BL_PID_43242 0xbd1f +#define BCM_DNGL_BL_PID_43342 0xbd21 +#define BCM_DNGL_BL_PID_4335 0xbd20 +#define BCM_DNGL_BL_PID_4350 0xbd23 +#define BCM_DNGL_BL_PID_43341 0xbd22 #define BCM_DNGL_BDC_PID 0x0bdc #define BCM_DNGL_JTAG_PID 0x4a44 @@ -146,28 +152,42 @@ #define BCM43131_D11N2G_ID 0x43aa #define BCM4314_D11N2G_ID 0x4364 #define BCM43142_D11N2G_ID 0x4365 +#define BCM43143_D11N2G_ID 0x4366 #define BCM4334_D11N_ID 0x4380 #define BCM4334_D11N2G_ID 0x4381 #define BCM4334_D11N5G_ID 0x4382 +#define BCM43342_D11N_ID 0x4383 +#define BCM43342_D11N2G_ID 0x4384 +#define BCM43342_D11N5G_ID 0x4385 #define BCM43341_D11N_ID 0x4386 #define BCM43341_D11N2G_ID 0x4387 #define BCM43341_D11N5G_ID 0x4388 #define BCM4360_D11AC_ID 0x43a0 #define BCM4360_D11AC2G_ID 0x43a1 #define BCM4360_D11AC5G_ID 0x43a2 +#define BCM4335_D11AC_ID 0x43ae +#define BCM4335_D11AC2G_ID 0x43af +#define BCM4335_D11AC5G_ID 0x43b0 +#define BCM4352_D11AC_ID 0x43b1 +#define BCM4352_D11AC2G_ID 0x43b2 +#define BCM4352_D11AC5G_ID 0x43b3 #define BCM943228HMB_SSID_VEN1 0x0607 #define BCM94313HMGBL_SSID_VEN1 0x0608 #define BCM94313HMG_SSID_VEN1 0x0609 +#define BCM943142HM_SSID_VEN1 0x0611 +#define BCM43143_D11N2G_ID 0x4366 + +#define BCM43242_D11N_ID 0x4367 +#define BCM43242_D11N2G_ID 0x4368 +#define BCM43242_D11N5G_ID 0x4369 + +#define BCM4350_D11AC_ID 0x43a3 +#define BCM4350_D11AC2G_ID 0x43a4 +#define BCM4350_D11AC5G_ID 0x43a5 -#define BCM4335_D11AC_ID 0x43ae -#define BCM4335_D11AC2G_ID 0x43af -#define BCM4335_D11AC5G_ID 0x43b0 -#define BCM4352_D11AC_ID 0x43b1 -#define BCM4352_D11AC2G_ID 0x43b2 -#define BCM4352_D11AC5G_ID 0x43b3 #define BCMGPRS_UART_ID 0x4333 #define BCMGPRS2_UART_ID 0x4344 @@ -205,6 +225,8 @@ #define BCM47XX_GIGETH_ID 0x471f #define BCM4712_MIPS_ID 0x4720 #define BCM4716_DEVICE_ID 0x4722 +#define BCM47XX_USB30H_ID 0x472a +#define BCM47XX_USB30D_ID 0x472b #define BCM47XX_SMBUS_EMU_ID 0x47fe #define BCM47XX_XOR_EMU_ID 0x47ff #define EPI41210_DEVICE_ID 0xa0fa @@ -260,21 +282,27 @@ #define BCM6362_CHIP_ID 0x6362 #define BCM4314_CHIP_ID 0x4314 #define BCM43142_CHIP_ID 43142 +#define BCM43143_CHIP_ID 43143 #define BCM4324_CHIP_ID 0x4324 #define BCM43242_CHIP_ID 43242 +#define BCM43243_CHIP_ID 43243 #define BCM4334_CHIP_ID 0x4334 +#define BCM4335_CHIP_ID 0x4335 #define BCM4360_CHIP_ID 0x4360 #define BCM4352_CHIP_ID 0x4352 #define BCM43526_CHIP_ID 0xAA06 #define BCM43341_CHIP_ID 43341 #define BCM43342_CHIP_ID 43342 - #define BCM4335_CHIP_ID 0x4335 +#define BCM4350_CHIP_ID 0x4350 #define BCM4342_CHIP_ID 4342 #define BCM4402_CHIP_ID 0x4402 #define BCM4704_CHIP_ID 0x4704 #define BCM4706_CHIP_ID 0x5300 +#define BCM4707_CHIP_ID 53010 +#define BCM53018_CHIP_ID 53018 +#define BCM4707_CHIP(chipid) (((chipid) == BCM4707_CHIP_ID) || ((chipid) == BCM53018_CHIP_ID)) #define BCM4710_CHIP_ID 0x4710 #define BCM4712_CHIP_ID 0x4712 #define BCM4716_CHIP_ID 0x4716 @@ -336,27 +364,38 @@ #define BCM4314SDIO_FPBGA_PKG_ID (8 | 4) #define BCM4314DEV_PKG_ID (8 | 6) +#define BCM4707_PKG_ID 1 +#define BCM4708_PKG_ID 2 +#define BCM4709_PKG_ID 0 + #define PCIXX21_FLASHMEDIA0_ID 0x8033 #define PCIXX21_SDIOH0_ID 0x8034 +#define BCM4335_WLCSP_PKG_ID (0x0) +#define BCM4335_FCBGA_PKG_ID (0x1) +#define BCM4335_WLBGA_PKG_ID (0x2) +#define BCM4335_FCBGAD_PKG_ID (0x3) +#define BCM4335_PKG_MASK (0x3) + #define BFL_BTC2WIRE 0x00000001 #define BFL_BTCOEX 0x00000001 #define BFL_PACTRL 0x00000002 #define BFL_AIRLINEMODE 0x00000004 #define BFL_ADCDIV 0x00000008 -#define BFL_RFPLL 0x00000008 +#define BFL_DIS_256QAM 0x00000008 #define BFL_ENETROBO 0x00000010 #define BFL_NOPLLDOWN 0x00000020 #define BFL_CCKHIPWR 0x00000040 #define BFL_ENETADM 0x00000080 #define BFL_ENETVLAN 0x00000100 -#define BFL_UNUSED 0x00000200 +#define BFL_LTECOEX 0x00000200 #define BFL_NOPCI 0x00000400 #define BFL_FEM 0x00000800 #define BFL_EXTLNA 0x00001000 #define BFL_HGPA 0x00002000 -#define BFL_BTC2WIRE_ALTGPIO 0x00004000 +#define BFL_BTC2WIRE_ALTGPIO 0x00004000 + #define BFL_ALTIQ 0x00008000 #define BFL_NOPA 0x00010000 #define BFL_RSSIINV 0x00020000 @@ -365,6 +404,7 @@ #define BFL_PHASESHIFT 0x00100000 #define BFL_BUCKBOOST 0x00200000 #define BFL_FEM_BT 0x00400000 +#define BFL_RXCHAIN_OFF_BT 0x00400000 #define BFL_NOCBUCK 0x00800000 #define BFL_CCKFAVOREVM 0x01000000 #define BFL_PALDO 0x02000000 @@ -373,6 +413,7 @@ #define BFL_UCPWRCTL_MININDX 0x08000000 #define BFL_EXTLNA_5GHz 0x10000000 #define BFL_TRSW_1by2 0x20000000 +#define BFL_GAINBOOSTA01 0x20000000 #define BFL_LO_TRSW_R_5GHz 0x40000000 #define BFL_ELNA_GAINDEF 0x80000000 #define BFL_EXTLNA_TX 0x20000000 @@ -405,7 +446,8 @@ #define BFL2_ANAPACTRL_2G 0x00100000 #define BFL2_ANAPACTRL_5G 0x00200000 #define BFL2_ELNACTRL_TRSW_2G 0x00400000 -#define BFL2_BT_SHARE_ANT0 0x00800000 +#define BFL2_BT_SHARE_ANT0 0x00800000 +#define BFL2_BT_SHARE_BM_BIT0 0x00800000 #define BFL2_TEMPSENSE_HIGHER 0x01000000 #define BFL2_BTC3WIREONLY 0x02000000 #define BFL2_PWR_NOMINAL 0x04000000 @@ -413,7 +455,31 @@ #define BFL2_4313_RADIOREG 0x10000000 +#define BFL2_DYNAMIC_VMID 0x10000000 + #define BFL2_SDR_EN 0x20000000 +#define BFL2_DYNAMIC_VMID 0x10000000 +#define BFL2_BT_SHARE_BM_BIT1 0x40000000 + + +#define BFL_SROM11_BTCOEX 0x00000001 +#define BFL_SROM11_WLAN_BT_SH_XTL 0x00000002 +#define BFL_SROM11_EXTLNA 0x00001000 +#define BFL_SROM11_EXTLNA_5GHz 0x10000000 +#define BFL_SROM11_GAINBOOSTA01 0x20000000 +#define BFL2_SROM11_APLL_WAR 0x00000002 +#define BFL2_SROM11_ANAPACTRL_2G 0x00100000 +#define BFL2_SROM11_ANAPACTRL_5G 0x00200000 + + +#define BFL3_FEMCTRL_SUB 0x00000007 +#define BFL3_RCAL_WAR 0x00000008 +#define BFL3_TXGAINTBLID 0x00000070 +#define BFL3_TXGAINTBLID_SHIFT 0x4 +#define BFL3_TSSI_DIV_WAR 0x00000080 +#define BFL3_TSSI_DIV_WAR_SHIFT 0x7 +#define BFL3_FEMTBL_FROM_NVRAM 0x00000100 +#define BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8 #define BOARD_GPIO_BTC3W_IN 0x850 @@ -457,6 +523,9 @@ #define BCM943341WLABGS_SSID 0x062d +#define BCM943342FCAGBI_SSID 0x0641 + + #define GPIO_NUMPINS 32 @@ -470,6 +539,12 @@ #define RDL_RAM_BASE_4328 0x80000000 #define RDL_RAM_SIZE_4322 0x60000 #define RDL_RAM_BASE_4322 0x60000000 +#define RDL_RAM_SIZE_4360 0xA0000 +#define RDL_RAM_BASE_4360 0x60000000 +#define RDL_RAM_SIZE_43242 0x90000 +#define RDL_RAM_BASE_43242 0x60000000 +#define RDL_RAM_SIZE_43143 0x70000 +#define RDL_RAM_BASE_43143 0x60000000 #define MUXENAB_UART 0x00000001 diff --git a/drivers/net/wireless/bcmdhd/include/bcmnvram.h b/drivers/net/wireless/bcmdhd/include/bcmnvram.h index ce0e035..ba22bec 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmnvram.h +++ b/drivers/net/wireless/bcmdhd/include/bcmnvram.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: bcmnvram.h 320632 2012-03-12 19:22:42Z $ + * $Id: bcmnvram.h 364705 2012-10-25 00:42:42Z $ */ #ifndef _bcmnvram_h_ @@ -51,6 +51,7 @@ extern char *nvram_default_get(const char *name); extern int nvram_init(void *sih); +extern int nvram_deinit(void *sih); extern int nvram_append(void *si, char *vars, uint varsz); @@ -80,7 +81,7 @@ nvram_safe_get(const char *name) static INLINE int -nvram_match(char *name, char *match) +nvram_match(const char *name, const char *match) { const char *value = nvram_get(name); return (value && !strcmp(value, match)); @@ -88,7 +89,7 @@ nvram_match(char *name, char *match) static INLINE int -nvram_invmatch(char *name, char *invmatch) +nvram_invmatch(const char *name, const char *invmatch) { const char *value = nvram_get(name); return (value && strcmp(value, invmatch)); @@ -109,6 +110,8 @@ extern int nvram_getall(char *nvram_buf, int count); uint8 nvram_calc_crc(struct nvram_header * nvh); +extern int nvram_space; + #endif @@ -120,6 +123,13 @@ uint8 nvram_calc_crc(struct nvram_header * nvh); #define NVRAM_VERSION 1 #define NVRAM_HEADER_SIZE 20 #define NVRAM_SPACE 0x8000 +#define DEF_NVRAM_SPACE 0x8000 +#ifdef MAX_NVRAM_SPACE +#undef MAX_NVRAM_SPACE +#endif +#define MAX_NVRAM_SPACE NVRAM_SPACE +#define ROM_ENVRAM_SPACE 0x1000 +#define NVRAM_LZMA_MAGIC 0x4c5a4d41 #define NVRAM_MAX_VALUE_LEN 255 #define NVRAM_MAX_PARAM_LEN 64 diff --git a/drivers/net/wireless/bcmdhd/include/bcmsdbus.h b/drivers/net/wireless/bcmdhd/include/bcmsdbus.h index 29657d7..cbea8c5 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmsdbus.h +++ b/drivers/net/wireless/bcmdhd/include/bcmsdbus.h @@ -22,7 +22,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: bcmsdbus.h 347614 2012-07-27 10:24:51Z $ + * $Id: bcmsdbus.h 387188 2013-02-24 09:20:24Z $ */ #ifndef _sdio_api_h_ @@ -48,12 +48,27 @@ #ifdef BCMSDIOH_TXGLOM /* Max number of glommed pkts */ -#define SDPCM_MAXGLOM_SIZE 10 -#define SDPCM_DEFGLOM_SIZE 3 +#ifdef CUSTOM_MAX_TXGLOM_SIZE +#define SDPCM_MAXGLOM_SIZE CUSTOM_MAX_TXGLOM_SIZE +#else +#define SDPCM_MAXGLOM_SIZE 16 +#endif /* CUSTOM_MAX_TXGLOM_SIZE */ #define SDPCM_TXGLOM_CPY 0 /* SDIO 2.0 should use copy mode */ #define SDPCM_TXGLOM_MDESC 1 /* SDIO 3.0 should use multi-desc mode */ + +#ifdef BCMSDIOH_TXGLOM_HIGHSPEED +#define SDPCM_DEFGLOM_MODE SDPCM_TXGLOM_MDESC +#ifdef CUSTOM_TXGLOM_SIZE +#define SDPCM_DEFGLOM_SIZE CUSTOM_TXGLOM_SIZE +#else +#define SDPCM_DEFGLOM_SIZE 10 #endif +#else +#define SDPCM_DEFGLOM_MODE SDPCM_TXGLOM_CPY +#define SDPCM_DEFGLOM_SIZE 3 +#endif /* BCMSDIOH_TXGLOM_HIGHSPEED */ +#endif /* BCMSDIOH_TXGLOM */ typedef int SDIOH_API_RC; @@ -96,12 +111,12 @@ extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t *si, uint pio_dma, uint fi void *pkt); #ifdef BCMSDIOH_TXGLOM -extern void sdioh_glom_post(sdioh_info_t *sd, uint8 *frame, uint len); +extern void sdioh_glom_post(sdioh_info_t *sd, uint8 *frame, void *pkt, uint len); extern void sdioh_glom_clear(sdioh_info_t *sd); extern uint sdioh_set_mode(sdioh_info_t *sd, uint mode); extern bool sdioh_glom_enabled(void); #else -#define sdioh_glom_post(a, b, c) +#define sdioh_glom_post(a, b, c, d) #define sdioh_glom_clear(a) #define sdioh_set_mode(a) (0) #define sdioh_glom_enabled() (FALSE) diff --git a/drivers/net/wireless/bcmdhd/include/bcmsdh.h b/drivers/net/wireless/bcmdhd/include/bcmsdh.h index 3348e84..e882d5e 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmsdh.h +++ b/drivers/net/wireless/bcmdhd/include/bcmsdh.h @@ -23,7 +23,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: bcmsdh.h 347614 2012-07-27 10:24:51Z $ + * $Id: bcmsdh.h 365575 2012-10-30 05:25:07Z $ */ /** @@ -48,6 +48,8 @@ extern const uint bcmsdh_msglevel; typedef struct bcmsdh_info bcmsdh_info_t; typedef void (*bcmsdh_cb_fn_t)(void *); +extern struct device *pm_dev; + /* Attach and build an interface to the underlying SD host driver. * - Allocates resources (structs, arrays, mem, OS handles, etc) needed by bcmsdh. * - Returns the bcmsdh handle and virtual address base for register access. @@ -145,7 +147,7 @@ extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags, uint8 *buf, uint nbytes, void *pkt, bcmsdh_cmplt_fn_t complete_fn, void *handle); -extern void bcmsdh_glom_post(void *sdh, uint8 *frame, uint len); +extern void bcmsdh_glom_post(void *sdh, uint8 *frame, void *pkt, uint len); extern void bcmsdh_glom_clear(void *sdh); extern uint bcmsdh_set_mode(void *sdh, uint mode); extern bool bcmsdh_glom_enabled(void); diff --git a/drivers/net/wireless/bcmdhd/include/bcmsdh_sdmmc.h b/drivers/net/wireless/bcmdhd/include/bcmsdh_sdmmc.h index 25cd55b..bd85de3 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmsdh_sdmmc.h +++ b/drivers/net/wireless/bcmdhd/include/bcmsdh_sdmmc.h @@ -21,21 +21,19 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: bcmsdh_sdmmc.h 355594 2012-09-07 10:22:02Z $ + * $Id: bcmsdh_sdmmc.h 393684 2013-03-28 11:03:49Z $ */ #ifndef __BCMSDH_SDMMC_H__ #define __BCMSDH_SDMMC_H__ -#define sd_err(x) do {printf x;} while (0) +#define sd_err(x) #define sd_trace(x) #define sd_info(x) #define sd_debug(x) #define sd_data(x) #define sd_ctrl(x) -#define sd_trace_hw4 sd_trace - #define sd_sync_dma(sd, read, nbytes) #define sd_init_dma(sd) #define sd_ack_intr(sd) @@ -61,10 +59,21 @@ extern void sdioh_sdmmc_osfree(sdioh_info_t *sd); /* private bus modes */ #define SDIOH_MODE_SD4 2 -#define CLIENT_INTR 0x100 /* Get rid of this! */ +#define CLIENT_INTR 0x100 /* Get rid of this! */ + +#ifdef BCMSDIOH_TXGLOM +/* Setting the MAX limit to 10 */ +#define SDIOH_MAXGLOM_SIZE 16 + +typedef struct glom_buf { + void *glom_pkt_head; + void *glom_pkt_tail; + uint32 count; /* Total number of pkts queued */ +} glom_buf_t; +#endif struct sdioh_info { - osl_t *osh; /* osh handler */ + osl_t *osh; /* osh handler */ bool client_intr_enabled; /* interrupt connnected flag */ bool intr_handler_valid; /* client driver interrupt handler valid */ sdioh_cb_fn_t intr_handler; /* registered interrupt handler */ @@ -72,22 +81,27 @@ struct sdioh_info { uint16 intmask; /* Current active interrupts */ void *sdos_info; /* Pointer to per-OS private data */ - uint irq; /* Client irq */ - int intrcount; /* Client interrupts */ + uint irq; /* Client irq */ + int intrcount; /* Client interrupts */ bool sd_use_dma; /* DMA on CMD53 */ - bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */ + bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */ /* Must be on for sd_multiblock to be effective */ bool use_client_ints; /* If this is false, make sure to restore */ int sd_mode; /* SD1/SD4/SPI */ int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */ uint8 num_funcs; /* Supported funcs on client */ uint32 com_cis_ptr; - uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS]; + uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS]; #define SDIOH_SDMMC_MAX_SG_ENTRIES 32 struct scatterlist sg_list[SDIOH_SDMMC_MAX_SG_ENTRIES]; bool use_rxchain; + +#ifdef BCMSDIOH_TXGLOM + glom_buf_t glom_info; /* pkt information used for glomming */ + uint txglom_mode; /* Txglom mode: 0 - copy, 1 - multi-descriptor */ +#endif }; /************************************************************ diff --git a/drivers/net/wireless/bcmdhd/include/bcmsdpcm.h b/drivers/net/wireless/bcmdhd/include/bcmsdpcm.h index 80c0a3d..1fc37f9 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmsdpcm.h +++ b/drivers/net/wireless/bcmdhd/include/bcmsdpcm.h @@ -22,7 +22,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: bcmsdpcm.h 291086 2011-10-21 01:17:24Z $ + * $Id: bcmsdpcm.h 364353 2012-10-23 20:31:46Z $ */ #ifndef _bcmsdpcm_h_ @@ -146,16 +146,23 @@ #define SDPCM_GLOMDESC(p) (((uint8 *)p)[1] & 0x80) /* For TEST_CHANNEL packets, define another 4-byte header */ -#define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2); - * Semantics of Ext byte depend on command. - * Len is current or requested frame length, not - * including test header; sent little-endian. - */ -#define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */ -#define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */ -#define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */ -#define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count */ -#define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off */ +#define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2); + * Semantics of Ext byte depend on command. + * Len is current or requested frame length, not + * including test header; sent little-endian. + */ +#define SDPCM_TEST_PKT_CNT_FLD_LEN 4 /* Packet count filed legth */ +#define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */ +#define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */ +#define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */ +#define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count + * (Backward compatabilty) Set frame count in a + * 4 byte filed adjacent to the HDR + */ +#define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off + * Set frame count in a 4 byte filed adjacent to + * the HDR + */ /* Handy macro for filling in datagen packets with a pattern */ #define SDPCM_TEST_FILL(byteno, id) ((uint8)(id + byteno)) diff --git a/drivers/net/wireless/bcmdhd/include/bcmsdstd.h b/drivers/net/wireless/bcmdhd/include/bcmsdstd.h index 896686c..2b5adf1 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmsdstd.h +++ b/drivers/net/wireless/bcmdhd/include/bcmsdstd.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: bcmsdstd.h 347614 2012-07-27 10:24:51Z $ + * $Id: bcmsdstd.h 343301 2012-07-06 13:07:32Z $ */ #ifndef _BCM_SD_STD_H #define _BCM_SD_STD_H diff --git a/drivers/net/wireless/bcmdhd/include/bcmspibrcm.h b/drivers/net/wireless/bcmdhd/include/bcmspibrcm.h index d94e9e4..a3e9b49 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmspibrcm.h +++ b/drivers/net/wireless/bcmdhd/include/bcmspibrcm.h @@ -1,168 +1,168 @@ -/*
- * SD-SPI Protocol Conversion - BCMSDH->gSPI Translation Layer
- *
- * Copyright (C) 1999-2012, Broadcom Corporation
- *
- * Unless you and Broadcom execute a separate written software license
- * agreement governing use of this software, this software is licensed to you
- * under the terms of the GNU General Public License version 2 (the "GPL"),
- * available at http://www.broadcom.com/licenses/GPLv2.php, with the
- * following added to such license:
- *
- * As a special exception, the copyright holders of this software give you
- * permission to link this software with independent modules, and to copy and
- * distribute the resulting executable under terms of your choice, provided that
- * you also meet, for each linked independent module, the terms and conditions of
- * the license of that module. An independent module is a module which is not
- * derived from this software. The special exception does not apply to any
- * modifications of the software.
- *
- * Notwithstanding the above, under no circumstances may you combine this
- * software in any way with any other Broadcom software provided under a license
- * other than the GPL, without Broadcom's express prior written consent.
- *
- * $Id: bcmspibrcm.h 354176 2012-08-30 07:34:33Z $
- */
-#ifndef _BCM_SPI_BRCM_H
-#define _BCM_SPI_BRCM_H
-
-#ifndef SPI_MAX_IOFUNCS
-/* Maximum number of I/O funcs */
-#define SPI_MAX_IOFUNCS 4
-#endif
-/* global msglevel for debug messages - bitvals come from sdiovar.h */
-
-#if defined(DHD_DEBUG)
-#define sd_err(x) do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0)
-#define sd_trace(x) do { if (sd_msglevel & SDH_TRACE_VAL) printf x; } while (0)
-#define sd_info(x) do { if (sd_msglevel & SDH_INFO_VAL) printf x; } while (0)
-#define sd_debug(x) do { if (sd_msglevel & SDH_DEBUG_VAL) printf x; } while (0)
-#define sd_data(x) do { if (sd_msglevel & SDH_DATA_VAL) printf x; } while (0)
-#define sd_ctrl(x) do { if (sd_msglevel & SDH_CTRL_VAL) printf x; } while (0)
-#else
-#define sd_err(x)
-#define sd_trace(x)
-#define sd_info(x)
-#define sd_debug(x)
-#define sd_data(x)
-#define sd_ctrl(x)
-#endif
-
-#define sd_log(x)
-
-#define SDIOH_ASSERT(exp) \
- do { if (!(exp)) \
- printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
- } while (0)
-
-#define BLOCK_SIZE_F1 64
-#define BLOCK_SIZE_F2 2048
-#define BLOCK_SIZE_F3 2048
-
-/* internal return code */
-#define SUCCESS 0
-#undef ERROR
-#define ERROR 1
-#define ERROR_UF 2
-#define ERROR_OF 3
-
-/* private bus modes */
-#define SDIOH_MODE_SPI 0
-
-#define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */
-#define USE_MULTIBLOCK 0x4
-
-struct sdioh_info {
- uint cfg_bar; /* pci cfg address for bar */
- uint32 caps; /* cached value of capabilities reg */
-#ifndef BCMSPI_ANDROID
- void *bar0; /* BAR0 for PCI Device */
-#endif /* !BCMSPI_ANDROID */
- osl_t *osh; /* osh handler */
- void *controller; /* Pointer to SPI Controller's private data struct */
-#ifndef BCMSPI_ANDROID
- uint lockcount; /* nest count of spi_lock() calls */
- bool client_intr_enabled; /* interrupt connnected flag */
- bool intr_handler_valid; /* client driver interrupt handler valid */
- sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
- void *intr_handler_arg; /* argument to call interrupt handler */
-#endif /* !BCMSPI_ANDROID */
- bool initialized; /* card initialized */
- uint32 target_dev; /* Target device ID */
- uint32 intmask; /* Current active interrupts */
-#ifndef BCMSPI_ANDROID
- void *sdos_info; /* Pointer to per-OS private data */
-#endif /* !BCMSPI_ANDROID */
- uint32 controller_type; /* Host controller type */
- uint8 version; /* Host Controller Spec Compliance Version */
- uint irq; /* Client irq */
- uint32 intrcount; /* Client interrupts */
- uint32 local_intrcount; /* Controller interrupts */
- bool host_init_done; /* Controller initted */
- bool card_init_done; /* Client SDIO interface initted */
- bool polled_mode; /* polling for command completion */
-
- bool sd_use_dma; /* DMA on CMD53 */
- bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
- /* Must be on for sd_multiblock to be effective */
- bool use_client_ints; /* If this is false, make sure to restore */
- /* polling hack in wl_linux.c:wl_timer() */
- int adapter_slot; /* Maybe dealing with multiple slots/controllers */
- int sd_mode; /* SD1/SD4/SPI */
- int client_block_size[SPI_MAX_IOFUNCS]; /* Blocksize */
- uint32 data_xfer_count; /* Current transfer */
- uint16 card_rca; /* Current Address */
- uint8 num_funcs; /* Supported funcs on client */
- uint32 card_dstatus; /* 32bit device status */
- uint32 com_cis_ptr;
- uint32 func_cis_ptr[SPI_MAX_IOFUNCS];
- void *dma_buf;
- ulong dma_phys;
- int r_cnt; /* rx count */
- int t_cnt; /* tx_count */
- uint32 wordlen; /* host processor 16/32bits */
- uint32 prev_fun;
- uint32 chip;
- uint32 chiprev;
- bool resp_delay_all;
- bool dwordmode;
- bool resp_delay_new;
-
- struct spierrstats_t spierrstats;
-};
-
-/************************************************************
- * Internal interfaces: per-port references into bcmspibrcm.c
- */
-
-/* Global message bits */
-extern uint sd_msglevel;
-
-/**************************************************************
- * Internal interfaces: bcmspibrcm.c references to per-port code
- */
-
-/* Interrupt (de)registration routines */
-extern int spi_register_irq(sdioh_info_t *sd, uint irq);
-extern void spi_free_irq(uint irq, sdioh_info_t *sd);
-
-/* OS-specific interrupt wrappers (atomic interrupt enable/disable) */
-extern void spi_lock(sdioh_info_t *sd);
-extern void spi_unlock(sdioh_info_t *sd);
-
-/* Allocate/init/free per-OS private data */
-extern int spi_osinit(sdioh_info_t *sd);
-extern void spi_osfree(sdioh_info_t *sd);
-
-#define SPI_RW_FLAG_M BITFIELD_MASK(1) /* Bit [31] - R/W Command Bit */
-#define SPI_RW_FLAG_S 31
-#define SPI_ACCESS_M BITFIELD_MASK(1) /* Bit [30] - Fixed/Incr Access */
-#define SPI_ACCESS_S 30
-#define SPI_FUNCTION_M BITFIELD_MASK(2) /* Bit [29:28] - Function Number */
-#define SPI_FUNCTION_S 28
-#define SPI_REG_ADDR_M BITFIELD_MASK(17) /* Bit [27:11] - Address */
-#define SPI_REG_ADDR_S 11
-#define SPI_LEN_M BITFIELD_MASK(11) /* Bit [10:0] - Packet length */
-#define SPI_LEN_S 0
-
-#endif /* _BCM_SPI_BRCM_H */
+/* + * SD-SPI Protocol Conversion - BCMSDH->gSPI Translation Layer + * + * Copyright (C) 1999-2012, Broadcom Corporation + * + * Unless you and Broadcom execute a separate written software license + * agreement governing use of this software, this software is licensed to you + * under the terms of the GNU General Public License version 2 (the "GPL"), + * available at http://www.broadcom.com/licenses/GPLv2.php, with the + * following added to such license: + * + * As a special exception, the copyright holders of this software give you + * permission to link this software with independent modules, and to copy and + * distribute the resulting executable under terms of your choice, provided that + * you also meet, for each linked independent module, the terms and conditions of + * the license of that module. An independent module is a module which is not + * derived from this software. The special exception does not apply to any + * modifications of the software. + * + * Notwithstanding the above, under no circumstances may you combine this + * software in any way with any other Broadcom software provided under a license + * other than the GPL, without Broadcom's express prior written consent. + * + * $Id: bcmspibrcm.h 358377 2012-09-23 11:30:22Z $ + */ +#ifndef _BCM_SPI_BRCM_H +#define _BCM_SPI_BRCM_H + +#ifndef SPI_MAX_IOFUNCS +/* Maximum number of I/O funcs */ +#define SPI_MAX_IOFUNCS 4 +#endif +/* global msglevel for debug messages - bitvals come from sdiovar.h */ + +#if defined(DHD_DEBUG) +#define sd_err(x) do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0) +#define sd_trace(x) do { if (sd_msglevel & SDH_TRACE_VAL) printf x; } while (0) +#define sd_info(x) do { if (sd_msglevel & SDH_INFO_VAL) printf x; } while (0) +#define sd_debug(x) do { if (sd_msglevel & SDH_DEBUG_VAL) printf x; } while (0) +#define sd_data(x) do { if (sd_msglevel & SDH_DATA_VAL) printf x; } while (0) +#define sd_ctrl(x) do { if (sd_msglevel & SDH_CTRL_VAL) printf x; } while (0) +#else +#define sd_err(x) +#define sd_trace(x) +#define sd_info(x) +#define sd_debug(x) +#define sd_data(x) +#define sd_ctrl(x) +#endif + +#define sd_log(x) + +#define SDIOH_ASSERT(exp) \ + do { if (!(exp)) \ + printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \ + } while (0) + +#define BLOCK_SIZE_F1 64 +#define BLOCK_SIZE_F2 2048 +#define BLOCK_SIZE_F3 2048 + +/* internal return code */ +#define SUCCESS 0 +#undef ERROR +#define ERROR 1 +#define ERROR_UF 2 +#define ERROR_OF 3 + +/* private bus modes */ +#define SDIOH_MODE_SPI 0 + +#define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */ +#define USE_MULTIBLOCK 0x4 + +struct sdioh_info { + uint cfg_bar; /* pci cfg address for bar */ + uint32 caps; /* cached value of capabilities reg */ +#ifndef BCMSPI_ANDROID + void *bar0; /* BAR0 for PCI Device */ +#endif /* !BCMSPI_ANDROID */ + osl_t *osh; /* osh handler */ + void *controller; /* Pointer to SPI Controller's private data struct */ +#ifndef BCMSPI_ANDROID + uint lockcount; /* nest count of spi_lock() calls */ + bool client_intr_enabled; /* interrupt connnected flag */ + bool intr_handler_valid; /* client driver interrupt handler valid */ + sdioh_cb_fn_t intr_handler; /* registered interrupt handler */ + void *intr_handler_arg; /* argument to call interrupt handler */ +#endif /* !BCMSPI_ANDROID */ + bool initialized; /* card initialized */ + uint32 target_dev; /* Target device ID */ + uint32 intmask; /* Current active interrupts */ +#ifndef BCMSPI_ANDROID + void *sdos_info; /* Pointer to per-OS private data */ +#endif /* !BCMSPI_ANDROID */ + uint32 controller_type; /* Host controller type */ + uint8 version; /* Host Controller Spec Compliance Version */ + uint irq; /* Client irq */ + uint32 intrcount; /* Client interrupts */ + uint32 local_intrcount; /* Controller interrupts */ + bool host_init_done; /* Controller initted */ + bool card_init_done; /* Client SDIO interface initted */ + bool polled_mode; /* polling for command completion */ + + bool sd_use_dma; /* DMA on CMD53 */ + bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */ + /* Must be on for sd_multiblock to be effective */ + bool use_client_ints; /* If this is false, make sure to restore */ + /* polling hack in wl_linux.c:wl_timer() */ + int adapter_slot; /* Maybe dealing with multiple slots/controllers */ + int sd_mode; /* SD1/SD4/SPI */ + int client_block_size[SPI_MAX_IOFUNCS]; /* Blocksize */ + uint32 data_xfer_count; /* Current transfer */ + uint16 card_rca; /* Current Address */ + uint8 num_funcs; /* Supported funcs on client */ + uint32 card_dstatus; /* 32bit device status */ + uint32 com_cis_ptr; + uint32 func_cis_ptr[SPI_MAX_IOFUNCS]; + void *dma_buf; + ulong dma_phys; + int r_cnt; /* rx count */ + int t_cnt; /* tx_count */ + uint32 wordlen; /* host processor 16/32bits */ + uint32 prev_fun; + uint32 chip; + uint32 chiprev; + bool resp_delay_all; + bool dwordmode; + bool resp_delay_new; + + struct spierrstats_t spierrstats; +}; + +/************************************************************ + * Internal interfaces: per-port references into bcmspibrcm.c + */ + +/* Global message bits */ +extern uint sd_msglevel; + +/************************************************************** + * Internal interfaces: bcmspibrcm.c references to per-port code + */ + +/* Interrupt (de)registration routines */ +extern int spi_register_irq(sdioh_info_t *sd, uint irq); +extern void spi_free_irq(uint irq, sdioh_info_t *sd); + +/* OS-specific interrupt wrappers (atomic interrupt enable/disable) */ +extern void spi_lock(sdioh_info_t *sd); +extern void spi_unlock(sdioh_info_t *sd); + +/* Allocate/init/free per-OS private data */ +extern int spi_osinit(sdioh_info_t *sd); +extern void spi_osfree(sdioh_info_t *sd); + +#define SPI_RW_FLAG_M BITFIELD_MASK(1) /* Bit [31] - R/W Command Bit */ +#define SPI_RW_FLAG_S 31 +#define SPI_ACCESS_M BITFIELD_MASK(1) /* Bit [30] - Fixed/Incr Access */ +#define SPI_ACCESS_S 30 +#define SPI_FUNCTION_M BITFIELD_MASK(2) /* Bit [29:28] - Function Number */ +#define SPI_FUNCTION_S 28 +#define SPI_REG_ADDR_M BITFIELD_MASK(17) /* Bit [27:11] - Address */ +#define SPI_REG_ADDR_S 11 +#define SPI_LEN_M BITFIELD_MASK(11) /* Bit [10:0] - Packet length */ +#define SPI_LEN_S 0 + +#endif /* _BCM_SPI_BRCM_H */ diff --git a/drivers/net/wireless/bcmdhd/include/bcmsrom_fmt.h b/drivers/net/wireless/bcmdhd/include/bcmsrom_fmt.h index f5246a5..0347674 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmsrom_fmt.h +++ b/drivers/net/wireless/bcmdhd/include/bcmsrom_fmt.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: bcmsrom_fmt.h 327439 2012-04-13 17:44:48Z $ + * $Id: bcmsrom_fmt.h 361510 2012-10-09 00:15:04Z $ */ #ifndef _bcmsrom_fmt_h_ @@ -43,6 +43,7 @@ #define SROM3_SWRGN_OFF 28 /* s/w region offset in words */ #define SROM_SSID 2 +#define SROM_SVID 3 #define SROM_WL1LHMAXP 29 @@ -452,6 +453,7 @@ #define SROM11_THERMAL 87 #define SROM11_MPWR_RAWTS 88 #define SROM11_TS_SLP_OPT_CORRX 89 +#define SROM11_XTAL_FREQ 90 #define SROM11_PHYCAL_TEMPDELTA 92 #define SROM11_MPWR_1_AND_2 93 @@ -465,6 +467,16 @@ #define SROM11_TEMPSENSE_OPTION_MASK 0x3 #define SROM11_TEMPSENSE_OPTION_SHIFT 0 +#define SROM11_PDOFF_2G_40M_A0_MASK 0x000f +#define SROM11_PDOFF_2G_40M_A0_SHIFT 0 +#define SROM11_PDOFF_2G_40M_A1_MASK 0x00f0 +#define SROM11_PDOFF_2G_40M_A1_SHIFT 4 +#define SROM11_PDOFF_2G_40M_A2_MASK 0x0f00 +#define SROM11_PDOFF_2G_40M_A2_SHIFT 8 +#define SROM11_PDOFF_2G_40M_VALID_MASK 0x8000 +#define SROM11_PDOFF_2G_40M_VALID_SHIFT 15 + +#define SROM11_PDOFF_2G_40M 100 #define SROM11_PDOFF_40M_A0 101 #define SROM11_PDOFF_40M_A1 102 #define SROM11_PDOFF_40M_A2 103 @@ -533,25 +545,23 @@ #define SROM11_MCSBW405GLPO_1 179 #define SROM11_MCSBW805GLPO 180 #define SROM11_MCSBW805GLPO_1 181 -#define SROM11_MCSBW1605GLPO 182 -#define SROM11_MCSBW1605GLPO_1 183 +#define SROM11_RPCAL_2G 182 +#define SROM11_RPCAL_5GL 183 #define SROM11_MCSBW205GMPO 184 #define SROM11_MCSBW205GMPO_1 185 #define SROM11_MCSBW405GMPO 186 #define SROM11_MCSBW405GMPO_1 187 #define SROM11_MCSBW805GMPO 188 #define SROM11_MCSBW805GMPO_1 189 -#define SROM11_MCSBW1605GMPO 190 -#define SROM11_MCSBW1605GMPO_1 191 +#define SROM11_RPCAL_5GM 190 +#define SROM11_RPCAL_5GH 191 #define SROM11_MCSBW205GHPO 192 #define SROM11_MCSBW205GHPO_1 193 #define SROM11_MCSBW405GHPO 194 #define SROM11_MCSBW405GHPO_1 195 #define SROM11_MCSBW805GHPO 196 #define SROM11_MCSBW805GHPO_1 197 -#define SROM11_MCSBW1605GHPO 198 -#define SROM11_MCSBW1605GHPO_1 199 - +#define SROM11_RPCAL_5GU 198 #define SROM11_MCSLR5GLPO 200 #define SROM11_MCSLR5GMPO 201 #define SROM11_MCSLR5GHPO 202 diff --git a/drivers/net/wireless/bcmdhd/include/bcmsrom_tbl.h b/drivers/net/wireless/bcmdhd/include/bcmsrom_tbl.h index 040ae6a..cb49421 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmsrom_tbl.h +++ b/drivers/net/wireless/bcmdhd/include/bcmsrom_tbl.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: bcmsrom_tbl.h 327694 2012-04-16 13:22:24Z $ + * $Id: bcmsrom_tbl.h 368874 2012-11-15 02:39:03Z $ */ #ifndef _bcmsrom_tbl_h_ @@ -65,7 +65,11 @@ typedef struct { */ static const sromvar_t pci_sromvars[] = { +#if defined(CABLECPE) + {"devid", 0xffffff00, SRFL_PRHEX, PCI_F0DEVID, 0xffff}, +#else {"devid", 0xffffff00, SRFL_PRHEX|SRFL_NOVAR, PCI_F0DEVID, 0xffff}, +#endif {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK}, {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff}, {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff}, @@ -87,7 +91,7 @@ static const sromvar_t pci_sromvars[] = { {"boardflags2", 0xffffff00, SRFL_PRHEX|SRFL_MORE, SROM8_BFL2, 0xffff}, {"", 0, 0, SROM8_BFL3, 0xffff}, {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff}, - + {"subvid", 0xfffffffc, SRFL_PRHEX, SROM_SVID, 0xffff}, {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff}, {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff}, {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff}, @@ -446,8 +450,8 @@ static const sromvar_t pci_sromvars[] = { {"", 0x00000400, SRFL_PRHEX, SROM10_SWCTRLMAP_2G + 8, 0xffff}, /* sromrev 11 */ - {"boardflags3", 0xfffff800, SRFL_PRHEX|SRFL_MORE, SROM11_BFL3, 0xffff}, - {"", 0, 0, SROM11_BFL3, 0xffff}, + {"boardflags3", 0xfffff800, SRFL_PRHEX|SRFL_MORE, SROM11_BFL4, 0xffff}, + {"", 0, 0, SROM11_BFL5, 0xffff}, {"boardnum", 0xfffff800, 0, SROM11_MACLO, 0xffff}, {"macaddr", 0xfffff800, SRFL_ETHADDR, SROM11_MACHI, 0xffff}, {"ccode", 0xfffff800, SRFL_CCODE, SROM11_CCODE, 0xffff}, @@ -459,12 +463,12 @@ static const sromvar_t pci_sromvars[] = { {"leddc", 0xfffff800, SRFL_NOFFS|SRFL_LEDDC, SROM11_LEDDC, 0xffff}, {"aa2g", 0xfffff800, 0, SROM11_AA, 0x00ff}, {"aa5g", 0xfffff800, 0, SROM11_AA, 0xff00}, - {"agbg0", 0xfffff800, 0, SROM11_AGBG10, 0x00ff}, - {"agbg1", 0xfffff800, 0, SROM11_AGBG10, 0xff00}, - {"agbg2", 0xfffff800, 0, SROM11_AGBG2A0, 0x00ff}, - {"aga0", 0xfffff800, 0, SROM11_AGBG2A0, 0xff00}, - {"aga1", 0xfffff800, 0, SROM11_AGA21, 0x00ff}, - {"aga2", 0xfffff800, 0, SROM11_AGA21, 0xff00}, + {"agbg0", 0xfffff800, 0, SROM11_AGBG10, 0xff00}, + {"agbg1", 0xfffff800, 0, SROM11_AGBG10, 0x00ff}, + {"agbg2", 0xfffff800, 0, SROM11_AGBG2A0, 0xff00}, + {"aga0", 0xfffff800, 0, SROM11_AGBG2A0, 0x00ff}, + {"aga1", 0xfffff800, 0, SROM11_AGA21, 0xff00}, + {"aga2", 0xfffff800, 0, SROM11_AGA21, 0x00ff}, {"txchain", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_TXCHAIN_MASK}, {"rxchain", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_RXCHAIN_MASK}, {"antswitch", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_SWITCH_MASK}, @@ -490,11 +494,17 @@ static const sromvar_t pci_sromvars[] = { {"tempsense_slope", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0x00ff}, {"tempcorrx", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0xfc00}, {"tempsense_option", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0x0300}, + {"xtalfreq", 0xfffff800, 0, SROM11_XTAL_FREQ, 0xffff}, {"phycal_tempdelta", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0x00ff}, {"temps_period", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0x0f00}, {"temps_hysteresis", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0xf000}, {"measpower1", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_1_AND_2, 0x007f}, {"measpower2", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_1_AND_2, 0x3f80}, + + {"pdoffset2g40ma0", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x000f}, + {"pdoffset2g40ma1", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x00f0}, + {"pdoffset2g40ma2", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x0f00}, + {"pdoffset2g40mvalid", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x8000}, {"pdoffset40ma0", 0xfffff800, 0, SROM11_PDOFF_40M_A0, 0xffff}, {"pdoffset40ma1", 0xfffff800, 0, SROM11_PDOFF_40M_A1, 0xffff}, {"pdoffset40ma2", 0xfffff800, 0, SROM11_PDOFF_40M_A2, 0xffff}, @@ -519,28 +529,22 @@ static const sromvar_t pci_sromvars[] = { {"", 0xfffff800, 0, SROM11_MCSBW405GLPO_1, 0xffff}, {"mcsbw805glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GLPO, 0xffff}, {"", 0xfffff800, 0, SROM11_MCSBW805GLPO_1, 0xffff}, - {"mcsbw1605glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW1605GLPO, 0xffff}, - {"", 0xfffff800, 0, SROM11_MCSBW1605GLPO_1, 0xffff}, {"mcsbw205gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GMPO, 0xffff}, {"", 0xfffff800, 0, SROM11_MCSBW205GMPO_1, 0xffff}, {"mcsbw405gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GMPO, 0xffff}, {"", 0xfffff800, 0, SROM11_MCSBW405GMPO_1, 0xffff}, {"mcsbw805gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GMPO, 0xffff}, {"", 0xfffff800, 0, SROM11_MCSBW805GMPO_1, 0xffff}, - {"mcsbw1605gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW1605GMPO, 0xffff}, - {"", 0xfffff800, 0, SROM11_MCSBW1605GMPO_1, 0xffff}, {"mcsbw205ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GHPO, 0xffff}, {"", 0xfffff800, 0, SROM11_MCSBW205GHPO_1, 0xffff}, {"mcsbw405ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GHPO, 0xffff}, {"", 0xfffff800, 0, SROM11_MCSBW405GHPO_1, 0xffff}, {"mcsbw805ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GHPO, 0xffff}, {"", 0xfffff800, 0, SROM11_MCSBW805GHPO_1, 0xffff}, - {"mcsbw1605ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW1605GHPO, 0xffff}, - {"", 0xfffff800, 0, SROM11_MCSBW1605GHPO_1, 0xffff}, {"mcslr5glpo", 0xfffff800, 0, SROM11_MCSLR5GLPO, 0xffff}, {"mcslr5gmpo", 0xfffff800, 0, SROM11_MCSLR5GMPO, 0xffff}, {"mcslr5ghpo", 0xfffff800, 0, SROM11_MCSLR5GHPO, 0xffff}, - {"sb20in40hrrpo", 0xfffff800, 0, SROM11_SB20IN40HRPO, 0xffff}, + {"sb20in40hrpo", 0xfffff800, 0, SROM11_SB20IN40HRPO, 0xffff}, {"sb20in80and160hr5glpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GLPO, 0xffff}, {"sb40and80hr5glpo", 0xfffff800, 0, SROM11_SB40AND80HR5GLPO, 0xffff}, {"sb20in80and160hr5gmpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GMPO, 0xffff}, @@ -558,7 +562,6 @@ static const sromvar_t pci_sromvars[] = { {"dot11agduplrpo", 0xfffff800, 0, SROM11_DOT11AGDUPLRPO, 0xffff}, /* Misc */ - {"pcieingress_war", 0xfffff800, 0, SROM11_PCIEINGRESS_WAR, 0xf}, {"sar2g", 0xfffff800, 0, SROM11_SAR, 0x00ff}, {"sar5g", 0xfffff800, 0, SROM11_SAR, 0xff00}, @@ -593,6 +596,11 @@ static const sromvar_t pci_sromvars[] = { {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0xf800}, {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0xf800}, {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0xf800}, + {"rpcal2g", 0xfffff800, 0, SROM11_RPCAL_2G, 0xffff}, + {"rpcal5gb0", 0xfffff800, 0, SROM11_RPCAL_5GL, 0xffff}, + {"rpcal5gb1", 0xfffff800, 0, SROM11_RPCAL_5GM, 0xffff}, + {"rpcal5gb2", 0xfffff800, 0, SROM11_RPCAL_5GH, 0xffff}, + {"rpcal5gb3", 0xfffff800, 0, SROM11_RPCAL_5GU, 0xffff}, {NULL, 0, 0, 0, 0} }; @@ -786,7 +794,8 @@ static const cis_tuple_t cis_hnbuvars[] = { {HNBU_AA, 0xffffffff, 3, "1aa0 1aa1"}, /* backward compatibility */ {HNBU_AG, 0xffffffff, 5, "1ag0 1ag1 1ag2 1ag3"}, {HNBU_BOARDFLAGS, 0xffffffff, 13, "4boardflags 4boardflags2 4boardflags3"}, - {HNBU_LEDS, 0xffffffff, 5, "1ledbh0 1ledbh1 1ledbh2 1ledbh3"}, + {HNBU_LEDS, 0xffffffff, 13, "1ledbh0 1ledbh1 1ledbh2 1ledbh3 1ledbh4 1ledbh5 " + "1ledbh6 1ledbh7 1ledbh8 1ledbh9 1ledbh10 1ledbh11"}, {HNBU_CCODE, 0xffffffff, 4, "2ccode 1cctl"}, {HNBU_CCKPO, 0xffffffff, 3, "2cckpo"}, {HNBU_OFDMPO, 0xffffffff, 5, "4ofdmpo"}, @@ -869,8 +878,8 @@ static const cis_tuple_t cis_hnbuvars[] = { "2pdoffset80ma0 2pdoffset80ma1 2pdoffset80ma2"}, {HNBU_ACPPR_2GPO, 0xfffff800, 5, "2dot11agofdmhrbw202gpo 2ofdmlrbw202gpo"}, {HNBU_ACPPR_5GPO, 0xfffff800, 31, "4mcsbw805glpo 4mcsbw1605glpo 4mcsbw805gmpo " - "4mcsbw1605gmpo 4mcsbw805ghpo 4mcsbw1605ghpo 2mcslr5rlpo 2mcslr5gmpo 2mcslr5ghpo"}, - {HNBU_ACPPR_SBPO, 0xfffff800, 33, "2sb20in40hrrpo 2sb20in80and160hr5glpo " + "4mcsbw1605gmpo 4mcsbw805ghpo 4mcsbw1605ghpo 2mcslr5glpo 2mcslr5gmpo 2mcslr5ghpo"}, + {HNBU_ACPPR_SBPO, 0xfffff800, 33, "2sb20in40hrpo 2sb20in80and160hr5glpo " "2sb40and80hr5glpo 2sb20in80and160hr5gmpo 2sb40and80hr5gmpo 2sb20in80and160hr5ghpo " "2sb40and80hr5ghpo 2sb20in40lrpo 2sb20in80and160lr5glpo 2sb40and80lr5glpo " "2sb20in80and160lr5gmpo 2sb40and80lr5gmpo 2sb20in80and160lr5ghpo 2sb40and80lr5ghpo " @@ -894,6 +903,10 @@ static const cis_tuple_t cis_hnbuvars[] = { "0rxgains5gelnagaina2 0rxgains2gtrelnabypa2 0rxgains2gtrisoa2 0rxgains2gelnagaina2 " "0rxgains5ghtrelnabypa2 0rxgains5ghtrisoa2 0rxgains5ghelnagaina2 0rxgains5gmtrelnabypa2 " "0rxgains5gmtrisoa2 0rxgains5gmelnagaina2"}, /* special case */ + {HNBU_TXDUTY, 0xfffff800, 9, "2tx_duty_cycle_ofdm_40_5g " + "2tx_duty_cycle_thresh_40_5g 2tx_duty_cycle_ofdm_80_5g 2tx_duty_cycle_thresh_80_5g"}, + {HNBU_PDOFF_2G, 0xfffff800, 3, "0pdoffset2g40ma0 0pdoffset2g40ma1 " + "0pdoffset2g40ma2 0pdoffset2g40mvalid"}, {0xFF, 0xffffffff, 0, ""} }; diff --git a/drivers/net/wireless/bcmdhd/include/bcmutils.h b/drivers/net/wireless/bcmdhd/include/bcmutils.h index cbbd7ef..1b21327 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmutils.h +++ b/drivers/net/wireless/bcmdhd/include/bcmutils.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: bcmutils.h 354184 2012-08-30 08:08:08Z $ + * $Id: bcmutils.h 365744 2012-10-30 22:01:29Z $ */ #ifndef _bcmutils_h_ @@ -121,6 +121,8 @@ typedef struct { uint32 max_avail; uint32 max_used; uint32 queue_capacity; + uint32 rtsfail; + uint32 acked; } pktq_counters_t; #endif @@ -137,7 +139,9 @@ struct pktq { struct pktq_prec q[PKTQ_MAX_PREC]; #ifdef PKTQ_LOG - pktq_counters_t _prec_cnt[PKTQ_MAX_PREC]; + pktq_counters_t _prec_cnt[PKTQ_MAX_PREC]; + pktq_counters_t _prec_bytes[PKTQ_MAX_PREC]; + uint32 _logtime; #endif }; @@ -289,6 +293,7 @@ extern void *pktq_penq(struct pktq *pq, int prec, void *p); extern void *pktq_penq_head(struct pktq *pq, int prec, void *p); extern void *pktq_pdeq(struct pktq *pq, int prec); extern void *pktq_pdeq_prev(struct pktq *pq, int prec, void *prev_p); +extern void *pktq_pdeq_with_fn(struct pktq *pq, int prec, ifpkt_cb_t fn, int arg); extern void *pktq_pdeq_tail(struct pktq *pq, int prec); extern void pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir, @@ -335,7 +340,8 @@ extern uint pkttotlen(osl_t *osh, void *p); extern void *pktlast(osl_t *osh, void *p); extern uint pktsegcnt(osl_t *osh, void *p); extern uint pktsegcnt_war(osl_t *osh, void *p); -extern uint8 *pktoffset(osl_t *osh, void *p, uint offset); +extern uint8 *pktdataoffset(osl_t *osh, void *p, uint offset); +extern void *pktoffset(osl_t *osh, void *p, uint offset); #define PKTPRIO_VDSCP 0x100 @@ -568,6 +574,24 @@ extern int bcm_format_ssid(char* buf, const uchar ssid[], uint ssid_len); #define MAX(a, b) (((a) > (b)) ? (a) : (b)) #endif + +#ifndef LIMIT_TO_RANGE +#define LIMIT_TO_RANGE(x, min, max) \ + ((x) < (min) ? (min) : ((x) > (max) ? (max) : (x))) +#endif + + +#ifndef LIMIT_TO_MAX +#define LIMIT_TO_MAX(x, max) \ + (((x) > (max) ? (max) : (x))) +#endif + + +#ifndef LIMIT_TO_MIN +#define LIMIT_TO_MIN(x, min) \ + (((x) < (min) ? (min) : (x))) +#endif + #define CEIL(x, y) (((x) + ((y) - 1)) / (y)) #define ROUNDUP(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) #define ISALIGNED(a, x) (((uintptr)(a) & ((x) - 1)) == 0) @@ -598,7 +622,7 @@ extern void *_bcmutils_dummy_fn; #ifndef setbit -#ifndef NBBY +#ifndef NBBY #define NBBY 8 #endif #define setbit(a, i) (((uint8 *)a)[(i) / NBBY] |= 1 << ((i) % NBBY)) @@ -607,6 +631,8 @@ extern void *_bcmutils_dummy_fn; #define isclr(a, i) ((((const uint8 *)a)[(i) / NBBY] & (1 << ((i) % NBBY))) == 0) #endif +#define isbitset(a, i) (((a) & (1 << (i))) != 0) + #define NBITS(type) (sizeof(type) * 8) #define NBITVAL(nbits) (1 << (nbits)) #define MAXBITVAL(nbits) ((1 << (nbits)) - 1) @@ -663,7 +689,8 @@ extern void *_bcmutils_dummy_fn; #else #define MACDBG "%02x:%02x:%02x" #define MAC2STRDBG(ea) (ea)[0], (ea)[4], (ea)[5] -#endif /* SIMPLE_MAC_PRINT */ +#endif + typedef struct bcm_bit_desc { uint32 bit; @@ -671,6 +698,13 @@ typedef struct bcm_bit_desc { } bcm_bit_desc_t; +typedef struct bcm_bit_desc_ex { + uint32 mask; + const bcm_bit_desc_t *bitfield; +} bcm_bit_desc_ex_t; + + + typedef struct bcm_tlv { uint8 id; uint8 len; @@ -716,6 +750,9 @@ extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc); #if defined(DHD_DEBUG) || defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) || \ defined(WLMSG_ASSOC) + +extern int bcm_format_field(const bcm_bit_desc_ex_t *bd, uint32 field, char* buf, int len); + extern int bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char* buf, int len); #endif @@ -737,7 +774,7 @@ extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key); extern const char *bcmerrorstr(int bcmerror); -extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key); + typedef uint32 mbool; diff --git a/drivers/net/wireless/bcmdhd/include/dbus.h b/drivers/net/wireless/bcmdhd/include/dbus.h index c5ea223..9784e1f 100644 --- a/drivers/net/wireless/bcmdhd/include/dbus.h +++ b/drivers/net/wireless/bcmdhd/include/dbus.h @@ -22,7 +22,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: dbus.h 323680 2012-03-26 17:52:31Z $ + * $Id: dbus.h 349214 2012-08-07 10:04:38Z $ */ #ifndef __DBUS_H__ @@ -33,7 +33,6 @@ #define DBUSTRACE(args) #define DBUSERR(args) #define DBUSINFO(args) -#define DBUSTRACE(args) #define DBUSDBGLOCK(args) enum { @@ -77,8 +76,8 @@ enum { #define DBUS_TX_RETRY_LIMIT 3 /* retries for failed txirb */ #define DBUS_TX_TIMEOUT_INTERVAL 250 /* timeout for txirb complete, in ms */ -#define DBUS_BUFFER_SIZE_TX 16000 -#define DBUS_BUFFER_SIZE_RX 5000 +#define DBUS_BUFFER_SIZE_TX 32000 +#define DBUS_BUFFER_SIZE_RX 24000 #define DBUS_BUFFER_SIZE_TX_NOAGG 2048 #define DBUS_BUFFER_SIZE_RX_NOAGG 2048 @@ -296,7 +295,6 @@ extern int dbus_send_ctl(dbus_pub_t *pub, uint8 *buf, int len); extern int dbus_recv_ctl(dbus_pub_t *pub, uint8 *buf, int len); extern int dbus_recv_bulk(dbus_pub_t *pub, uint32 ep_idx); extern int dbus_poll_intr(dbus_pub_t *pub); - extern int dbus_get_stats(dbus_pub_t *pub, dbus_stats_t *stats); extern int dbus_get_attrib(dbus_pub_t *pub, dbus_attrib_t *attrib); extern int dbus_get_device_speed(dbus_pub_t *pub); diff --git a/drivers/net/wireless/bcmdhd/include/dhdioctl.h b/drivers/net/wireless/bcmdhd/include/dhdioctl.h index 11fff55..53bab2c 100644 --- a/drivers/net/wireless/bcmdhd/include/dhdioctl.h +++ b/drivers/net/wireless/bcmdhd/include/dhdioctl.h @@ -25,7 +25,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: dhdioctl.h 354894 2012-09-04 12:34:07Z $ + * $Id: dhdioctl.h 358413 2012-09-24 04:50:47Z $ */ #ifndef _dhdioctl_h_ @@ -93,7 +93,8 @@ enum { #define DHD_ARPOE_VAL 0x4000 #define DHD_REORDER_VAL 0x8000 #define DHD_WL_VAL 0x10000 -#define DHD_WL_VAL2 0x20000 +#define DHD_NOCHECKDIED_VAL 0x20000 /* UTF WAR */ +#define DHD_WL_VAL2 0x40000 #ifdef SDTEST /* For pktgen iovar */ diff --git a/drivers/net/wireless/bcmdhd/include/epivers.h b/drivers/net/wireless/bcmdhd/include/epivers.h index 60f9838..12470ad 100644 --- a/drivers/net/wireless/bcmdhd/include/epivers.h +++ b/drivers/net/wireless/bcmdhd/include/epivers.h @@ -28,28 +28,28 @@ #define EPI_MAJOR_VERSION 1 -#define EPI_MINOR_VERSION 28 +#define EPI_MINOR_VERSION 61 -#define EPI_RC_NUMBER 13 +#define EPI_RC_NUMBER 47 -#define EPI_INCREMENTAL_NUMBER 1 +#define EPI_INCREMENTAL_NUMBER 0 #define EPI_BUILD_NUMBER 0 -#define EPI_VERSION 1, 28, 13, 1 +#define EPI_VERSION 1, 61, 47, 0 -#define EPI_VERSION_NUM 0x011c0d01 +#define EPI_VERSION_NUM 0x013d2f00 -#define EPI_VERSION_DEV 1.28.13 +#define EPI_VERSION_DEV 1.61.47 /* Driver Version String, ASCII, 32 chars max */ #ifdef BCMINTERNAL -#define EPI_VERSION_STR "1.28.13.1 (r BCMINT)" +#define EPI_VERSION_STR "1.61.47 (r BCMINT)" #else #ifdef WLTEST -#define EPI_VERSION_STR "1.28.13.1 (r WLTEST)" +#define EPI_VERSION_STR "1.61.47 (r WLTEST)" #else -#define EPI_VERSION_STR "1.28.13.1 (r)" +#define EPI_VERSION_STR "1.61.47 (r)" #endif #endif /* BCMINTERNAL */ diff --git a/drivers/net/wireless/bcmdhd/include/hndsoc.h b/drivers/net/wireless/bcmdhd/include/hndsoc.h index 66640c3..f5c161b 100644 --- a/drivers/net/wireless/bcmdhd/include/hndsoc.h +++ b/drivers/net/wireless/bcmdhd/include/hndsoc.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: hndsoc.h 309193 2012-01-19 00:03:57Z $ + * $Id: hndsoc.h 365041 2012-10-26 09:10:35Z $ */ #ifndef _HNDSOC_H @@ -46,10 +46,8 @@ #define SI_WRAP_BASE 0x18100000 /* Wrapper space base */ #define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ -#define SI_MAXCORES 16 /* Max cores (this is arbitrary, for software - * convenience and could be changed if we - * make any larger chips - */ + +#define SI_MAXCORES 32 /* NorthStar has more cores */ #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */ #define SI_FASTRAM_SWAPPED 0x19800000 @@ -59,6 +57,13 @@ #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ #define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ #define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ +#define SI_FLASH_WINDOW 0x01000000 /* Flash XIP Window */ + +#define SI_NS_NANDFLASH 0x1c000000 /* NorthStar NAND flash base */ +#define SI_NS_NORFLASH 0x1e000000 /* NorthStar NOR flash base */ +#define SI_NS_ROM 0xfffd0000 /* NorthStar ROM */ +#define SI_NS_FLASH_WINDOW 0x02000000 /* Flash XIP Window */ + #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ #define SI_ARMCR4_ROM 0x000f0000 /* ARM Cortex-R4 ROM */ #define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ @@ -147,7 +152,21 @@ */ #define CC_4706_CORE_ID 0x500 /* chipcommon core */ +#define NS_PCIEG2_CORE_ID 0x501 /* PCIE Gen 2 core */ +#define NS_DMA_CORE_ID 0x502 /* DMA core */ +#define NS_SDIO3_CORE_ID 0x503 /* SDIO3 core */ +#define NS_USB20_CORE_ID 0x504 /* USB2.0 core */ +#define NS_USB30_CORE_ID 0x505 /* USB3.0 core */ +#define NS_A9JTAG_CORE_ID 0x506 /* ARM Cortex A9 JTAG core */ +#define NS_DDR23_CORE_ID 0x507 /* Denali DDR2/DDR3 memory controller */ +#define NS_ROM_CORE_ID 0x508 /* ROM core */ +#define NS_NAND_CORE_ID 0x509 /* NAND flash controller core */ +#define NS_QSPI_CORE_ID 0x50a /* SPI flash controller core */ +#define NS_CCB_CORE_ID 0x50b /* ChipcommonB core */ #define SOCRAM_4706_CORE_ID 0x50e /* internal memory core */ +#define NS_SOCRAM_CORE_ID SOCRAM_4706_CORE_ID +#define ARMCA9_CORE_ID 0x510 /* ARM Cortex A9 core (ihost) */ +#define NS_IHOST_CORE_ID ARMCA9_CORE_ID /* ARM Cortex A9 core (ihost) */ #define GMAC_COMMON_4706_CORE_ID 0x5dc /* Gigabit MAC core */ #define GMAC_4706_CORE_ID 0x52d /* Gigabit MAC core */ #define AMEMC_CORE_ID 0x52e /* DDR1/2 memory controller core */ @@ -172,6 +191,7 @@ #define SOCI_SB 0 #define SOCI_AI 1 #define SOCI_UBUS 2 +#define SOCI_NAI 3 /* Common core control flags */ #define SICF_BIST_EN 0x8000 @@ -187,6 +207,14 @@ #define SISF_DMA64 0x1000 #define SISF_CORE_BITS 0x0fff +/* Norstar core status flags */ +#define SISF_NS_BOOTDEV_MASK 0x0003 /* ROM core */ +#define SISF_NS_BOOTDEV_NOR 0x0000 /* ROM core */ +#define SISF_NS_BOOTDEV_NAND 0x0001 /* ROM core */ +#define SISF_NS_BOOTDEV_ROM 0x0002 /* ROM core */ +#define SISF_NS_BOOTDEV_OFFLOAD 0x0003 /* ROM core */ +#define SISF_NS_SKUVEC_MASK 0x000c /* ROM core */ + /* A register that is common to all cores to * communicate w/PMU regarding clock control. */ @@ -232,4 +260,18 @@ #define BISZ_BSSEND_IDX 6 /* 6: bss end */ #define BISZ_SIZE 7 /* descriptor size in 32-bit integers */ +/* Boot/Kernel related defintion and functions */ +#define SOC_BOOTDEV_ROM 0x00000001 +#define SOC_BOOTDEV_PFLASH 0x00000002 +#define SOC_BOOTDEV_SFLASH 0x00000004 +#define SOC_BOOTDEV_NANDFLASH 0x00000008 + +#define SOC_KNLDEV_NORFLASH 0x00000002 +#define SOC_KNLDEV_NANDFLASH 0x00000004 + +#ifndef _LANGUAGE_ASSEMBLY +int soc_boot_dev(void *sih); +int soc_knl_dev(void *sih); +#endif /* _LANGUAGE_ASSEMBLY */ + #endif /* _HNDSOC_H */ diff --git a/drivers/net/wireless/bcmdhd/include/linux_osl.h b/drivers/net/wireless/bcmdhd/include/linux_osl.h index 5fd1dbd..7d6481f 100644 --- a/drivers/net/wireless/bcmdhd/include/linux_osl.h +++ b/drivers/net/wireless/bcmdhd/include/linux_osl.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: linux_osl.h 352246 2012-08-22 05:42:04Z $ + * $Id: linux_osl.h 388661 2013-03-04 05:50:45Z $ */ #ifndef _linux_osl_h_ @@ -92,7 +92,6 @@ extern struct pci_dev *osl_pci_device(osl_t *osh); typedef struct { bool pkttag; - uint pktalloced; bool mmbus; pktfree_cb_fn_t tx_fn; void *tx_ctx; @@ -139,7 +138,8 @@ extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa); #define DMA_UNMAP(osh, pa, size, direction, p, dmah) \ osl_dma_unmap((osh), (pa), (size), (direction)) -extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction); +extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction, void *p, + hnddma_seg_map_t *txp_dmah); extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction); @@ -165,8 +165,11 @@ extern int osl_error(int bcmerror); #include <linuxver.h> #include <linux/kernel.h> #include <linux/string.h> - +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 4, 29) #define OSL_SYSUPTIME() ((uint32)jiffies_to_msecs(jiffies)) +#else +#define OSL_SYSUPTIME() ((uint32)jiffies * (1000 / HZ)) +#endif #define printf(fmt, args...) printk(fmt , ## args) #include <linux/kernel.h> #include <linux/string.h> @@ -218,6 +221,9 @@ extern int osl_error(int bcmerror); #define OSL_UNCACHED(va) ((void *)va) #define OSL_CACHED(va) ((void *)va) + +#define OSL_CACHE_FLUSH(va, len) + #define OSL_PREF_RANGE_LD(va, sz) #define OSL_PREF_RANGE_ST(va, sz) @@ -260,14 +266,14 @@ extern int osl_error(int bcmerror); #define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data) #define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len) #define PKTHEADROOM(osh, skb) (PKTDATA(osh, skb)-(((struct sk_buff*)(skb))->head)) -#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail)) +#define PKTTAILROOM(osh, skb) skb_tailroom((struct sk_buff*)(skb)) +#define PKTPADTAILROOM(osh, skb, padlen) skb_pad((struct sk_buff*)(skb), (padlen)) #define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next) #define PKTSETNEXT(osh, skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x)) #define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len)) #define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes)) #define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes)) #define PKTTAG(skb) ((void*)(((struct sk_buff*)(skb))->cb)) -#define PKTALLOCED(osh) ((osl_pubinfo_t *)(osh))->pktalloced #define PKTSETPOOL(osh, skb, x, y) do {} while (0) #define PKTPOOL(osh, skb) FALSE #define PKTSHRINK(osh, m) (m) @@ -286,6 +292,18 @@ typedef struct ctfpool { uint slow_allocs; } ctfpool_t; #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36) +#define FASTBUF (1 << 0) +#define CTFBUF (1 << 1) +#define PKTSETFAST(osh, skb) ((((struct sk_buff*)(skb))->pktc_flags) |= FASTBUF) +#define PKTCLRFAST(osh, skb) ((((struct sk_buff*)(skb))->pktc_flags) &= (~FASTBUF)) +#define PKTSETCTF(osh, skb) ((((struct sk_buff*)(skb))->pktc_flags) |= CTFBUF) +#define PKTCLRCTF(osh, skb) ((((struct sk_buff*)(skb))->pktc_flags) &= (~CTFBUF)) +#define PKTISFAST(osh, skb) ((((struct sk_buff*)(skb))->pktc_flags) & FASTBUF) +#define PKTISCTF(osh, skb) ((((struct sk_buff*)(skb))->pktc_flags) & CTFBUF) +#define PKTFAST(osh, skb) (((struct sk_buff*)(skb))->pktc_flags) +#else #define FASTBUF (1 << 16) #define CTFBUF (1 << 17) #define PKTSETFAST(osh, skb) ((((struct sk_buff*)(skb))->mac_len) |= FASTBUF) @@ -295,6 +313,7 @@ typedef struct ctfpool { #define PKTISFAST(osh, skb) ((((struct sk_buff*)(skb))->mac_len) & FASTBUF) #define PKTISCTF(osh, skb) ((((struct sk_buff*)(skb))->mac_len) & CTFBUF) #define PKTFAST(osh, skb) (((struct sk_buff*)(skb))->mac_len) +#endif #else #define FASTBUF (1 << 0) #define CTFBUF (1 << 1) @@ -307,8 +326,13 @@ typedef struct ctfpool { #define PKTFAST(osh, skb) (((struct sk_buff*)(skb))->__unused) #endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36) +#define CTFPOOLPTR(osh, skb) (((struct sk_buff*)(skb))->ctfpool) +#define CTFPOOLHEAD(osh, skb) (((ctfpool_t *)((struct sk_buff*)(skb))->ctfpool)->head) +#else #define CTFPOOLPTR(osh, skb) (((struct sk_buff*)(skb))->sk) #define CTFPOOLHEAD(osh, skb) (((ctfpool_t *)((struct sk_buff*)(skb))->sk)->head) +#endif extern void *osl_ctfpool_add(osl_t *osh); extern void osl_ctfpool_replenish(osl_t *osh, uint thresh); @@ -320,20 +344,45 @@ extern void osl_ctfpool_stats(osl_t *osh, void *b); #ifdef HNDCTF #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36) +#define SKIPCT (1 << 2) +#define CHAINED (1 << 3) +#define PKTSETSKIPCT(osh, skb) (((struct sk_buff*)(skb))->pktc_flags |= SKIPCT) +#define PKTCLRSKIPCT(osh, skb) (((struct sk_buff*)(skb))->pktc_flags &= (~SKIPCT)) +#define PKTSKIPCT(osh, skb) (((struct sk_buff*)(skb))->pktc_flags & SKIPCT) +#define PKTSETCHAINED(osh, skb) (((struct sk_buff*)(skb))->pktc_flags |= CHAINED) +#define PKTCLRCHAINED(osh, skb) (((struct sk_buff*)(skb))->pktc_flags &= (~CHAINED)) +#define PKTISCHAINED(skb) (((struct sk_buff*)(skb))->pktc_flags & CHAINED) +#else #define SKIPCT (1 << 18) +#define CHAINED (1 << 19) #define PKTSETSKIPCT(osh, skb) (((struct sk_buff*)(skb))->mac_len |= SKIPCT) #define PKTCLRSKIPCT(osh, skb) (((struct sk_buff*)(skb))->mac_len &= (~SKIPCT)) #define PKTSKIPCT(osh, skb) (((struct sk_buff*)(skb))->mac_len & SKIPCT) +#define PKTSETCHAINED(osh, skb) (((struct sk_buff*)(skb))->mac_len |= CHAINED) +#define PKTCLRCHAINED(osh, skb) (((struct sk_buff*)(skb))->mac_len &= (~CHAINED)) +#define PKTISCHAINED(skb) (((struct sk_buff*)(skb))->mac_len & CHAINED) +#endif #else #define SKIPCT (1 << 2) +#define CHAINED (1 << 3) #define PKTSETSKIPCT(osh, skb) (((struct sk_buff*)(skb))->__unused |= SKIPCT) #define PKTCLRSKIPCT(osh, skb) (((struct sk_buff*)(skb))->__unused &= (~SKIPCT)) #define PKTSKIPCT(osh, skb) (((struct sk_buff*)(skb))->__unused & SKIPCT) +#define PKTSETCHAINED(osh, skb) (((struct sk_buff*)(skb))->__unused |= CHAINED) +#define PKTCLRCHAINED(osh, skb) (((struct sk_buff*)(skb))->__unused &= (~CHAINED)) +#define PKTISCHAINED(skb) (((struct sk_buff*)(skb))->__unused & CHAINED) #endif +typedef struct ctf_mark { + uint32 value; +} ctf_mark_t; +#define CTF_MARK(m) (m.value) #else #define PKTSETSKIPCT(osh, skb) #define PKTCLRSKIPCT(osh, skb) #define PKTSKIPCT(osh, skb) +#define CTF_MARK(m) 0 #endif extern void osl_pktfree(osl_t *osh, void *skb, bool send); @@ -357,8 +406,24 @@ extern struct sk_buff *osl_pkt_tonative(osl_t *osh, void *pkt); #define PKTSHARED(skb) (((struct sk_buff*)(skb))->cloned) +#ifdef CONFIG_NF_CONNTRACK_MARK +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)) +#define PKTMARK(p) (((struct sk_buff *)(p))->mark) +#define PKTSETMARK(p, m) ((struct sk_buff *)(p))->mark = (m) +#else +#define PKTMARK(p) (((struct sk_buff *)(p))->nfmark) +#define PKTSETMARK(p, m) ((struct sk_buff *)(p))->nfmark = (m) +#endif +#else +#define PKTMARK(p) 0 +#define PKTSETMARK(p, m) +#endif + +#define PKTALLOCED(osh) osl_pktalloced(osh) +extern uint osl_pktalloced(osl_t *osh); + #define DMA_MAP(osh, va, size, direction, p, dmah) \ - osl_dma_map((osh), (va), (size), (direction)) + osl_dma_map((osh), (va), (size), (direction), (p), (dmah)) #ifdef PKTC @@ -373,27 +438,47 @@ struct chain_node { #define CHAIN_NODE(skb) ((struct chain_node*)&(((struct sk_buff*)skb)->stamp)) #endif +#define PKTCSETATTR(s, f, p, b) ({CHAIN_NODE(s)->flags = (f); CHAIN_NODE(s)->pkts = (p); \ + CHAIN_NODE(s)->bytes = (b);}) +#define PKTCCLRATTR(s) ({CHAIN_NODE(s)->flags = CHAIN_NODE(s)->pkts = \ + CHAIN_NODE(s)->bytes = 0;}) +#define PKTCGETATTR(s) (CHAIN_NODE(s)->flags << 29 | CHAIN_NODE(s)->pkts << 20 | \ + CHAIN_NODE(s)->bytes) #define PKTCCNT(skb) (CHAIN_NODE(skb)->pkts) #define PKTCLEN(skb) (CHAIN_NODE(skb)->bytes) #define PKTCFLAGS(skb) (CHAIN_NODE(skb)->flags) -#define PKTCSETCNT(skb, c) (CHAIN_NODE(skb)->pkts = (c) & ((1 << 9) - 1)) -#define PKTCSETLEN(skb, l) (CHAIN_NODE(skb)->bytes = (l) & ((1 << 20) - 1)) +#define PKTCSETCNT(skb, c) (CHAIN_NODE(skb)->pkts = (c)) +#define PKTCINCRCNT(skb) (CHAIN_NODE(skb)->pkts++) +#define PKTCADDCNT(skb, c) (CHAIN_NODE(skb)->pkts += (c)) +#define PKTCSETLEN(skb, l) (CHAIN_NODE(skb)->bytes = (l)) +#define PKTCADDLEN(skb, l) (CHAIN_NODE(skb)->bytes += (l)) #define PKTCSETFLAG(skb, fb) (CHAIN_NODE(skb)->flags |= (fb)) #define PKTCCLRFLAG(skb, fb) (CHAIN_NODE(skb)->flags &= ~(fb)) #define PKTCLINK(skb) (CHAIN_NODE(skb)->link) #define PKTSETCLINK(skb, x) (CHAIN_NODE(skb)->link = (struct sk_buff*)(x)) -#define PKTISCHAINED(skb) (PKTCLINK(skb) != NULL) #define FOREACH_CHAINED_PKT(skb, nskb) \ for (; (skb) != NULL; (skb) = (nskb)) \ - if ((nskb) = PKTCLINK(skb), PKTSETCLINK((skb), NULL), 1) + if ((nskb) = (PKTISCHAINED(skb) ? PKTCLINK(skb) : NULL), \ + PKTSETCLINK((skb), NULL), 1) #define PKTCFREE(osh, skb, send) \ do { \ void *nskb; \ ASSERT((skb) != NULL); \ FOREACH_CHAINED_PKT((skb), nskb) { \ + PKTCLRCHAINED((osh), (skb)); \ + PKTCCLRATTR((skb)); \ PKTFREE((osh), (skb), (send)); \ } \ } while (0) +#define PKTCENQTAIL(h, t, p) \ +do { \ + if ((t) == NULL) { \ + (h) = (t) = (p); \ + } else { \ + PKTSETCLINK((t), (p)); \ + (t) = (p); \ + } \ +} while (0) #endif #else diff --git a/drivers/net/wireless/bcmdhd/include/linuxver.h b/drivers/net/wireless/bcmdhd/include/linuxver.h index 3c2a168..149b740 100644 --- a/drivers/net/wireless/bcmdhd/include/linuxver.h +++ b/drivers/net/wireless/bcmdhd/include/linuxver.h @@ -22,7 +22,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: linuxver.h 353905 2012-08-29 07:33:08Z $ + * $Id: linuxver.h 367714 2012-11-09 03:26:01Z $ */ #ifndef _linuxver_h_ @@ -511,29 +511,28 @@ typedef struct { #endif -#define PROC_START(thread_func, owner, tsk_ctl, flags) \ +#ifdef USE_KTHREAD_API +#define PROC_START(thread_func, owner, tsk_ctl, flags, name) \ { \ sema_init(&((tsk_ctl)->sema), 0); \ init_completion(&((tsk_ctl)->completed)); \ (tsk_ctl)->parent = owner; \ (tsk_ctl)->terminated = FALSE; \ - (tsk_ctl)->thr_pid = kernel_thread(thread_func, tsk_ctl, flags); \ + (tsk_ctl)->p_task = kthread_run(thread_func, tsk_ctl, (char*)name); \ + (tsk_ctl)->thr_pid = (tsk_ctl)->p_task->pid; \ DBG_THR(("%s thr:%lx created\n", __FUNCTION__, (tsk_ctl)->thr_pid)); \ - if ((tsk_ctl)->thr_pid > 0) \ - wait_for_completion(&((tsk_ctl)->completed)); \ - DBG_THR(("%s thr:%lx started\n", __FUNCTION__, (tsk_ctl)->thr_pid)); \ } - -#ifdef USE_KTHREAD_API -#define PROC_START2(thread_func, owner, tsk_ctl, flags, name) \ +#else +#define PROC_START(thread_func, owner, tsk_ctl, flags, name) \ { \ sema_init(&((tsk_ctl)->sema), 0); \ init_completion(&((tsk_ctl)->completed)); \ (tsk_ctl)->parent = owner; \ (tsk_ctl)->terminated = FALSE; \ - (tsk_ctl)->p_task = kthread_run(thread_func, tsk_ctl, (char*)name); \ - (tsk_ctl)->thr_pid = (tsk_ctl)->p_task->pid; \ - DBG_THR(("%s thr:%lx created\n", __FUNCTION__, (tsk_ctl)->thr_pid)); \ + (tsk_ctl)->thr_pid = kernel_thread(thread_func, tsk_ctl, flags); \ + if ((tsk_ctl)->thr_pid > 0) \ + wait_for_completion(&((tsk_ctl)->completed)); \ + DBG_THR(("%s thr:%lx started\n", __FUNCTION__, (tsk_ctl)->thr_pid)); \ } #endif diff --git a/drivers/net/wireless/bcmdhd/include/osl.h b/drivers/net/wireless/bcmdhd/include/osl.h index ca171d8..b7173fd 100644 --- a/drivers/net/wireless/bcmdhd/include/osl.h +++ b/drivers/net/wireless/bcmdhd/include/osl.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: osl.h 320905 2012-03-13 15:33:25Z $ + * $Id: osl.h 346935 2012-07-25 00:24:55Z $ */ #ifndef _osl_h_ @@ -69,20 +69,30 @@ typedef void (*osl_wreg_fn_t)(void *ctx, volatile void *reg, unsigned int val, #endif #if !defined(PKTC) +#define PKTCGETATTR(s) (0) +#define PKTCSETATTR(skb, f, p, b) +#define PKTCCLRATTR(skb) #define PKTCCNT(skb) (0) #define PKTCLEN(skb) (0) #define PKTCFLAGS(skb) (0) #define PKTCSETCNT(skb, c) +#define PKTCINCRCNT(skb) +#define PKTCADDCNT(skb, c) #define PKTCSETLEN(skb, l) +#define PKTCADDLEN(skb, l) #define PKTCSETFLAG(skb, fb) #define PKTCCLRFLAG(skb, fb) -#define PKTCLINK(skb) PKTLINK(skb) -#define PKTSETCLINK(skb, x) PKTSETLINK((skb), (x)) -#define PKTISCHAINED(skb) FALSE +#define PKTCLINK(skb) NULL +#define PKTSETCLINK(skb, x) #define FOREACH_CHAINED_PKT(skb, nskb) \ for ((nskb) = NULL; (skb) != NULL; (skb) = (nskb)) #define PKTCFREE PKTFREE -#endif +#endif +#ifndef HNDCTF +#define PKTSETCHAINED(osh, skb) +#define PKTCLRCHAINED(osh, skb) +#define PKTISCHAINED(skb) (FALSE) +#endif #endif diff --git a/drivers/net/wireless/bcmdhd/include/pcicfg.h b/drivers/net/wireless/bcmdhd/include/pcicfg.h index 5f7df6a..0a984e8a 100644 --- a/drivers/net/wireless/bcmdhd/include/pcicfg.h +++ b/drivers/net/wireless/bcmdhd/include/pcicfg.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: pcicfg.h 309193 2012-01-19 00:03:57Z $ + * $Id: pcicfg.h 346935 2012-07-25 00:24:55Z $ */ #ifndef _h_pcicfg_ @@ -55,6 +55,7 @@ #define PCI_CFG_PIN 0x3d #define PCI_CFG_MINGNT 0x3e #define PCI_CFG_MAXLAT 0x3f +#define PCI_CFG_DEVCTRL 0xd8 #define PCI_BAR0_WIN 0x80 #define PCI_BAR1_WIN 0x84 #define PCI_SPROM_CONTROL 0x88 diff --git a/drivers/net/wireless/bcmdhd/include/proto/802.11.h b/drivers/net/wireless/bcmdhd/include/proto/802.11.h index 1632e7d..aca9316 100644 --- a/drivers/net/wireless/bcmdhd/include/proto/802.11.h +++ b/drivers/net/wireless/bcmdhd/include/proto/802.11.h @@ -21,7 +21,7 @@ * * Fundamental types and constants relating to 802.11 * - * $Id: 802.11.h 346820 2012-07-24 13:53:12Z $ + * $Id: 802.11.h 368403 2012-11-13 17:20:09Z $ */ #ifndef _802_11_H_ @@ -410,6 +410,36 @@ BWL_PRE_PACKED_STRUCT struct dot11y_action_ext_csa { struct dot11_csa_body b; } BWL_POST_PACKED_STRUCT; + +BWL_PRE_PACKED_STRUCT struct dot11_wide_bw_channel_switch { + uint8 id; + uint8 len; + uint8 channel_width; + uint8 center_frequency_segment_0; + uint8 center_frequency_segment_1; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_wide_bw_channel_switch dot11_wide_bw_chan_switch_ie_t; + +#define DOT11_WIDE_BW_SWITCH_IE_LEN 3 + + +BWL_PRE_PACKED_STRUCT struct dot11_channel_switch_wrapper { + uint8 id; + uint8 len; + dot11_wide_bw_chan_switch_ie_t wb_chan_switch_ie; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_channel_switch_wrapper dot11_chan_switch_wrapper_ie_t; + + +BWL_PRE_PACKED_STRUCT struct dot11_vht_transmit_power_envelope { + uint8 id; + uint8 len; + uint8 transmit_power_info; + uint8 local_max_transmit_power_20; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_vht_transmit_power_envelope dot11_vht_transmit_power_envelope_ie_t; + + BWL_PRE_PACKED_STRUCT struct dot11_obss_coex { uint8 id; uint8 len; @@ -469,7 +499,7 @@ typedef struct dot11_extcap dot11_extcap_t; #define DOT11_MEASURE_TYPE_NOISE 4 #define DOT11_MEASURE_TYPE_BEACON 5 #define DOT11_MEASURE_TYPE_FRAME 6 -#define DOT11_MEASURE_TYPE_STATS 7 +#define DOT11_MEASURE_TYPE_STAT 7 #define DOT11_MEASURE_TYPE_LCI 8 #define DOT11_MEASURE_TYPE_TXSTREAM 9 #define DOT11_MEASURE_TYPE_PAUSE 255 @@ -564,8 +594,8 @@ typedef struct dot11_ibss_dfs dot11_ibss_dfs_t; #define WME_OUI "\x00\x50\xf2" -#define WME_OUI_LEN 3 #define WME_OUI_TYPE 2 +#define WME_OUI_LEN 3 #define WME_TYPE 2 #define WME_SUBTYPE_IE 0 #define WME_SUBTYPE_PARAM_IE 1 @@ -1060,6 +1090,7 @@ typedef struct ti_ie ti_ie_t; #define DOT11_MNG_EXT_RATES_ID 50 #define DOT11_MNG_AP_CHREP_ID 51 #define DOT11_MNG_NBR_REP_ID 52 +#define DOT11_MNG_RCPI_ID 53 #define DOT11_MNG_MDIE_ID 54 #define DOT11_MNG_FTIE_ID 55 #define DOT11_MNG_FT_TI_ID 56 @@ -1067,12 +1098,20 @@ typedef struct ti_ie ti_ie_t; #define DOT11_MNG_EXT_CSA_ID 60 #define DOT11_MNG_HT_ADD 61 #define DOT11_MNG_EXT_CHANNEL_OFFSET 62 +#define DOT11_MNG_BSS_AVR_ACCESS_DELAY_ID 63 +#define DOT11_MNG_ANTENNA_ID 64 +#define DOT11_MNG_RSNI_ID 65 +#define DOT11_MNG_MEASUREMENT_PILOT_TX_ID 66 +#define DOT11_MNG_BSS_AVAL_ADMISSION_CAP_ID 67 +#define DOT11_MNG_BSS_AC_ACCESS_DELAY_ID 68 #define DOT11_MNG_WAPI_ID 68 #define DOT11_MNG_TIME_ADVERTISE_ID 69 #define DOT11_MNG_RRM_CAP_ID 70 +#define DOT11_MNG_MULTIPLE_BSSID_ID 71 #define DOT11_MNG_HT_BSS_COEXINFO_ID 72 #define DOT11_MNG_HT_BSS_CHANNEL_REPORT_ID 73 #define DOT11_MNG_HT_OBSS_ID 74 +#define DOT11_MNG_MMIE_ID 76 #define DOT11_MNG_CHANNEL_USAGE 97 #define DOT11_MNG_TIME_ZONE_ID 98 #define DOT11_MNG_LINK_IDENTIFIER_ID 101 @@ -1089,6 +1128,10 @@ typedef struct ti_ie ti_ie_t; #define DOT11_MNG_EXT_CAP_ID 127 #define DOT11_MNG_VHT_CAP_ID 191 #define DOT11_MNG_VHT_OPERATION_ID 192 +#define DOT11_MNG_WIDE_BW_CHANNEL_SWITCH_ID 194 +#define DOT11_MNG_VHT_TRANSMIT_POWER_ENVELOPE_ID 195 +#define DOT11_MNG_CHANNEL_SWITCH_WRAPPER_ID 196 + #define DOT11_MNG_WPA_ID 221 #define DOT11_MNG_PROPR_ID 221 @@ -1096,8 +1139,27 @@ typedef struct ti_ie ti_ie_t; #define DOT11_MNG_VS_ID 221 -#define DOT11_RATE_BASIC 0x80 -#define DOT11_RATE_MASK 0x7F + + + +#define DOT11_RATE_1M 2 +#define DOT11_RATE_2M 4 +#define DOT11_RATE_5M5 11 +#define DOT11_RATE_11M 22 +#define DOT11_RATE_6M 12 +#define DOT11_RATE_9M 18 +#define DOT11_RATE_12M 24 +#define DOT11_RATE_18M 36 +#define DOT11_RATE_24M 48 +#define DOT11_RATE_36M 72 +#define DOT11_RATE_48M 96 +#define DOT11_RATE_54M 108 +#define DOT11_RATE_MAX 108 + + +#define DOT11_RATE_BASIC 0x80 +#define DOT11_RATE_MASK 0x7F + #define DOT11_MNG_ERP_LEN 1 @@ -1128,6 +1190,8 @@ typedef struct ti_ie ti_ie_t; #define DOT11_EXT_CAP_SPSMP 6 +#define DOT11_EXT_CAP_PROXY_ARP 12 + #define DOT11_EXT_CAP_BSS_TRANSITION_MGMT 19 #define DOT11_EXT_CAP_IW 31 @@ -1153,7 +1217,7 @@ typedef struct ti_ie ti_ie_t; #define DOT11_ACTION_CAT_HT 7 #define DOT11_ACTION_CAT_SA_QUERY 8 #define DOT11_ACTION_CAT_PDPA 9 -#define DOT11_ACTION_CAT_BSSMGMT 10 +#define DOT11_ACTION_CAT_WNM 10 #define DOT11_ACTION_NOTIFICATION 17 #define DOT11_ACTION_CAT_VSP 126 #define DOT11_ACTION_CAT_VS 127 @@ -1411,6 +1475,8 @@ typedef struct dot11_ft_res dot11_ft_res_t; #define DOT11_RRM_CAP_LEN 5 +#define RCPI_IE_LEN 1 +#define RSNI_IE_LEN 1 BWL_PRE_PACKED_STRUCT struct dot11_rrm_cap_ie { uint8 cap[DOT11_RRM_CAP_LEN]; } BWL_POST_PACKED_STRUCT; @@ -1455,6 +1521,7 @@ BWL_PRE_PACKED_STRUCT struct dot11_rmreq { uint8 action; uint8 token; uint16 reps; + uint8 data[1]; } BWL_POST_PACKED_STRUCT; typedef struct dot11_rmreq dot11_rmreq_t; #define DOT11_RMREQ_LEN 5 @@ -1533,9 +1600,189 @@ typedef struct dot11_rmrep_bcn dot11_rmrep_bcn_t; #define DOT11_RMREP_BCN_FRM_BODY 1 -BWL_PRE_PACKED_STRUCT struct dot11_rmrep_nbr { +#define DOT11_RMREP_FRAME_COUNT_REPORT 1 + + +BWL_PRE_PACKED_STRUCT struct dot11_rmreq_chanload { + uint8 id; + uint8 len; + uint8 token; + uint8 mode; + uint8 type; + uint8 reg; + uint8 channel; + uint16 interval; + uint16 duration; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rmreq_chanload dot11_rmreq_chanload_t; +#define DOT11_RMREQ_CHANLOAD_LEN 11 + + +BWL_PRE_PACKED_STRUCT struct dot11_rmrep_chanload { + uint8 reg; + uint8 channel; + uint32 starttime[2]; + uint16 duration; + uint8 channel_load; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rmrep_chanload dot11_rmrep_chanload_t; +#define DOT11_RMREP_CHANLOAD_LEN 13 + + +BWL_PRE_PACKED_STRUCT struct dot11_rmreq_noise { + uint8 id; + uint8 len; + uint8 token; + uint8 mode; + uint8 type; + uint8 reg; + uint8 channel; + uint16 interval; + uint16 duration; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rmreq_noise dot11_rmreq_noise_t; +#define DOT11_RMREQ_NOISE_LEN 11 + + +BWL_PRE_PACKED_STRUCT struct dot11_rmrep_noise { + uint8 reg; + uint8 channel; + uint32 starttime[2]; + uint16 duration; + uint8 antid; + uint8 anpi; + uint8 ipi0_dens; + uint8 ipi1_dens; + uint8 ipi2_dens; + uint8 ipi3_dens; + uint8 ipi4_dens; + uint8 ipi5_dens; + uint8 ipi6_dens; + uint8 ipi7_dens; + uint8 ipi8_dens; + uint8 ipi9_dens; + uint8 ipi10_dens; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rmrep_noise dot11_rmrep_noise_t; +#define DOT11_RMREP_NOISE_LEN 25 + + +BWL_PRE_PACKED_STRUCT struct dot11_rmreq_frame { + uint8 id; + uint8 len; + uint8 token; + uint8 mode; + uint8 type; + uint8 reg; + uint8 channel; + uint16 interval; + uint16 duration; + uint8 req_type; + struct ether_addr ta; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rmreq_frame dot11_rmreq_frame_t; +#define DOT11_RMREQ_FRAME_LEN 18 + + +BWL_PRE_PACKED_STRUCT struct dot11_rmrep_frame { + uint8 reg; + uint8 channel; + uint32 starttime[2]; + uint16 duration; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rmrep_frame dot11_rmrep_frame_t; +#define DOT11_RMREP_FRAME_LEN 12 + + +BWL_PRE_PACKED_STRUCT struct dot11_rmrep_frmentry { + struct ether_addr ta; struct ether_addr bssid; - uint32 bssid_info; + uint8 phy_type; + uint8 avg_rcpi; + uint8 last_rsni; + uint8 last_rcpi; + uint8 ant_id; + uint16 frame_cnt; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rmrep_frmentry dot11_rmrep_frmentry_t; +#define DOT11_RMREP_FRMENTRY_LEN 19 + + +BWL_PRE_PACKED_STRUCT struct dot11_rmreq_stat { + uint8 id; + uint8 len; + uint8 token; + uint8 mode; + uint8 type; + struct ether_addr peer; + uint16 interval; + uint16 duration; + uint8 group_id; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rmreq_stat dot11_rmreq_stat_t; +#define DOT11_RMREQ_STAT_LEN 16 + + +BWL_PRE_PACKED_STRUCT struct dot11_rmrep_stat { + uint16 duration; + uint8 group_id; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rmrep_stat dot11_rmrep_stat_t; + + +BWL_PRE_PACKED_STRUCT struct dot11_rmreq_tx_stream { + uint8 id; + uint8 len; + uint8 token; + uint8 mode; + uint8 type; + uint16 interval; + uint16 duration; + struct ether_addr peer; + uint8 traffic_id; + uint8 bin0_range; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rmreq_tx_stream dot11_rmreq_tx_stream_t; + + +BWL_PRE_PACKED_STRUCT struct dot11_rmrep_tx_stream { + uint32 starttime[2]; + uint16 duration; + struct ether_addr peer; + uint8 traffic_id; + uint8 reason; + uint32 txmsdu_cnt; + uint32 msdu_discarded_cnt; + uint32 msdufailed_cnt; + uint32 msduretry_cnt; + uint32 cfpolls_lost_cnt; + uint32 avrqueue_delay; + uint32 avrtx_delay; + uint8 bin0_range; + uint32 bin0; + uint32 bin1; + uint32 bin2; + uint32 bin3; + uint32 bin4; + uint32 bin5; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rmrep_tx_stream dot11_rmrep_tx_stream_t; + + +BWL_PRE_PACKED_STRUCT struct dot11_rmreq_pause_time { + uint8 id; + uint8 len; + uint8 token; + uint8 mode; + uint8 type; + uint16 pause_time; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rmreq_pause_time dot11_rmreq_pause_time_t; + + +BWL_PRE_PACKED_STRUCT struct dot11_rmrep_nbr { + struct ether_addr bssid; + uint32 bssid_info; uint8 reg; uint8 channel; uint8 phytype; @@ -1545,6 +1792,15 @@ typedef struct dot11_rmrep_nbr dot11_rmrep_nbr_t; #define DOT11_RMREP_NBR_LEN 13 +BWL_PRE_PACKED_STRUCT struct dot11_rrmrep_nbr { + uint8 id; + uint8 len; + dot11_rmrep_nbr_t nbr_rrmrep; +} BWL_POST_PACKED_STRUCT; +typedef struct dot11_rrmrep_nbr dot11_rrmrep_nbr_t; +#define DOT11_RRMREP_NBR_LEN 15 + + #define DOT11_BSSTYPE_INFRASTRUCTURE 0 #define DOT11_BSSTYPE_INDEPENDENT 1 #define DOT11_BSSTYPE_ANY 2 @@ -1585,42 +1841,56 @@ typedef struct dot11_lmrep dot11_lmrep_t; -#define HT_SIG1_MCS_MASK 0x00007F -#define HT_SIG1_CBW 0x000080 -#define HT_SIG1_HT_LENGTH 0xFFFF00 +#define HT_SIG1_MCS_MASK 0x00007F +#define HT_SIG1_CBW 0x000080 +#define HT_SIG1_HT_LENGTH 0xFFFF00 -#define HT_SIG2_SMOOTHING 0x000001 -#define HT_SIG2_NOT_SOUNDING 0x000002 -#define HT_SIG2_RESERVED 0x000004 -#define HT_SIG2_AGGREGATION 0x000008 -#define HT_SIG2_STBC_MASK 0x000030 -#define HT_SIG2_STBC_SHIFT 4 -#define HT_SIG2_FEC_CODING 0x000040 -#define HT_SIG2_SHORT_GI 0x000080 -#define HT_SIG2_ESS_MASK 0x000300 -#define HT_SIG2_ESS_SHIFT 8 -#define HT_SIG2_CRC 0x03FC00 -#define HT_SIG2_TAIL 0x1C0000 +#define HT_SIG2_SMOOTHING 0x000001 +#define HT_SIG2_NOT_SOUNDING 0x000002 +#define HT_SIG2_RESERVED 0x000004 +#define HT_SIG2_AGGREGATION 0x000008 +#define HT_SIG2_STBC_MASK 0x000030 +#define HT_SIG2_STBC_SHIFT 4 +#define HT_SIG2_FEC_CODING 0x000040 +#define HT_SIG2_SHORT_GI 0x000080 +#define HT_SIG2_ESS_MASK 0x000300 +#define HT_SIG2_ESS_SHIFT 8 +#define HT_SIG2_CRC 0x03FC00 +#define HT_SIG2_TAIL 0x1C0000 -#define APHY_SLOT_TIME 9 -#define APHY_SIFS_TIME 16 -#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME)) -#define APHY_PREAMBLE_TIME 16 -#define APHY_SIGNAL_TIME 4 -#define APHY_SYMBOL_TIME 4 -#define APHY_SERVICE_NBITS 16 -#define APHY_TAIL_NBITS 6 -#define APHY_CWMIN 15 +#define HT_T_LEG_PREAMBLE 16 +#define HT_T_L_SIG 4 +#define HT_T_SIG 8 +#define HT_T_LTF1 4 +#define HT_T_GF_LTF1 8 +#define HT_T_LTFs 4 +#define HT_T_STF 4 +#define HT_T_GF_STF 8 +#define HT_T_SYML 4 +#define HT_N_SERVICE 16 +#define HT_N_TAIL 6 -#define BPHY_SLOT_TIME 20 -#define BPHY_SIFS_TIME 10 -#define BPHY_DIFS_TIME 50 -#define BPHY_PLCP_TIME 192 -#define BPHY_PLCP_SHORT_TIME 96 -#define BPHY_CWMIN 31 + +#define APHY_SLOT_TIME 9 +#define APHY_SIFS_TIME 16 +#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME)) +#define APHY_PREAMBLE_TIME 16 +#define APHY_SIGNAL_TIME 4 +#define APHY_SYMBOL_TIME 4 +#define APHY_SERVICE_NBITS 16 +#define APHY_TAIL_NBITS 6 +#define APHY_CWMIN 15 + + +#define BPHY_SLOT_TIME 20 +#define BPHY_SIFS_TIME 10 +#define BPHY_DIFS_TIME 50 +#define BPHY_PLCP_TIME 192 +#define BPHY_PLCP_SHORT_TIME 96 +#define BPHY_CWMIN 31 #define DOT11_OFDM_SIGNAL_EXTENSION 6 @@ -1635,30 +1905,36 @@ typedef int vht_group_id_t; -#define VHT_SIGA1_CONST_MASK 0x800004 +#define VHT_SIGA1_CONST_MASK 0x800004 -#define VHT_SIGA1_20MHZ_VAL 0x000000 -#define VHT_SIGA1_40MHZ_VAL 0x000001 -#define VHT_SIGA1_80MHZ_VAL 0x000002 -#define VHT_SIGA1_160MHZ_VAL 0x000003 +#define VHT_SIGA1_BW_MASK 0x000003 +#define VHT_SIGA1_20MHZ_VAL 0x000000 +#define VHT_SIGA1_40MHZ_VAL 0x000001 +#define VHT_SIGA1_80MHZ_VAL 0x000002 +#define VHT_SIGA1_160MHZ_VAL 0x000003 -#define VHT_SIGA1_STBC 0x000008 +#define VHT_SIGA1_STBC 0x000008 -#define VHT_SIGA1_GID_MAX_GID 0x3f -#define VHT_SIGA1_GID_SHIFT 4 -#define VHT_SIGA1_GID_TO_AP 0x00 -#define VHT_SIGA1_GID_NOT_TO_AP 0x3f +#define VHT_SIGA1_GID_MASK 0x0003f0 +#define VHT_SIGA1_GID_SHIFT 4 +#define VHT_SIGA1_GID_TO_AP 0x00 +#define VHT_SIGA1_GID_NOT_TO_AP 0x3f +#define VHT_SIGA1_GID_MAX_GID 0x3f -#define VHT_SIGA1_NSTS_SHIFT 10 #define VHT_SIGA1_NSTS_SHIFT_MASK_USER0 0x001C00 +#define VHT_SIGA1_NSTS_SHIFT 10 -#define VHT_SIGA1_PARTIAL_AID_SHIFT 13 +#define VHT_SIGA1_PARTIAL_AID_MASK 0x3fe000 +#define VHT_SIGA1_PARTIAL_AID_SHIFT 13 + +#define VHT_SIGA1_TXOP_PS_NOT_ALLOWED 0x400000 #define VHT_SIGA2_GI_NONE 0x000000 #define VHT_SIGA2_GI_SHORT 0x000001 #define VHT_SIGA2_GI_W_MOD10 0x000002 #define VHT_SIGA2_CODING_LDPC 0x000004 +#define VHT_SIGA2_LDPC_EXTRA_OFDM_SYM 0x000008 #define VHT_SIGA2_BEAMFORM_ENABLE 0x000100 #define VHT_SIGA2_MCS_SHIFT 4 @@ -1666,8 +1942,17 @@ typedef int vht_group_id_t; #define VHT_SIGA2_TAIL_MASK 0xfc0000 #define VHT_SIGA2_TAIL_VALUE 0x000000 -#define VHT_SIGA2_SVC_BITS 16 -#define VHT_SIGA2_TAIL_BITS 6 + +#define VHT_T_LEG_PREAMBLE 16 +#define VHT_T_L_SIG 4 +#define VHT_T_SIG_A 8 +#define VHT_T_LTF 4 +#define VHT_T_STF 4 +#define VHT_T_SIG_B 4 +#define VHT_T_SYML 4 + +#define VHT_N_SERVICE 16 +#define VHT_N_TAIL 6 @@ -1693,6 +1978,9 @@ typedef struct d11cnt { +#define BRCM_SYSCAP_WET_TUNNEL 0x0100 + + #define BRCM_OUI "\x00\x10\x18" @@ -1722,6 +2010,7 @@ typedef struct brcm_ie brcm_ie_t; #define BRF1_RX_LARGE_AGG 0x10 #define BRF1_RFAWARE_DCS 0x20 #define BRF1_SOFTAP 0x40 +#define BRF1_DWDS 0x80 BWL_PRE_PACKED_STRUCT struct vndr_ie { @@ -1952,6 +2241,8 @@ typedef struct dot11_obss_ie dot11_obss_ie_t; + + BWL_PRE_PACKED_STRUCT struct vht_cap_ie { uint32 vht_cap_info; @@ -1962,23 +2253,22 @@ BWL_PRE_PACKED_STRUCT struct vht_cap_ie { } BWL_POST_PACKED_STRUCT; typedef struct vht_cap_ie vht_cap_ie_t; + #define VHT_CAP_IE_LEN 12 -#define VHT_CAP_INFO_MAX_MPDU_LEN_MASK 0x00000003 + +#define VHT_CAP_INFO_MAX_MPDU_LEN_MASK 0x00000003 #define VHT_CAP_INFO_SUPP_CHAN_WIDTH_MASK 0x0000000c #define VHT_CAP_INFO_LDPC 0x00000010 #define VHT_CAP_INFO_SGI_80MHZ 0x00000020 - #define VHT_CAP_INFO_SGI_160MHZ 0x00000040 #define VHT_CAP_INFO_TX_STBC 0x00000080 - #define VHT_CAP_INFO_RX_STBC_MASK 0x00000700 #define VHT_CAP_INFO_RX_STBC_SHIFT 8 #define VHT_CAP_INFO_SU_BEAMFMR 0x00000800 #define VHT_CAP_INFO_SU_BEAMFMEE 0x00001000 #define VHT_CAP_INFO_NUM_BMFMR_ANT_MASK 0x0000e000 #define VHT_CAP_INFO_NUM_BMFMR_ANT_SHIFT 13 - #define VHT_CAP_INFO_NUM_SOUNDING_DIM_MASK 0x00070000 #define VHT_CAP_INFO_NUM_SOUNDING_DIM_SHIFT 16 #define VHT_CAP_INFO_MU_BEAMFMR 0x00080000 @@ -1987,39 +2277,75 @@ typedef struct vht_cap_ie vht_cap_ie_t; #define VHT_CAP_INFO_HTCVHT 0x00400000 #define VHT_CAP_INFO_AMPDU_MAXLEN_EXP_MASK 0x03800000 #define VHT_CAP_INFO_AMPDU_MAXLEN_EXP_SHIFT 23 - #define VHT_CAP_INFO_LINK_ADAPT_CAP_MASK 0x0c000000 #define VHT_CAP_INFO_LINK_ADAPT_CAP_SHIFT 26 -#define VHT_CAP_SUPP_MCS_RX_HIGHEST_RATE_MASK 0x1fff -#define VHT_CAP_SUPP_MCS_RX_HIGHEST_RATE_SHIFT 0 +#define VHT_CAP_SUPP_MCS_RX_HIGHEST_RATE_MASK 0x1fff +#define VHT_CAP_SUPP_MCS_RX_HIGHEST_RATE_SHIFT 0 + +#define VHT_CAP_SUPP_MCS_TX_HIGHEST_RATE_MASK 0x1fff +#define VHT_CAP_SUPP_MCS_TX_HIGHEST_RATE_SHIFT 0 + +#define VHT_CAP_MCS_MAP_0_7 0 +#define VHT_CAP_MCS_MAP_0_8 1 +#define VHT_CAP_MCS_MAP_0_9 2 +#define VHT_CAP_MCS_MAP_NONE 3 +#define VHT_CAP_MCS_MAP_S 2 +#define VHT_CAP_MCS_MAP_M 0x3 + +#define VHT_CAP_MCS_MAP_NONE_ALL 0xffff + +#define VHT_CAP_MCS_MAP_0_9_NSS3 \ + ((VHT_CAP_MCS_MAP_0_9 << VHT_MCS_MAP_GET_SS_IDX(1)) | \ + (VHT_CAP_MCS_MAP_0_9 << VHT_MCS_MAP_GET_SS_IDX(2)) | \ + (VHT_CAP_MCS_MAP_0_9 << VHT_MCS_MAP_GET_SS_IDX(3))) -#define VHT_CAP_SUPP_MCS_TX_HIGHEST_RATE_MASK 0x1fff -#define VHT_CAP_SUPP_MCS_TX_HIGHEST_RATE_SHIFT 0 +#define VHT_CAP_MCS_MAP_NSS_MAX 8 -#define VHT_CAP_MCS_MAP_0_7 0 -#define VHT_CAP_MCS_MAP_0_8 1 -#define VHT_CAP_MCS_MAP_0_9 2 -#define VHT_CAP_MCS_MAP_NONE 3 -#define VHT_CAP_MCS_MAP_NSS_MAX 8 +#define VHT_CAP_MCS_MAP_CREATE(mcsmap, nss, mcs) \ + do { \ + int i; \ + for (i = 1; i <= nss; i++) { \ + VHT_MCS_MAP_SET_MCS_PER_SS(i, mcs, mcsmap); \ + } \ + } while (0) + + +#define VHT_MCS_CODE_TO_MCS_MAP(mcs_code) \ + ((mcs_code == VHT_CAP_MCS_MAP_0_7) ? 0xff : \ + (mcs_code == VHT_CAP_MCS_MAP_0_8) ? 0x1ff : \ + (mcs_code == VHT_CAP_MCS_MAP_0_9) ? 0x3ff : 0) + + +#define VHT_MCS_MAP_TO_MCS_CODE(mcs_map) \ + ((mcs_map == 0xff) ? VHT_CAP_MCS_MAP_0_7 : \ + (mcs_map == 0x1ff) ? VHT_CAP_MCS_MAP_0_8 : \ + (mcs_map == 0x3ff) ? VHT_CAP_MCS_MAP_0_9 : VHT_CAP_MCS_MAP_NONE) typedef enum vht_cap_chan_width { - VHT_CAP_CHAN_WIDTH_20_40 = 0x00, - VHT_CAP_CHAN_WIDTH_80 = 0x04, - VHT_CAP_CHAN_WIDTH_160 = 0x08 + VHT_CAP_CHAN_WIDTH_SUPPORT_MANDATORY = 0x00, + VHT_CAP_CHAN_WIDTH_SUPPORT_160 = 0x04, + VHT_CAP_CHAN_WIDTH_SUPPORT_160_8080 = 0x08 } vht_cap_chan_width_t; typedef enum vht_cap_max_mpdu_len { - VHT_CAP_MPDU_MAX_4K = 0x00, - VHT_CAP_MPDU_MAX_8K = 0x01, - VHT_CAP_MPDU_MAX_11K = 0x02 + VHT_CAP_MPDU_MAX_4K = 0x00, + VHT_CAP_MPDU_MAX_8K = 0x01, + VHT_CAP_MPDU_MAX_11K = 0x02 } vht_cap_max_mpdu_len_t; +#define VHT_MPDU_LIMIT_4K 3895 +#define VHT_MPDU_LIMIT_8K 7991 +#define VHT_MPDU_LIMIT_11K 11454 + + + + BWL_PRE_PACKED_STRUCT struct vht_op_ie { uint8 chan_width; uint8 chan1; @@ -2028,6 +2354,7 @@ BWL_PRE_PACKED_STRUCT struct vht_op_ie { } BWL_POST_PACKED_STRUCT; typedef struct vht_op_ie vht_op_ie_t; + #define VHT_OP_IE_LEN 5 typedef enum vht_op_chan_width { @@ -2038,16 +2365,31 @@ typedef enum vht_op_chan_width { } vht_op_chan_width_t; -#define VHT_MCS_MAP_GET_SS_IDX(nss) (((nss)-1)*2) +#define BRCM_VHT_FEATURES_OUITYPE 0x4 +BWL_PRE_PACKED_STRUCT struct vht_features_ie_hdr { + uint8 oui[3]; + uint8 type; + uint8 rate_mask; +} BWL_POST_PACKED_STRUCT; +typedef struct vht_features_ie_hdr vht_features_ie_hdr_t; + + +#define VHT_MCS_MAP_GET_SS_IDX(nss) (((nss)-1) * VHT_CAP_MCS_MAP_S) #define VHT_MCS_MAP_GET_MCS_PER_SS(nss, mcsMap) \ - (((mcsMap) >> VHT_MCS_MAP_GET_SS_IDX(nss)) & 0x3) + (((mcsMap) >> VHT_MCS_MAP_GET_SS_IDX(nss)) & VHT_CAP_MCS_MAP_M) #define VHT_MCS_MAP_SET_MCS_PER_SS(nss, numMcs, mcsMap) \ - ((mcsMap) |= (((numMcs) & 0x3) << VHT_MCS_MAP_GET_SS_IDX(nss))) + do { \ + (mcsMap) &= (~(VHT_CAP_MCS_MAP_M << VHT_MCS_MAP_GET_SS_IDX(nss))); \ + (mcsMap) |= (((numMcs) & VHT_CAP_MCS_MAP_M) << VHT_MCS_MAP_GET_SS_IDX(nss)); \ + } while (0) +#define VHT_MCS_SS_SUPPORTED(nss, mcsMap) \ + (VHT_MCS_MAP_GET_MCS_PER_SS((nss), (mcsMap)) != VHT_CAP_MCS_MAP_NONE) + #define WPA_OUI "\x00\x50\xF2" -#define WPA_OUI_LEN 3 #define WPA_OUI_TYPE 1 +#define WPA_OUI_LEN 3 #define WPA_VERSION 1 #define WPA2_OUI "\x00\x0F\xAC" #define WPA2_OUI_LEN 3 @@ -2075,6 +2417,8 @@ typedef enum vht_op_chan_width { #define WFA_OUI_TYPE_TPC 8 #ifdef WLTDLS +#define WFA_OUI_TYPE_TPQ 4 +#define WFA_OUI_TYPE_TPS 5 #define WFA_OUI_TYPE_WFD 10 #endif @@ -2110,6 +2454,7 @@ typedef enum vht_op_chan_width { #define AES_KEY_SIZE 16 #define AES_MIC_SIZE 8 #define BIP_KEY_SIZE 16 +#define BIP_MIC_SIZE 8 #define WCN_OUI "\x00\x50\xf2" @@ -2158,7 +2503,6 @@ BWL_PRE_PACKED_STRUCT struct dot11_timeout_ie { typedef struct dot11_timeout_ie dot11_timeout_ie_t; - BWL_PRE_PACKED_STRUCT struct dot11_gtk_ie { uint8 id; uint8 len; @@ -2169,6 +2513,16 @@ BWL_PRE_PACKED_STRUCT struct dot11_gtk_ie { } BWL_POST_PACKED_STRUCT; typedef struct dot11_gtk_ie dot11_gtk_ie_t; + +BWL_PRE_PACKED_STRUCT struct mmic_ie { + uint8 id; + uint8 len; + uint16 key_id; + uint8 ipn[6]; + uint8 mic[BIP_MIC_SIZE]; +} BWL_POST_PACKED_STRUCT; +typedef struct mmic_ie mmic_ie_t; + #define BSSID_INVALID "\x00\x00\x00\x00\x00\x00" #define BSSID_BROADCAST "\xFF\xFF\xFF\xFF\xFF\xFF" diff --git a/drivers/net/wireless/bcmdhd/include/proto/bcmevent.h b/drivers/net/wireless/bcmdhd/include/proto/bcmevent.h index 312074d..243a975 100644 --- a/drivers/net/wireless/bcmdhd/include/proto/bcmevent.h +++ b/drivers/net/wireless/bcmdhd/include/proto/bcmevent.h @@ -23,7 +23,7 @@ * * Dependencies: proto/bcmeth.h * - * $Id: bcmevent.h 326276 2012-04-06 23:16:42Z $ + * $Id: bcmevent.h 369617 2012-11-19 16:45:34Z $ * */ @@ -188,8 +188,23 @@ typedef BWL_PRE_PACKED_STRUCT struct bcm_event { #define WLC_E_AUTH_REQ 91 #define WLC_E_TDLS_PEER_EVENT 92 #define WLC_E_SPEEDY_RECREATE_FAIL 93 -#define WLC_E_LAST 94 - +#define WLC_E_NATIVE 94 +#define WLC_E_PKTDELAY_IND 95 +#define WLC_E_AWDL_AW 96 +#define WLC_E_AWDL_ROLE 97 +#define WLC_E_AWDL_EVENT 98 +#ifdef WLNIC +#define WLC_E_NIC_AF_TXS 99 +#define WLC_E_NIC_NIC_REPORT 100 +#endif +#define WLC_E_BEACON_FRAME_RX 101 +#define WLC_E_SERVICE_FOUND 102 +#define WLC_E_GAS_FRAGMENT_RX 103 +#define WLC_E_GAS_COMPLETE 104 +#define WLC_E_P2PO_ADD_DEVICE 105 +#define WLC_E_P2PO_DEL_DEVICE 106 +#define WLC_E_IBSS_COALESCE 107 +#define WLC_E_LAST 108 typedef struct { @@ -216,8 +231,8 @@ extern const int bcmevent_names_size; #define WLC_E_STATUS_SUPPRESS 12 #define WLC_E_STATUS_NOCHANS 13 #ifdef BCMCCX -#define WLC_E_STATUS_CCXFASTRM 14 -#endif +#define WLC_E_STATUS_CCXFASTRM 14 +#endif #define WLC_E_STATUS_CS_ABORT 15 #define WLC_E_STATUS_ERROR 16 @@ -251,20 +266,20 @@ extern const int bcmevent_names_size; #define WLC_E_PRUNE_NO_COMMON_RATES 9 #define WLC_E_PRUNE_BASIC_RATES 10 #ifdef BCMCCX -#define WLC_E_PRUNE_CCXFAST_PREVAP 11 -#endif +#define WLC_E_PRUNE_CCXFAST_PREVAP 11 +#endif #define WLC_E_PRUNE_CIPHER_NA 12 #define WLC_E_PRUNE_KNOWN_STA 13 #ifdef BCMCCX -#define WLC_E_PRUNE_CCXFAST_DROAM 14 -#endif +#define WLC_E_PRUNE_CCXFAST_DROAM 14 +#endif #define WLC_E_PRUNE_WDS_PEER 15 #define WLC_E_PRUNE_QBSS_LOAD 16 #define WLC_E_PRUNE_HOME_AP 17 #ifdef BCMCCX -#define WLC_E_PRUNE_AP_BLOCKED 18 -#define WLC_E_PRUNE_NO_DIAG_SUPPORT 19 -#endif +#define WLC_E_PRUNE_AP_BLOCKED 18 +#define WLC_E_PRUNE_NO_DIAG_SUPPORT 19 +#endif #define WLC_E_SUP_OTHER 0 @@ -321,6 +336,7 @@ typedef struct wl_event_data_if { #define WLC_E_IF_ROLE_BTA_ACCEPTOR 6 #endif +#define WLC_E_IF_FLAGS_BSSCFG_NOIF 0x1 #define WLC_E_LINK_BCN_LOSS 1 #define WLC_E_LINK_DISASSOC 2 @@ -337,6 +353,27 @@ typedef struct wl_event_data_if { #define WLC_E_TDLS_PEER_DISCONNECTED 2 +typedef BWL_PRE_PACKED_STRUCT struct wl_event_gas { + uint16 channel; + uint8 dialog_token; + uint8 fragment_id; + uint16 status_code; + uint16 data_len; + uint8 data[1]; +} BWL_POST_PACKED_STRUCT wl_event_gas_t; + + +typedef BWL_PRE_PACKED_STRUCT struct wl_event_sd { + uint8 protocol; + uint16 channel; + uint8 dialog_token; + uint8 fragment_id; + uint16 status_code; + uint16 data_len; + uint8 data[1]; +} BWL_POST_PACKED_STRUCT wl_event_sd_t; + + #include <packed_section_end.h> #endif diff --git a/drivers/net/wireless/bcmdhd/include/proto/bcmip.h b/drivers/net/wireless/bcmdhd/include/proto/bcmip.h index d5c3b76..02ddd37 100644 --- a/drivers/net/wireless/bcmdhd/include/proto/bcmip.h +++ b/drivers/net/wireless/bcmdhd/include/proto/bcmip.h @@ -21,7 +21,7 @@ * * Fundamental constants relating to IP Protocol * - * $Id: bcmip.h 290206 2011-10-17 19:13:51Z $ + * $Id: bcmip.h 346935 2012-07-25 00:24:55Z $ */ #ifndef _bcmip_h_ @@ -52,15 +52,16 @@ #define IP_PROT_ICMP6 0x3a -#define IPV4_VER_HL_OFFSET 0 -#define IPV4_TOS_OFFSET 1 -#define IPV4_PKTLEN_OFFSET 2 -#define IPV4_PKTFLAG_OFFSET 6 -#define IPV4_PROT_OFFSET 9 -#define IPV4_CHKSUM_OFFSET 10 -#define IPV4_SRC_IP_OFFSET 12 -#define IPV4_DEST_IP_OFFSET 16 -#define IPV4_OPTIONS_OFFSET 20 +#define IPV4_VER_HL_OFFSET 0 +#define IPV4_TOS_OFFSET 1 +#define IPV4_PKTLEN_OFFSET 2 +#define IPV4_PKTFLAG_OFFSET 6 +#define IPV4_PROT_OFFSET 9 +#define IPV4_CHKSUM_OFFSET 10 +#define IPV4_SRC_IP_OFFSET 12 +#define IPV4_DEST_IP_OFFSET 16 +#define IPV4_OPTIONS_OFFSET 20 +#define IPV4_MIN_HEADER_LEN 20 #define IPV4_VER_MASK 0xf0 @@ -204,6 +205,8 @@ ipv6_exthdr_len(uint8 *h, uint8 *proto) return len; } +#define IPV4_ISMULTI(a) (((a) & 0xf0000000) == 0xe0000000) + #include <packed_section_end.h> diff --git a/drivers/net/wireless/bcmdhd/include/proto/ethernet.h b/drivers/net/wireless/bcmdhd/include/proto/ethernet.h index e455185..7b9b2e2 100644 --- a/drivers/net/wireless/bcmdhd/include/proto/ethernet.h +++ b/drivers/net/wireless/bcmdhd/include/proto/ethernet.h @@ -21,10 +21,10 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: ethernet.h 309193 2012-01-19 00:03:57Z $ + * $Id: ethernet.h 354714 2012-09-03 03:12:21Z $ */ -#ifndef _NET_ETHERNET_H_ +#ifndef _NET_ETHERNET_H_ #define _NET_ETHERNET_H_ #ifndef _TYPEDEFS_H_ @@ -67,6 +67,11 @@ #define ETHER_TYPE_IPV6 0x86dd #define ETHER_TYPE_BRCM 0x886c #define ETHER_TYPE_802_1X 0x888e +#ifdef PLC +#define ETHER_TYPE_88E1 0x88e1 +#define ETHER_TYPE_8912 0x8912 +#define ETHER_TYPE_GIGLED 0xffff +#endif #define ETHER_TYPE_802_1X_PREAUTH 0x88c7 #define ETHER_TYPE_WAI 0x88b4 #define ETHER_TYPE_89_0D 0x890d @@ -94,7 +99,7 @@ ((uint8 *)ea)[5] = ((mgrp_ip) >> 0) & 0xff; \ } -#ifndef __INCif_etherh +#ifndef __INCif_etherh BWL_PRE_PACKED_STRUCT struct ether_header { uint8 ether_dhost[ETHER_ADDR_LEN]; @@ -122,19 +127,26 @@ BWL_PRE_PACKED_STRUCT struct ether_addr { -#define ether_cmp(a, b) (!(((short*)(a))[0] == ((short*)(b))[0]) | \ - !(((short*)(a))[1] == ((short*)(b))[1]) | \ - !(((short*)(a))[2] == ((short*)(b))[2])) +#define eacmp(a, b) ((((uint16 *)(a))[0] ^ ((uint16 *)(b))[0]) | \ + (((uint16 *)(a))[1] ^ ((uint16 *)(b))[1]) | \ + (((uint16 *)(a))[2] ^ ((uint16 *)(b))[2])) + +#define ether_cmp(a, b) eacmp(a, b) -#define ether_copy(s, d) { \ - ((short*)(d))[0] = ((const short*)(s))[0]; \ - ((short*)(d))[1] = ((const short*)(s))[1]; \ - ((short*)(d))[2] = ((const short*)(s))[2]; } +#define eacopy(s, d) \ +do { \ + ((uint16 *)(d))[0] = ((const uint16 *)(s))[0]; \ + ((uint16 *)(d))[1] = ((const uint16 *)(s))[1]; \ + ((uint16 *)(d))[2] = ((const uint16 *)(s))[2]; \ +} while (0) + +#define ether_copy(s, d) eacopy(s, d) static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}}; static const struct ether_addr ether_null = {{0, 0, 0, 0, 0, 0}}; +static const struct ether_addr ether_ipv6_mcast = {{0x33, 0x33, 0x00, 0x00, 0x00, 0x01}}; #define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \ ((uint8 *)(ea))[1] & \ @@ -149,6 +161,11 @@ static const struct ether_addr ether_null = {{0, 0, 0, 0, 0, 0}}; ((uint8 *)(ea))[4] | \ ((uint8 *)(ea))[5]) == 0) +#define ETHER_ISNULLDEST(da) ((((const uint16 *)(da))[0] | \ + ((const uint16 *)(da))[1] | \ + ((const uint16 *)(da))[2]) == 0) +#define ETHER_ISNULLSRC(sa) ETHER_ISNULLDEST(sa) + #define ETHER_MOVE_HDR(d, s) \ do { \ struct ether_header t; \ @@ -156,6 +173,8 @@ do { \ *(struct ether_header *)(d) = t; \ } while (0) +#define ETHER_ISUCAST(ea) ((((uint8 *)(ea))[0] & 0x01) == 0) + #include <packed_section_end.h> diff --git a/drivers/net/wireless/bcmdhd/include/proto/p2p.h b/drivers/net/wireless/bcmdhd/include/proto/p2p.h index 2b6fef6..8f7652f 100644 --- a/drivers/net/wireless/bcmdhd/include/proto/p2p.h +++ b/drivers/net/wireless/bcmdhd/include/proto/p2p.h @@ -21,7 +21,7 @@ * * Fundamental types and constants relating to WFA P2P (aka WiFi Direct) * - * $Id: p2p.h 357863 2012-09-20 06:40:47Z $ + * $Id: p2p.h 356416 2012-09-12 16:40:42Z $ */ #ifndef _P2P_H_ @@ -376,7 +376,8 @@ typedef struct wifi_p2p_pub_act_frame wifi_p2p_pub_act_frame_t; #define P2P_PAF_DEVDIS_RSP 6 #define P2P_PAF_PROVDIS_REQ 7 #define P2P_PAF_PROVDIS_RSP 8 -#define P2P_PAF_SUBTYPE_INVALID 255 /* Invalid Subtype */ +#define P2P_PAF_SUBTYPE_INVALID 255 + #define P2P_TYPE_MNREQ P2P_PAF_GON_REQ #define P2P_TYPE_MNRSP P2P_PAF_GON_RSP diff --git a/drivers/net/wireless/bcmdhd/include/proto/vlan.h b/drivers/net/wireless/bcmdhd/include/proto/vlan.h index 9c94985..2eb4832 100644 --- a/drivers/net/wireless/bcmdhd/include/proto/vlan.h +++ b/drivers/net/wireless/bcmdhd/include/proto/vlan.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: vlan.h 241182 2011-02-17 21:50:03Z $ + * $Id: vlan.h 346935 2012-07-25 00:24:55Z $ */ #ifndef _vlan_h_ @@ -40,11 +40,19 @@ #define VLAN_PRI_MASK 7 +#define VLAN_TPID_OFFSET 12 +#define VLAN_TCI_OFFSET 14 + #define VLAN_TAG_LEN 4 #define VLAN_TAG_OFFSET (2 * ETHER_ADDR_LEN) #define VLAN_TPID 0x8100 +struct vlan_header { + uint16 vlan_type; + uint16 vlan_tag; +}; + struct ethervlan_header { uint8 ether_dhost[ETHER_ADDR_LEN]; uint8 ether_shost[ETHER_ADDR_LEN]; diff --git a/drivers/net/wireless/bcmdhd/include/proto/wpa.h b/drivers/net/wireless/bcmdhd/include/proto/wpa.h index 47bc354..7ebeeda 100644 --- a/drivers/net/wireless/bcmdhd/include/proto/wpa.h +++ b/drivers/net/wireless/bcmdhd/include/proto/wpa.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: wpa.h 261155 2011-05-23 23:51:32Z $ + * $Id: wpa.h 369547 2012-11-19 08:57:31Z $ */ #ifndef _proto_wpa_h_ @@ -34,7 +34,11 @@ #include <packed_section_start.h> +#ifdef CUSTOMER_HW4 #include <dhd_sec_feature.h> +#endif + + #define DOT11_RC_INVALID_WPA_IE 13 @@ -116,9 +120,9 @@ typedef BWL_PRE_PACKED_STRUCT struct #define WPA_CIPHER_BIP 6 #define WPA_CIPHER_TPK 7 #ifdef BCMCCX -#define WPA_CIPHER_CKIP 8 -#define WPA_CIPHER_CKIP_MMH 9 -#define WPA_CIPHER_WEP_MMH 10 +#define WPA_CIPHER_CKIP 8 +#define WPA_CIPHER_CKIP_MMH 9 +#define WPA_CIPHER_WEP_MMH 10 #define IS_CCX_CIPHER(cipher) ((cipher) == WPA_CIPHER_CKIP || \ (cipher) == WPA_CIPHER_CKIP_MMH || \ @@ -170,10 +174,8 @@ typedef BWL_PRE_PACKED_STRUCT struct #define RSN_CAP_2_REPLAY_CNTRS 1 #define RSN_CAP_4_REPLAY_CNTRS 2 #define RSN_CAP_16_REPLAY_CNTRS 3 -#ifdef MFP #define RSN_CAP_MFPR 0x0040 #define RSN_CAP_MFPC 0x0080 -#endif #define WPA_CAP_4_REPLAY_CNTRS RSN_CAP_4_REPLAY_CNTRS diff --git a/drivers/net/wireless/bcmdhd/include/sbchipc.h b/drivers/net/wireless/bcmdhd/include/sbchipc.h index 5feb743..463c8af 100644 --- a/drivers/net/wireless/bcmdhd/include/sbchipc.h +++ b/drivers/net/wireless/bcmdhd/include/sbchipc.h @@ -5,7 +5,7 @@ * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer, * GPIO interface, extbus, and support for serial and parallel flashes. * - * $Id: sbchipc.h 347614 2012-07-27 10:24:51Z $ + * $Id: sbchipc.h 368270 2012-11-12 23:46:50Z $ * * Copyright (C) 1999-2012, Broadcom Corporation * @@ -289,10 +289,10 @@ typedef volatile struct { uint32 pllcontrol_data; uint32 pmustrapopt; uint32 pmu_xtalfreq; - uint32 retention_ctl; + uint32 retention_ctl; uint32 PAD[3]; - uint32 retention_grpidx; - uint32 retention_grpctl; + uint32 retention_grpidx; + uint32 retention_grpctl; uint32 PAD[94]; uint16 sromotp[512]; #ifdef NFLASH_SUPPORT @@ -358,16 +358,58 @@ typedef volatile struct { uint32 nand_cache_data; uint32 nand_ctrl_config; uint32 nand_ctrl_status; -#endif - uint32 gci_corecaps0; - uint32 gci_corecaps1; - uint32 gci_corecaps2; - uint32 gci_corectrl; - uint32 gci_corestat; - uint32 PAD[11]; - uint32 gci_indirect_addr; - uint32 PAD[111]; - uint32 gci_chipctrl; +#endif + uint32 gci_corecaps0; + uint32 gci_corecaps1; + uint32 gci_corecaps2; + uint32 gci_corectrl; + uint32 gci_corestat; + uint32 gci_intstat; + uint32 gci_intmask; + uint32 gci_wakemask; + uint32 gci_levelintstat; + uint32 gci_eventintstat; + uint32 PAD[6]; + uint32 gci_indirect_addr; + uint32 gci_gpioctl; + uint32 PAD; + uint32 gci_gpiomask; + uint32 PAD; + uint32 gci_miscctl; + uint32 PAD[2]; + uint32 gci_input[32]; + uint32 gci_event[32]; + uint32 gci_output[4]; + uint32 gci_control_0; + uint32 gci_control_1; + uint32 gci_level_polreg; + uint32 gci_levelintmask; + uint32 gci_eventintmask; + uint32 PAD[3]; + uint32 gci_inbandlevelintmask; + uint32 gci_inbandeventintmask; + uint32 PAD[2]; + uint32 gci_seciauxtx; + uint32 gci_seciauxrx; + uint32 gci_secitx_datatag; + uint32 gci_secirx_datatag; + uint32 gci_secitx_datamask; + uint32 gci_seciusef0tx_reg; + uint32 gci_secif0tx_offset; + uint32 gci_secif0rx_offset; + uint32 gci_secif1tx_offset; + uint32 PAD[3]; + uint32 gci_uartescval; + uint32 PAD[3]; + uint32 gci_secibauddiv; + uint32 gci_secifcr; + uint32 gci_secilcr; + uint32 gci_secimcr; + uint32 PAD[2]; + uint32 gci_baudadj; + uint32 PAD; + uint32 gci_chipctrl; + uint32 gci_chipsts; } chipcregs_t; #endif @@ -473,9 +515,12 @@ typedef volatile struct { #define CC_CAP2_GSIO 0x00000002 -#define CC_CAP_EXT_SECI_PRESENT 0x00000001 +#define CC_CAP_EXT_SECI_PRESENT 0x00000001 +#define CC_CAP_EXT_GCI_PRESENT 0x00000004 +#define GCI_WL_CHN_INFO_MASK (0xFF00) + #define PLL_NONE 0x00000000 #define PLL_TYPE1 0x00010000 #define PLL_TYPE2 0x00020000 @@ -491,6 +536,28 @@ typedef volatile struct { #define ALP_CLOCK 20000000 +#ifdef CFG_SIM +#define NS_ALP_CLOCK 84922 +#define NS_SLOW_ALP_CLOCK 84922 +#define NS_CPU_CLOCK 534500 +#define NS_SLOW_CPU_CLOCK 534500 +#define NS_SI_CLOCK 271750 +#define NS_SLOW_SI_CLOCK 271750 +#define NS_FAST_MEM_CLOCK 271750 +#define NS_MEM_CLOCK 271750 +#define NS_SLOW_MEM_CLOCK 271750 +#else +#define NS_ALP_CLOCK 125000000 +#define NS_SLOW_ALP_CLOCK 100000000 +#define NS_CPU_CLOCK 1000000000 +#define NS_SLOW_CPU_CLOCK 800000000 +#define NS_SI_CLOCK 250000000 +#define NS_SLOW_SI_CLOCK 200000000 +#define NS_FAST_MEM_CLOCK 800000000 +#define NS_MEM_CLOCK 533000000 +#define NS_SLOW_MEM_CLOCK 400000000 +#endif + #define HT_CLOCK 80000000 @@ -808,6 +875,33 @@ typedef volatile struct { #define PCTL_LPO_SEL 0x00000001 +#define PMU_RCTL_CLK_DIV_SHIFT 0 +#define PMU_RCTL_CHAIN_LEN_SHIFT 12 +#define PMU_RCTL_MACPHY_DISABLE_SHIFT 26 +#define PMU_RCTL_MACPHY_DISABLE_MASK (1 << 26) +#define PMU_RCTL_LOGIC_DISABLE_SHIFT 27 +#define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27) +#define PMU_RCTL_MEMSLP_LOG_SHIFT 28 +#define PMU_RCTL_MEMSLP_LOG_MASK (1 << 28) +#define PMU_RCTL_MEMRETSLP_LOG_SHIFT 29 +#define PMU_RCTL_MEMRETSLP_LOG_MASK (1 << 29) + + +#define PMU_RCTLGRP_CHAIN_LEN_SHIFT 0 +#define PMU_RCTLGRP_RMODE_ENABLE_SHIFT 14 +#define PMU_RCTLGRP_RMODE_ENABLE_MASK (1 << 14) +#define PMU_RCTLGRP_DFT_ENABLE_SHIFT 15 +#define PMU_RCTLGRP_DFT_ENABLE_MASK (1 << 15) +#define PMU_RCTLGRP_NSRST_DISABLE_SHIFT 16 +#define PMU_RCTLGRP_NSRST_DISABLE_MASK (1 << 16) + +#define PMU4334_RCTLGRP_CHAIN_LEN_GRP0 338 +#define PMU4334_RCTLGRP_CHAIN_LEN_GRP1 315 + +#define PMU43341_RCTLGRP_CHAIN_LEN_GRP0 366 +#define PMU43341_RCTLGRP_CHAIN_LEN_GRP1 330 + + #define CSTRETCH_HT 0xffff0000 #define CSTRETCH_ALP 0x0000ffff @@ -874,6 +968,8 @@ typedef volatile struct { #define SFLASH_AT 0x200 #define NFLASH 0x300 #define PFLASH 0x700 +#define QSPIFLASH_ST 0x800 +#define QSPIFLASH_AT 0x900 #define CC_CFG_EN 0x0001 @@ -1726,9 +1822,36 @@ typedef volatile struct { #define CST43239_CHIPMODE_GSPI(cs) (((cs) & (1 << 0)) == (1 << 0)) -#define RES4324_OTP_PU 10 + +#define RES4324_LPLDO_PU 0 +#define RES4324_RESET_PULLDN_DIS 1 +#define RES4324_PMU_BG_PU 2 +#define RES4324_HSIC_LDO_PU 3 +#define RES4324_CBUCK_LPOM_PU 4 +#define RES4324_CBUCK_PFM_PU 5 +#define RES4324_CLDO_PU 6 +#define RES4324_LPLDO2_LVM 7 +#define RES4324_LNLDO1_PU 8 +#define RES4324_LNLDO2_PU 9 +#define RES4324_LDO3P3_PU 10 +#define RES4324_OTP_PU 11 +#define RES4324_XTAL_PU 12 +#define RES4324_BBPLL_PU 13 +#define RES4324_LQ_AVAIL 14 +#define RES4324_WL_CORE_READY 17 +#define RES4324_ILP_REQ 18 +#define RES4324_ALP_AVAIL 19 +#define RES4324_PALDO_PU 20 +#define RES4324_RADIO_PU 21 +#define RES4324_SR_CLK_STABLE 22 +#define RES4324_SR_SAVE_RESTORE 23 +#define RES4324_SR_PHY_PWRSW 24 +#define RES4324_SR_PHY_PIC 25 +#define RES4324_SR_SUBCORE_PWRSW 26 +#define RES4324_SR_SUBCORE_PIC 27 +#define RES4324_SR_MEM_PM0 28 #define RES4324_HT_AVAIL 29 -#define RES4324_MACPHY_CLKAVAIL 30 +#define RES4324_MACPHY_CLKAVAIL 30 #define CST4324_SPROM_MASK 0x00000080 @@ -1740,6 +1863,9 @@ typedef volatile struct { #define CST4324_CHIPMODE_USB20D(cs) (((cs) & CST4324_CHIPMODE_MASK) == 0x6) +#define CST43242_SFLASH_MASK 0x00000008 + + #define RES4331_REGULATOR 0 #define RES4331_ILP_REQUEST 1 #define RES4331_XTAL_PU 2 @@ -1974,6 +2100,42 @@ typedef volatile struct { #define PMU_VREG0_DISABLE_PULLD_BT_SHIFT 2 #define PMU_VREG0_DISABLE_PULLD_WL_SHIFT 3 +#define PMU_VREG4_ADDR 4 + +#define PMU_VREG4_CLDO_PWM_SHIFT 4 +#define PMU_VREG4_CLDO_PWM_MASK 0x7 + +#define PMU_VREG4_LPLDO1_SHIFT 15 +#define PMU_VREG4_LPLDO1_MASK 0x7 +#define PMU_VREG4_LPLDO1_1p20V 0 +#define PMU_VREG4_LPLDO1_1p15V 1 +#define PMU_VREG4_LPLDO1_1p10V 2 +#define PMU_VREG4_LPLDO1_1p25V 3 +#define PMU_VREG4_LPLDO1_1p05V 4 +#define PMU_VREG4_LPLDO1_1p00V 5 +#define PMU_VREG4_LPLDO1_0p95V 6 +#define PMU_VREG4_LPLDO1_0p90V 7 + +#define PMU_VREG4_LPLDO2_LVM_SHIFT 18 +#define PMU_VREG4_LPLDO2_LVM_MASK 0x7 +#define PMU_VREG4_LPLDO2_HVM_SHIFT 21 +#define PMU_VREG4_LPLDO2_HVM_MASK 0x7 +#define PMU_VREG4_LPLDO2_LVM_HVM_MASK 0x3f +#define PMU_VREG4_LPLDO2_1p00V 0 +#define PMU_VREG4_LPLDO2_1p15V 1 +#define PMU_VREG4_LPLDO2_1p20V 2 +#define PMU_VREG4_LPLDO2_1p10V 3 +#define PMU_VREG4_LPLDO2_0p90V 4 + +#define PMU_VREG4_HSICLDO_BYPASS_SHIFT 27 +#define PMU_VREG4_HSICLDO_BYPASS_MASK 0x1 + +#define PMU_VREG5_ADDR 5 +#define PMU_VREG5_HSICAVDD_PD_SHIFT 6 +#define PMU_VREG5_HSICAVDD_PD_MASK 0x1 +#define PMU_VREG5_HSICDVDD_PD_SHIFT 11 +#define PMU_VREG5_HSICDVDD_PD_MASK 0x1 + #define RES4334_LPLDO_PU 0 #define RES4334_RESET_PULLDN_DIS 1 @@ -2029,14 +2191,80 @@ typedef volatile struct { #define PCTL_4334_GPIO3_ENAB (1 << 3) +#define CCTRL4334_PMU_WAKEUP_GPIO1 (1 << 0) +#define CCTRL4334_PMU_WAKEUP_HSIC (1 << 1) +#define CCTRL4334_PMU_WAKEUP_AOS (1 << 2) +#define CCTRL4334_HSIC_WAKE_MODE (1 << 3) +#define CCTRL4334_HSIC_INBAND_GPIO1 (1 << 4) #define CCTRL4334_HSIC_LDO_PU (1 << 23) +#define CCTRL4334_BLOCK_EXTRNL_WAKE (1 << 4) +#define CCTRL4334_SAVERESTORE_FIX (1 << 5) + + +#define CCTRL43341_BLOCK_EXTRNL_WAKE (1 << 13) +#define CCTRL43341_SAVERESTORE_FIX (1 << 14) +#define CCTRL43341_BT_ISO_SEL (1 << 16) + + +#define CCTRL1_4334_GPIO_SEL (1 << 0) +#define CCTRL1_4334_ERCX_SEL (1 << 1) +#define CCTRL1_4334_SDIO_HOST_WAKE (1 << 2) +#define CCTRL1_4334_JTAG_DISABLE (1 << 3) +#define CCTRL1_4334_UART_ON_4_5 (1 << 28) + + #define CCTRL1_4324_GPIO_SEL (1 << 0) #define CCTRL1_4324_SDIO_HOST_WAKE (1 << 2) +#define CST43143_REMAP_TO_ROM (3 << 0) +#define CST43143_SDIO_EN (1 << 2) +#define CST43143_SDIO_ISO (1 << 3) +#define CST43143_USB_CPU_LESS (1 << 4) +#define CST43143_CBUCK_MODE (3 << 6) +#define CST43143_POK_CBUCK (1 << 8) +#define CST43143_PMU_OVRSPIKE (1 << 9) +#define CST43143_PMU_OVRTEMP (0xF << 10) +#define CST43143_SR_FLL_CAL_DONE (1 << 14) +#define CST43143_USB_PLL_LOCKDET (1 << 15) +#define CST43143_PMU_PLL_LOCKDET (1 << 16) +#define CST43143_CHIPMODE_SDIOD(cs) (((cs) & CST43143_SDIO_EN) != 0) + + + +#define CCTRL_43143_SECI (1<<0) +#define CCTRL_43143_BT_LEGACY (1<<1) +#define CCTRL_43143_I2S_MODE (1<<2) +#define CCTRL_43143_I2S_MASTER (1<<3) +#define CCTRL_43143_I2S_FULL (1<<4) +#define CCTRL_43143_GSIO (1<<5) +#define CCTRL_43143_RF_SWCTRL_MASK (7<<6) +#define CCTRL_43143_RF_SWCTRL_0 (1<<6) +#define CCTRL_43143_RF_SWCTRL_1 (2<<6) +#define CCTRL_43143_RF_SWCTRL_2 (4<<6) +#define CCTRL_43143_RF_XSWCTRL (1<<9) +#define CCTRL_43143_HOST_WAKE0 (1<<11) +#define CCTRL_43143_HOST_WAKE1 (1<<12) + + +#define RES43143_EXT_SWITCHER_PWM 0 +#define RES43143_XTAL_PU 1 +#define RES43143_ILP_REQUEST 2 +#define RES43143_ALP_AVAIL 3 +#define RES43143_WL_CORE_READY 4 +#define RES43143_BBPLL_PWRSW_PU 5 +#define RES43143_HT_AVAIL 6 +#define RES43143_RADIO_PU 7 +#define RES43143_MACPHY_CLK_AVAIL 8 +#define RES43143_OTP_PU 9 +#define RES43143_LQ_AVAIL 10 + +#define PMU43143_XTAL_CORE_SIZE_MASK 0x3F + + #define RES4313_BB_PU_RSRC 0 #define RES4313_ILP_REQ_RSRC 1 #define RES4313_XTAL_PU_RSRC 2 @@ -2137,11 +2365,19 @@ typedef volatile struct { #define FLSTRCF4706_1ST_MADDR_SEG_256MB 0x00000070 +#define CCTRL4360_I2C_MODE (1 << 0) +#define CCTRL4360_UART_MODE (1 << 1) #define CCTRL4360_SECI_MODE (1 << 2) #define CCTRL4360_BTSWCTRL_MODE (1 << 3) +#define CCTRL4360_DISCRETE_FEMCTRL_MODE (1 << 4) +#define CCTRL4360_DIGITAL_PACTRL_MODE (1 << 5) +#define CCTRL4360_BTSWCTRL_AND_DIGPA_PRESENT (1 << 6) +#define CCTRL4360_EXTRA_GPIO_MODE (1 << 7) #define CCTRL4360_EXTRA_FEMCTRL_MODE (1 << 8) #define CCTRL4360_BT_LGCY_MODE (1 << 9) #define CCTRL4360_CORE2FEMCTRL4_ON (1 << 21) +#define CCTRL4360_SECI_ON_GPIO01 (1 << 24) + #define RES4360_REGULATOR 0 @@ -2211,19 +2447,144 @@ typedef volatile struct { #define CST4335_RES_INIT_MODE_SHIFT 7 #define CST4335_RES_INIT_MODE_MASK 0x00000180 #define CST4335_CHIPMODE_MASK 0xF -#define CST4335_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) -#define CST4335_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) -#define CST4335_CHIPMODE_USB20D(cs) (((cs) & (1 << 2)) != 0) -#define CST4335_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) - - -#define CCTRL1_4335_GPIO_SEL (1 << 0) -#define CCTRL1_4335_SDIO_HOST_WAKE (1 << 2) - - -#define CR4_RAM_BASE (0x180000) - - +#define CST4335_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) +#define CST4335_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) +#define CST4335_CHIPMODE_USB20D(cs) (((cs) & (1 << 2)) != 0) +#define CST4335_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) + + +#define CCTRL1_4335_GPIO_SEL (1 << 0) +#define CCTRL1_4335_SDIO_HOST_WAKE (1 << 2) + +#define CR4_4335_RAM_BASE (0x180000) +#define CR4_4350_RAM_BASE (0x180000) +#define CR4_4360_RAM_BASE (0x0) + + + + + +#define CST4350_SDIO_MODE 0x00000001 +#define CST4350_HSIC20D_MODE 0x00000002 +#define CST4350_BP_ON_HSIC_CLK 0x00000004 +#define CST4350_PCIE_MODE 0x00000008 +#define CST4350_USB20D_MODE 0x00000010 +#define CST4350_USB30D_MODE 0x00000020 +#define CST4350_SPROM_PRESENT 0x00000040 +#define CST4350_RSRC_INIT_MODE_0 0x00000080 +#define CST4350_RSRC_INIT_MODE_1 0x00000100 +#define CST4350_SEL0_SDIO 0x00000200 +#define CST4350_SEL1_SDIO 0x00000400 +#define CST4350_SDIO_PAD_MODE 0x00000800 +#define CST4350_BBPLL_LOCKED 0x00001000 +#define CST4350_USBPLL_LOCKED 0x00002000 +#define CST4350_LINE_STATE 0x0000C000 +#define CST4350_SERDES_PIPE_PLLLOCK 0x00010000 +#define CST4350_BT_READY 0x00020000 +#define CST4350_SFLASH_PRESENT 0x00040000 +#define CST4350_CPULESS_ENABLE 0x00080000 +#define CST4350_STRAP_HOST_IFC_1 0x00100000 +#define CST4350_STRAP_HOST_IFC_2 0x00200000 +#define CST4350_STRAP_HOST_IFC_3 0x00400000 +#define CST4350_RAW_SPROM_PRESENT 0x00800000 +#define CST4350_APP_CLK_SWITCH_SEL_RDBACK 0x01000000 +#define CST4350_RAW_RSRC_INIT_MODE_0 0x02000000 +#define CST4350_SDIO_PAD_VDDIO 0x04000000 +#define CST4350_GSPI_MODE 0x08000000 +#define CST4350_PACKAGE_OPTION 0xF0000000 + + +#define CST4350_HOST_IFC_MASK 0x00700000 +#define CST4350_HOST_IFC_SHIFT 20 + + +#define CST4350_IFC_MODE_SDIOD 0x0 +#define CST4350_IFC_MODE_HSIC20D 0x1 +#define CST4350_IFC_MODE_HSIC30D 0x2 +#define CST4350_IFC_MODE_PCIE 0x3 +#define CST4350_IFC_MODE_USB20D 0x4 +#define CST4350_IFC_MODE_USB30D 0x5 +#define CST4350_IFC_MODE_USB30D_WL 0x6 +#define CST4350_IFC_MODE_USB30D_BT 0x7 + +#define CST4350_IFC_MODE(cs) ((cs & CST4350_HOST_IFC_MASK) >> CST4350_HOST_IFC_SHIFT) + +#define CST4350_CHIPMODE_SDIOD(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_SDIOD)) +#define CST4350_CHIPMODE_USB20D(cs) ((CST4350_IFC_MODE(cs)) == (CST4350_IFC_MODE_USB20D)) +#define CST4350_CHIPMODE_HSIC20D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC20D)) +#define CST4350_CHIPMODE_HSIC30D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC30D)) +#define CST4350_CHIPMODE_USB30D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D)) +#define CST4350_CHIPMODE_USB30D_WL(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D_WL)) + + +#define RES4350_LPLDO_PU 0 +#define RES4350_PMU_BG_PU 1 +#define RES4350_PMU_SLEEP 2 +#define RES4350_RSVD_3 3 +#define RES4350_CBUCK_LPOM_PU 4 +#define RES4350_CBUCK_PFM_PU 5 +#define RES4350_COLD_START_WAIT 6 +#define RES4350_RSVD_7 7 +#define RES4350_LNLDO_PU 8 +#define RES4350_XTALLDO_PU 9 +#define RES4350_LDO3P3_PU 10 +#define RES4350_OTP_PU 11 +#define RES4350_XTAL_PU 12 +#define RES4350_SR_CLK_START 13 +#define RES4350_LQ_AVAIL 14 +#define RES4350_LQ_START 15 +#define RES4350_RSVD_16 16 +#define RES4350_WL_CORE_RDY 17 +#define RES4350_ILP_REQ 18 +#define RES4350_ALP_AVAIL 19 +#define RES4350_MINI_PMU 20 +#define RES4350_RADIO_PU 21 +#define RES4350_SR_CLK_STABLE 22 +#define RES4350_SR_SAVE_RESTORE 23 +#define RES4350_SR_PHY_PWRSW 24 +#define RES4350_SR_VDDM_PWRSW 25 +#define RES4350_SR_SUBCORE_PWRSW 26 +#define RES4350_SR_SLEEP 27 +#define RES4350_HT_START 28 +#define RES4350_HT_AVAIL 29 +#define RES4350_MACPHY_CLKAVAIL 30 + +#define MUXENAB4350_UART_MASK (0x0000000f) + + +#define CC4350_FNSEL_HWDEF (0) +#define CC4350_FNSEL_SAMEASPIN (1) +#define CC4350_FNSEL_UART (2) +#define CC4350_FNSEL_SFLASH (3) +#define CC4350_FNSEL_SPROM (4) +#define CC4350_FNSEL_I2C (5) +#define CC4350_FNSEL_MISC0 (6) +#define CC4350_FNSEL_GCI (7) +#define CC4350_FNSEL_MISC1 (8) +#define CC4350_FNSEL_MISC2 (9) +#define CC4350_FNSEL_PWDOG (10) +#define CC4350_FNSEL_IND (12) +#define CC4350_FNSEL_PDN (13) +#define CC4350_FNSEL_PUP (14) +#define CC4350_FNSEL_TRISTATE (15) + + +#define CC4350_PIN_GPIO_00 (0) +#define CC4350_PIN_GPIO_01 (1) +#define CC4350_PIN_GPIO_02 (2) +#define CC4350_PIN_GPIO_03 (3) +#define CC4350_PIN_GPIO_04 (4) +#define CC4350_PIN_GPIO_05 (5) +#define CC4350_PIN_GPIO_06 (6) +#define CC4350_PIN_GPIO_07 (7) +#define CC4350_PIN_GPIO_08 (8) +#define CC4350_PIN_GPIO_09 (9) +#define CC4350_PIN_GPIO_10 (10) +#define CC4350_PIN_GPIO_11 (11) +#define CC4350_PIN_GPIO_12 (12) +#define CC4350_PIN_GPIO_13 (13) +#define CC4350_PIN_GPIO_14 (14) +#define CC4350_PIN_GPIO_15 (15) #define CC_GCI_CHIPCTRL_00 (0) diff --git a/drivers/net/wireless/bcmdhd/include/sbhnddma.h b/drivers/net/wireless/bcmdhd/include/sbhnddma.h index da1f1a1..0b44602 100644 --- a/drivers/net/wireless/bcmdhd/include/sbhnddma.h +++ b/drivers/net/wireless/bcmdhd/include/sbhnddma.h @@ -22,7 +22,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: sbhnddma.h 309193 2012-01-19 00:03:57Z $ + * $Id: sbhnddma.h 348178 2012-07-31 22:27:41Z $ */ #ifndef _sbhnddma_h_ @@ -233,11 +233,17 @@ typedef volatile struct { #define D64RINGALIGN_BITS 13 #define D64MAXRINGSZ (1 << D64RINGALIGN_BITS) -#define D64RINGALIGN (1 << D64RINGALIGN_BITS) +#define D64RINGBOUNDARY (1 << D64RINGALIGN_BITS) #define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t)) +#define D64MAXDD_LARGE ((1 << 16) / sizeof (dma64dd_t)) + + +#define D64RINGBOUNDARY_LARGE (1 << 16) + + #define D64_XC_XE 0x00000001 #define D64_XC_SE 0x00000002 #define D64_XC_LE 0x00000004 @@ -258,7 +264,7 @@ typedef volatile struct { #define D64_XP_LD_MASK 0x00001fff -#define D64_XS0_CD_MASK 0x00001fff +#define D64_XS0_CD_MASK (di->d64_xs0_cd_mask) #define D64_XS0_XS_MASK 0xf0000000 #define D64_XS0_XS_SHIFT 28 #define D64_XS0_XS_DISABLED 0x00000000 @@ -267,7 +273,7 @@ typedef volatile struct { #define D64_XS0_XS_STOPPED 0x30000000 #define D64_XS0_XS_SUSP 0x40000000 -#define D64_XS1_AD_MASK 0x00001fff +#define D64_XS1_AD_MASK (di->d64_xs1_ad_mask) #define D64_XS1_XE_MASK 0xf0000000 #define D64_XS1_XE_SHIFT 28 #define D64_XS1_XE_NOERR 0x00000000 @@ -306,7 +312,7 @@ typedef volatile struct { #define D64_RP_LD_MASK 0x00001fff -#define D64_RS0_CD_MASK 0x00001fff +#define D64_RS0_CD_MASK (di->d64_rs0_cd_mask) #define D64_RS0_RS_MASK 0xf0000000 #define D64_RS0_RS_SHIFT 28 #define D64_RS0_RS_DISABLED 0x00000000 diff --git a/drivers/net/wireless/bcmdhd/include/sbsdio.h b/drivers/net/wireless/bcmdhd/include/sbsdio.h index 0e9ad7d..30a891e 100644 --- a/drivers/net/wireless/bcmdhd/include/sbsdio.h +++ b/drivers/net/wireless/bcmdhd/include/sbsdio.h @@ -24,7 +24,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: sbsdio.h 308945 2012-01-18 02:15:27Z $ + * $Id: sbsdio.h 369545 2012-11-19 08:38:45Z $ */ #ifndef _SBSDIO_H @@ -101,6 +101,7 @@ * => busy signal is asserted between data blocks. */ #define SBSDIO_MESBUSYCTRL_MASK 0x7f +#define SBSDIO_MESBUSYCTRL_ENAB 0x80 /* Enable busy capability for MES access */ /* SBSDIO_DEVICE_CTL */ #define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when @@ -116,12 +117,9 @@ * external pads in tri-state; requires * sdio bus power cycle to clear (rev 9) */ -#define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */ -#define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */ -#define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */ -#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */ #define SBSDIO_DEVCTL_EN_F2_BLK_WATERMARK 0x10 /* Enable function 2 tx for each block */ - +#define SBSDIO_DEVCTL_F2WM_ENAB 0x10 /* Enable F2 Watermark */ +#define SBSDIO_DEVCTL_NONDAT_PADS_ISO 0x20 /* Isolate sdio clk and cmd (non-data) */ /* SBSDIO_FUNC1_CHIPCLKCSR */ #define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */ diff --git a/drivers/net/wireless/bcmdhd/include/sbsdpcmdev.h b/drivers/net/wireless/bcmdhd/include/sbsdpcmdev.h index 10c7401..66ff3fe 100644 --- a/drivers/net/wireless/bcmdhd/include/sbsdpcmdev.h +++ b/drivers/net/wireless/bcmdhd/include/sbsdpcmdev.h @@ -22,7 +22,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: sbsdpcmdev.h 347614 2012-07-27 10:24:51Z $ + * $Id: sbsdpcmdev.h 336848 2012-06-05 11:28:07Z $ */ #ifndef _sbsdpcmdev_h_ diff --git a/drivers/net/wireless/bcmdhd/include/sdioh.h b/drivers/net/wireless/bcmdhd/include/sdioh.h index 5517a71..7597901 100644 --- a/drivers/net/wireless/bcmdhd/include/sdioh.h +++ b/drivers/net/wireless/bcmdhd/include/sdioh.h @@ -22,7 +22,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: sdioh.h 347633 2012-07-27 11:02:02Z $ + * $Id: sdioh.h 345499 2012-07-18 06:59:05Z $ */ #ifndef _SDIOH_H @@ -90,8 +90,8 @@ #define SD3_PresetVal_SDR104 0x06c #define SD3_PresetVal_DDR50 0x06e /* SDIO3.0 Revx specific Registers */ -#define SD3_Tuning_Info_Register 0x0EC -#define SD3_WL_BT_reset_register 0x0F0 +#define SD3_Tuning_Info_Register 0x0EC +#define SD3_WL_BT_reset_register 0x0F0 /* preset value indices */ diff --git a/drivers/net/wireless/bcmdhd/include/siutils.h b/drivers/net/wireless/bcmdhd/include/siutils.h index a797b3d..4a5be1a 100644 --- a/drivers/net/wireless/bcmdhd/include/siutils.h +++ b/drivers/net/wireless/bcmdhd/include/siutils.h @@ -22,7 +22,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: siutils.h 347614 2012-07-27 10:24:51Z $ + * $Id: siutils.h 364853 2012-10-25 18:54:06Z $ */ #ifndef _siutils_h_ @@ -159,6 +159,7 @@ extern void si_setosh(si_t *sih, osl_t *osh); extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); extern void *si_coreregs(si_t *sih); extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val); +extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val); extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val); extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val); @@ -247,6 +248,8 @@ static INLINE void * si_eci_init(si_t *sih) {return NULL;} #define si_seci_upd(sih, a) do {} while (0) static INLINE void * si_seci_init(si_t *sih, uint8 use_seci) {return NULL;} #define si_seci_down(sih) do {} while (0) +#define si_gci(sih) 0 +static INLINE void * si_gci_init(si_t *sih) {return NULL;} extern bool si_is_otp_disabled(si_t *sih); @@ -282,6 +285,8 @@ extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len, const ch extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val); extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val); +extern uint8 si_pcieltrenable(si_t *sih, uint32 mask, uint32 val); +extern void si_pcie_set_error_injection(si_t *sih, uint32 mode); extern void si_war42780_clkreq(si_t *sih, bool clkreq); extern void si_pci_down(si_t *sih); extern void si_pci_up(si_t *sih); @@ -305,6 +310,7 @@ extern void si_btc_enable_chipcontrol(si_t *sih); extern void si_btcombo_p250_4313_war(si_t *sih); extern void si_btcombo_43228_war(si_t *sih); extern void si_clk_pmu_htavail_set(si_t *sih, bool set_clear); +extern void si_pmu_synth_pwrsw_4313_war(si_t *sih); extern uint si_pll_reset(si_t *sih); @@ -316,6 +322,8 @@ extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val); extern void si_pcie_set_request_size(si_t *sih, uint16 size); extern uint16 si_pcie_get_request_size(si_t *sih); +extern void si_pcie_set_maxpayload_size(si_t *sih, uint16 size); +extern uint16 si_pcie_get_maxpayload_size(si_t *sih); extern uint16 si_pcie_get_ssid(si_t *sih); extern uint32 si_pcie_get_bar0(si_t *sih); extern int si_pcie_configspace_cache(si_t *sih); @@ -329,4 +337,11 @@ extern uint32 si_tcm_size(si_t *sih); extern int si_set_sromctl(si_t *sih, uint32 value); extern uint32 si_get_sromctl(si_t *sih); + +extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val); +extern void si_gci_reset(si_t *sih); +extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel); +extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos); +extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val); + #endif diff --git a/drivers/net/wireless/bcmdhd/include/spid.h b/drivers/net/wireless/bcmdhd/include/spid.h index 6d2d403..bfe24ff 100644 --- a/drivers/net/wireless/bcmdhd/include/spid.h +++ b/drivers/net/wireless/bcmdhd/include/spid.h @@ -8,7 +8,7 @@ * under the terms of the GNU General Public License version 2 (the "GPL"), * available at http://www.broadcom.com/licenses/GPLv2.php, with the * following added to such license: - * + * * As a special exception, the copyright holders of this software give you * permission to link this software with independent modules, and to copy and * distribute the resulting executable under terms of your choice, provided that @@ -16,12 +16,12 @@ * the license of that module. An independent module is a module which is not * derived from this software. The special exception does not apply to any * modifications of the software. - * + * * Notwithstanding the above, under no circumstances may you combine this * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: spid.h 354172 2012-08-30 07:19:26Z $ + * $Id: spid.h 358377 2012-09-23 11:30:22Z $ */ #ifndef _SPI_H diff --git a/drivers/net/wireless/bcmdhd/include/trxhdr.h b/drivers/net/wireless/bcmdhd/include/trxhdr.h index bf92a56..da4763c 100644 --- a/drivers/net/wireless/bcmdhd/include/trxhdr.h +++ b/drivers/net/wireless/bcmdhd/include/trxhdr.h @@ -21,7 +21,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: trxhdr.h 260898 2011-05-20 23:11:12Z $ + * $Id: trxhdr.h 349211 2012-08-07 09:45:24Z $ */ #ifndef _TRX_HDR_H @@ -30,23 +30,62 @@ #include <typedefs.h> #define TRX_MAGIC 0x30524448 /* "HDR0" */ -#define TRX_VERSION 1 /* Version 1 */ #define TRX_MAX_LEN 0x3B0000 /* Max length */ #define TRX_NO_HEADER 1 /* Do not write TRX header */ #define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */ #define TRX_EMBED_UCODE 0x8 /* Trx contains embedded ucode image */ #define TRX_ROMSIM_IMAGE 0x10 /* Trx contains ROM simulation image */ #define TRX_UNCOMP_IMAGE 0x20 /* Trx contains uncompressed rtecdc.bin image */ -#define TRX_MAX_OFFSET 3 /* Max number of individual files */ +#define TRX_BOOTLOADER 0x40 /* the image is a bootloader */ +#define TRX_V1 1 +#define TRX_V1_MAX_OFFSETS 3 /* V1: Max number of individual files */ + +#ifndef BCMTRXV2 +#define TRX_VERSION TRX_V1 /* Version 1 */ +#define TRX_MAX_OFFSET TRX_V1_MAX_OFFSETS +#endif + +/* BMAC Host driver/application like bcmdl need to support both Ver 1 as well as + * Ver 2 of trx header. To make it generic, trx_header is structure is modified + * as below where size of "offsets" field will vary as per the TRX version. + * Currently, BMAC host driver and bcmdl are modified to support TRXV2 as well. + * To make sure, other applications like "dhdl" which are yet to be enhanced to support + * TRXV2 are not broken, new macro and structure defintion take effect only when BCMTRXV2 + * is defined. + */ struct trx_header { uint32 magic; /* "HDR0" */ uint32 len; /* Length of file including header */ uint32 crc32; /* 32-bit CRC from flag_version to end of file */ uint32 flag_version; /* 0:15 flags, 16:31 version */ +#ifndef BCMTRXV2 uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ +#else + uint32 offsets[1]; /* Offsets of partitions from start of header */ +#endif }; +#ifdef BCMTRXV2 +#define TRX_VERSION TRX_V2 /* Version 2 */ +#define TRX_MAX_OFFSET TRX_V2_MAX_OFFSETS + +#define TRX_V2 2 +/* V2: Max number of individual files + * To support SDR signature + Config data region + */ +#define TRX_V2_MAX_OFFSETS 5 +#define SIZEOF_TRXHDR_V1 (sizeof(struct trx_header)+(TRX_V1_MAX_OFFSETS-1)*sizeof(uint32)) +#define SIZEOF_TRXHDR_V2 (sizeof(struct trx_header)+(TRX_V2_MAX_OFFSETS-1)*sizeof(uint32)) +#define TRX_VER(trx) (trx->flag_version>>16) +#define ISTRX_V1(trx) (TRX_VER(trx) == TRX_V1) +#define ISTRX_V2(trx) (TRX_VER(trx) == TRX_V2) +/* For V2, return size of V2 size: others, return V1 size */ +#define SIZEOF_TRX(trx) (ISTRX_V2(trx) ? SIZEOF_TRXHDR_V2: SIZEOF_TRXHDR_V1) +#else +#define SIZEOF_TRX(trx) (sizeof(struct trx_header)) +#endif /* BCMTRXV2 */ + /* Compatibility */ typedef struct trx_header TRXHDR, *PTRXHDR; diff --git a/drivers/net/wireless/bcmdhd/include/wlfc_proto.h b/drivers/net/wireless/bcmdhd/include/wlfc_proto.h index 1c8cc01..dfa8db0 100644 --- a/drivers/net/wireless/bcmdhd/include/wlfc_proto.h +++ b/drivers/net/wireless/bcmdhd/include/wlfc_proto.h @@ -18,7 +18,7 @@ * Notwithstanding the above, under no circumstances may you combine this * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. -* $Id: wlfc_proto.h 347585 2012-07-27 09:02:53Z $ +* $Id: wlfc_proto.h 358262 2012-09-21 21:39:29Z $ * */ #ifndef __wlfc_proto_definitions_h__ @@ -62,12 +62,6 @@ | 13 | 3 | (count, handle, prec_bmp)| One time request for packet to a specific | | | | MAC destination. --------------------------------------------------------------------------- - | 15 | 1 | interface ID | NIC period start - --------------------------------------------------------------------------- - | 16 | 1 | interface ID | NIC period end - --------------------------------------------------------------------------- - | 17 | 3 | (ifid, txs) | Action frame tx status - --------------------------------------------------------------------------- | 255 | N/A | N/A | FILLER - This is a special type | | | | that has no length or value. | | | | Typically used for padding. @@ -82,7 +76,7 @@ #define WLFC_CTL_TYPE_MACDESC_ADD 6 #define WLFC_CTL_TYPE_MACDESC_DEL 7 -#define WLFC_CTL_TYPE_RSSI 8 +#define WLFC_CTL_TYPE_RSSI 8 #define WLFC_CTL_TYPE_INTERFACE_OPEN 9 #define WLFC_CTL_TYPE_INTERFACE_CLOSE 10 @@ -93,10 +87,9 @@ #define WLFC_CTL_TYPE_MAC_REQUEST_PACKET 13 #define WLFC_CTL_TYPE_HOST_REORDER_RXPKTS 14 -#define WLFC_CTL_TYPE_NIC_PRD_START 15 -#define WLFC_CTL_TYPE_NIC_PRD_END 16 -#define WLFC_CTL_TYPE_AF_TXS 17 -#define WLFC_CTL_TYPE_TRANS_ID 18 +#define WLFC_CTL_TYPE_TRANS_ID 18 +#define WLFC_CTL_TYPE_COMP_TXSTATUS 19 + #define WLFC_CTL_TYPE_FILLER 255 @@ -117,10 +110,6 @@ #define WLFC_CTL_VALUE_LEN_REQUEST_CREDIT 3 /* credit, MAC-handle, prec_bitmap */ #define WLFC_CTL_VALUE_LEN_REQUEST_PACKET 3 /* credit, MAC-handle, prec_bitmap */ -#define WLFC_CTL_VALUE_LEN_NIC_PRD_START 1 -#define WLFC_CTL_VALUE_LEN_NIC_PRD_END 1 -#define WLFC_CTL_VALUE_LEN_AF_TXS 3 - #define WLFC_PKTID_GEN_MASK 0x80000000 #define WLFC_PKTID_GEN_SHIFT 31 @@ -226,7 +215,8 @@ #define WLHOST_REORDERDATA_CURIDX_VALID 0x04 #define WLHOST_REORDERDATA_EXPIDX_VALID 0x08 #define WLHOST_REORDERDATA_NEW_HOLE 0x10 + /* transaction id data len byte 0: rsvd, byte 1: seqnumber, byte 2-5 will be used for timestampe */ -#define WLFC_CTL_TRANS_ID_LEN 6 +#define WLFC_CTL_TRANS_ID_LEN 6 #endif /* __wlfc_proto_definitions_h__ */ diff --git a/drivers/net/wireless/bcmdhd/include/wlioctl.h b/drivers/net/wireless/bcmdhd/include/wlioctl.h index 33811a1..09ba05c 100644 --- a/drivers/net/wireless/bcmdhd/include/wlioctl.h +++ b/drivers/net/wireless/bcmdhd/include/wlioctl.h @@ -24,7 +24,7 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: wlioctl.h 357627 2012-09-19 12:42:22Z $ + * $Id: wlioctl.h 384900 2013-02-13 14:23:02Z $ */ #ifndef _wlioctl_h_ @@ -43,7 +43,9 @@ #include <bcmcdc.h> #endif /* LINUX_POSTMOGRIFY_REMOVAL */ +#ifdef CUSTOMER_HW4 #include <dhd_sec_feature.h> +#endif /* CUSTOMER_HW4 */ /* LINUX_POSTMOGRIFY_REMOVAL: undefined during compile phase, so its * a no-op for most cases. For hybrid and other open source releases, @@ -211,8 +213,8 @@ typedef struct wl_bss_info { uint32 nbss_cap; /* 802.11N+AC BSS Capabilities */ uint8 ctl_ch; /* 802.11N BSS control channel number */ uint8 padding1[3]; /* explicit struct alignment padding */ - uint16 vht_rxmcsmap; /* VHT rx mcs map */ - uint16 vht_txmcsmap; /* VHT tx mcs map */ + uint16 vht_rxmcsmap; /* VHT rx mcs map (802.11ac VHT_CAP_MCS_MAP_*) */ + uint16 vht_txmcsmap; /* VHT tx mcs map (802.11ac VHT_CAP_MCS_MAP_*) */ uint8 flags; /* flags */ uint8 vht_cap; /* BSS is vht capable */ uint8 reserved[2]; /* Reserved for expansion of BSS properties */ @@ -306,7 +308,7 @@ typedef struct wl_clm_dload_info wl_clm_dload_info_t; typedef struct wlc_ssid { uint32 SSID_len; - uchar SSID[32]; + uchar SSID[DOT11_MAX_SSID_LEN]; } wlc_ssid_t; #ifndef LINUX_POSTMOGRIFY_REMOVAL @@ -360,6 +362,7 @@ typedef struct wl_extdscan_params { #define WL_SCANFLAGS_PASSIVE 0x01 /* force passive scan */ #define WL_SCANFLAGS_RESERVED 0x02 /* Reserved */ #define WL_SCANFLAGS_PROHIBITED 0x04 /* allow scanning prohibited channels */ +#define WL_SCANFLAGS_OFFCHAN 0x08 /* allow scanning/reporting off-channel APs */ #define WL_SCAN_PARAMS_SSID_MAX 10 @@ -505,6 +508,7 @@ typedef struct wl_rateset_args { uint32 count; /* # rates in this set */ uint8 rates[WL_MAXRATES_IN_SET]; /* rates in 500kbps units w/hi bit set if basic */ uint8 mcs[MCSSET_LEN]; /* supported mcs index bit map */ + uint16 vht_mcs[VHT_CAP_MCS_MAP_NSS_MAX]; /* supported mcs index bit map per nss */ } wl_rateset_args_t; /* uint32 list */ @@ -518,6 +522,10 @@ typedef struct wl_uint32_list { /* used for association with a specific BSSID and chanspec list */ typedef struct wl_assoc_params { struct ether_addr bssid; /* 00:00:00:00:00:00: broadcast scan */ + uint16 bssid_cnt; /* 0: use chanspec_num, and the single bssid, + * otherwise count of chanspecs in chanspec_list + * AND paired bssids following chanspec_list + */ int32 chanspec_num; /* 0: all available channels, * otherwise count of chanspecs in chanspec_list */ @@ -606,6 +614,7 @@ typedef struct wl_extjoin_params { #define WL_RSPEC_BW_MASK 0x00070000 /* bandwidth mask */ #define WL_RSPEC_BW_SHIFT 16 /* bandwidth shift */ #define WL_RSPEC_STBC 0x00100000 /* STBC encoding, Nsts = 2 x Nss */ +#define WL_RSPEC_TXBF 0x00200000 /* bit indicates TXBF mode */ #define WL_RSPEC_LDPC 0x00400000 /* bit indicates adv coding in use */ #define WL_RSPEC_SGI 0x00800000 /* Short GI mode */ #define WL_RSPEC_ENCODING_MASK 0x03000000 /* Encoding of Rate/MCS field */ @@ -881,18 +890,19 @@ typedef enum sup_auth_status { #define CRYPTO_ALGO_AES_CCM 4 #define CRYPTO_ALGO_AES_OCB_MSDU 5 #define CRYPTO_ALGO_AES_OCB_MPDU 6 -#if !defined(BCMCCX) +#if !defined(BCMCCX) && !defined(BCMEXTCCX) #define CRYPTO_ALGO_NALG 7 #else #define CRYPTO_ALGO_CKIP 7 #define CRYPTO_ALGO_CKIP_MMH 8 #define CRYPTO_ALGO_WEP_MMH 9 #define CRYPTO_ALGO_NALG 10 -#endif +#endif /* !BCMCCX && !BCMEXTCCX */ #ifdef BCMWAPI_WPI #define CRYPTO_ALGO_SMS4 11 #endif /* BCMWAPI_WPI */ #define CRYPTO_ALGO_PMK 12 /* for 802.1x supp to set PMK before 4-way */ +#define CRYPTO_ALGO_BIP 13 /* 802.11w BIP (aes cmac) */ #define WSEC_GEN_MIC_ERROR 0x0001 #define WSEC_GEN_REPLAY 0x0002 @@ -903,13 +913,13 @@ typedef enum sup_auth_status { #define WL_SOFT_KEY (1 << 0) /* Indicates this key is using soft encrypt */ #define WL_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */ -#if defined(BCMCCX) +#if defined(BCMCCX) || defined(BCMEXTCCX) #define WL_CKIP_KP (1 << 4) /* CMIC */ #define WL_CKIP_MMH (1 << 5) /* CKIP */ #else #define WL_KF_RES_4 (1 << 4) /* Reserved for backward compat */ #define WL_KF_RES_5 (1 << 5) /* Reserved for backward compat */ -#endif +#endif /* BCMCCX || BCMEXTCCX */ #define WL_IBSS_PEER_GROUP_KEY (1 << 6) /* Indicates a group key for a IBSS PEER */ typedef struct wl_wsec_key { @@ -990,21 +1000,19 @@ typedef struct { #define WSEC_SMS4_ENABLED(wsec) ((wsec) & SMS4_ENABLED) #endif /* BCMWAPI_WAI */ -#ifdef MFP #define MFP_CAPABLE 0x0200 #define MFP_REQUIRED 0x0400 #define MFP_SHA256 0x0800 /* a special configuration for STA for WIFI test tool */ -#endif /* MFP */ /* WPA authentication mode bitvec */ #define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */ #define WPA_AUTH_NONE 0x0001 /* none (IBSS) */ #define WPA_AUTH_UNSPECIFIED 0x0002 /* over 802.1x */ #define WPA_AUTH_PSK 0x0004 /* Pre-shared key */ -#if defined(BCMCCX) +#if defined(BCMCCX) || defined(BCMEXTCCX) #define WPA_AUTH_CCKM 0x0008 /* CCKM */ #define WPA2_AUTH_CCKM 0x0010 /* CCKM2 */ -#endif +#endif /* BCMCCX || BCMEXTCCX */ /* #define WPA_AUTH_8021X 0x0020 */ /* 802.1x, reserved */ #define WPA2_AUTH_UNSPECIFIED 0x0040 /* over 802.1x */ #define WPA2_AUTH_PSK 0x0080 /* Pre-shared key */ @@ -1022,6 +1030,7 @@ typedef struct { #define WPA_AUTH_PFN_ANY 0xffffffff /* for PFN, match only ssid */ /* pmkid */ +/* Due to pmkid_info driver IOVar/dhd implementation, leave this as 16 for now. */ #define MAXPMKID 16 typedef struct _pmkid { @@ -1119,6 +1128,32 @@ typedef struct wme_tx_params_s wme_tx_params_t; #define WL_WME_TX_PARAMS_IO_BYTES (sizeof(wme_tx_params_t) * AC_COUNT) +typedef struct wl_plc_nodelist { + uint count; /* Number of nodes */ + struct _node { + struct ether_addr ea; /* Node ether address */ + uint32 node_type; /* Node type */ + uint32 cost; /* PLC affinity */ + } node[1]; +} wl_plc_nodelist_t; + +typedef struct wl_plc_params { + uint32 cmd; /* Command */ + bool plc_failover; /* PLC failover control/status */ + struct ether_addr node_ea; /* Node ether address */ + uint32 cost; /* Link cost or mac cost */ +} wl_plc_params_t; + +#define PLC_CMD_FAILOVER 1 +#define PLC_CMD_MAC_COST 2 +#define PLC_CMD_LINK_COST 3 +#define PLC_CMD_NODE_LIST 4 + +#define NODE_TYPE_UNKNOWN 0 /* Unknown link */ +#define NODE_TYPE_WIFI_ONLY 1 /* Pure Wireless STA node */ +#define NODE_TYPE_PLC_ONLY 2 /* Pure PLC only node */ +#define NODE_TYPE_WIFI_PLC 3 /* WiFi PLC capable node */ + /* defines used by poweridx iovar - it controls power in a-band */ /* current gain setting is maintained */ #define WL_PWRIDX_PCL_OFF -2 /* turn off PCL. */ @@ -1264,7 +1299,7 @@ typedef struct { /* Get MAC rate histogram response */ typedef struct { - uint32 rate[WLC_MAXRATE + 1]; /* Rates */ + uint32 rate[DOT11_RATE_MAX + 1]; /* Rates */ uint32 mcs[WL_RATESET_SZ_HT_MCS * WL_TX_CHAINS_MAX]; /* MCS counts */ uint32 vht[WL_RATESET_SZ_VHT_MCS][WL_TX_CHAINS_MAX]; /* VHT counts */ uint32 tsf_timer[2][2]; /* Start and End time for 8bytes value */ @@ -1322,6 +1357,7 @@ typedef struct wlc_rev_info { uint phyrev; /* phy revision */ uint anarev; /* anacore rev */ uint chippkg; /* chip package info */ + uint nvramrev; /* nvram revision number */ } wlc_rev_info_t; #define WL_REV_INFO_LEGACY_LENGTH 48 @@ -1655,7 +1691,9 @@ typedef struct wlc_iov_trx_s { #define WLC_NVRAM_SET 265 #define WLC_NVRAM_DUMP 266 #define WLC_REBOOT 267 +#endif /* LINUX_POSTMOGRIFY_REMOVAL */ #define WLC_SET_WSEC_PMK 268 +#ifndef LINUX_POSTMOGRIFY_REMOVAL #define WLC_GET_AUTH_MODE 269 #define WLC_SET_AUTH_MODE 270 #define WLC_GET_WAKEENTRY 271 @@ -1776,15 +1814,12 @@ typedef struct { /* WLC_GET_AUTH, WLC_SET_AUTH values */ #define WL_AUTH_OPEN_SYSTEM 0 /* d11 open authentication */ #define WL_AUTH_SHARED_KEY 1 /* d11 shared authentication */ -#ifdef BCM4330_CHIP +#ifndef CONFIG_BCM4334 #define WL_AUTH_OPEN_SHARED 2 /* try open, then shared if open failed w/rc 13 */ #else -/* BCM4334(Phoenex branch) value changed to 3 */ -#define WL_AUTH_OPEN_SHARED 3 /* try open, then shared if open failed w/rc 13 */ +#define WL_AUTH_OPEN_SHARED 3 /* BCM4334(Phoenix branch) value changed to 3 */ #endif -#ifdef USE_WEP_AUTH_SHARED_OPEN -#define WL_AUTH_SHARED_OPEN 4 /* try shared, then open if shared failed w/rc 13 */ -#endif /* USE_WEP_AUTH_SHARED_OPEN */ + #endif /* LINUX_POSTMOGRIFY_REMOVAL */ /* Bit masks for radio disabled status - returned by WL_GET_RADIO */ @@ -1805,6 +1840,16 @@ typedef struct { #define WL_PHY_PAVARS_LEN 32 /* Phy type, Band range, chain, a1[0], b0[0], b1[0] ... */ #define WL_PHY_PAVAR_VER 1 /* pavars version */ +#define WL_PHY_PAVARS2_NUM 3 /* a1, b0, b1 */ +typedef struct wl_pavars2 { + uint16 ver; /* version of this struct */ + uint16 len; /* len of this structure */ + uint16 inuse; /* driver return 1 for a1,b0,b1 in current band range */ + uint16 phy_type; /* phy type */ + uint16 bandrange; + uint16 chain; + uint16 inpa[WL_PHY_PAVARS2_NUM]; /* phy pavars for one band range */ +} wl_pavars2_t; typedef struct wl_po { uint16 phy_type; /* Phy type */ @@ -1856,6 +1901,12 @@ typedef struct wl_po { #define WL_CHAN_FREQ_RANGE_5GM 2 #define WL_CHAN_FREQ_RANGE_5GH 3 +#define WL_CHAN_FREQ_RANGE_5GLL_5BAND 4 +#define WL_CHAN_FREQ_RANGE_5GLH_5BAND 5 +#define WL_CHAN_FREQ_RANGE_5GML_5BAND 6 +#define WL_CHAN_FREQ_RANGE_5GMH_5BAND 7 +#define WL_CHAN_FREQ_RANGE_5GH_5BAND 8 + #define WL_CHAN_FREQ_RANGE_5G_BAND0 1 #define WL_CHAN_FREQ_RANGE_5G_BAND1 2 #define WL_CHAN_FREQ_RANGE_5G_BAND2 3 @@ -1982,10 +2033,6 @@ typedef struct wl_po { /* when sgi_tx==WLC_SGI_ALL, bypass rate selection, enable sgi for all mcs */ #define WLC_SGI_ALL 0x02 -#define DHD_SCAN_ACTIVE_TIME 40 /* ms : Embedded default Active setting from DHD */ -#define DHD_SCAN_UNASSOC_ACTIVE_TIME 80 /* ms : def. Unassoc Active setting from DHD */ -#define DHD_SCAN_PASSIVE_TIME 130 /* ms: Embedded default Passive setting from DHD */ - #define LISTEN_INTERVAL 10 /* interference mitigation options */ #define INTERFERE_OVRRIDE_OFF -1 /* interference override off */ @@ -2060,6 +2107,8 @@ typedef struct wl_samplecollect_args { uint8 module_sel1; uint8 module_sel2; uint16 nsamps; + int bitStart; + uint32 gpioCapMask; } wl_samplecollect_args_t; #define WL_SAMPLEDATA_HEADER_TYPE 1 @@ -2079,6 +2128,117 @@ typedef struct wl_sampledata { uint32 flag; /* bit def */ } wl_sampledata_t; +/* WL_OTA START */ + +#define WL_OTA_ARG_PARSE_BLK_SIZE 1200 +#define WL_OTA_TEST_MAX_NUM_RATE 30 +#define WL_OTA_TEST_MAX_NUM_SEQ 100 + +/* OTA Test Status */ +enum { + WL_OTA_TEST_IDLE, /* Default Idle state */ + WL_OTA_TEST_ACTIVE, /* Test Running */ + WL_OTA_TEST_SUCCESS, /* Successfully Finished Test */ + WL_OTA_TEST_FAIL /* Test Failed in the Middle */ +}; +/* OTA SYNC Status */ +enum { + WL_OTA_SYNC_IDLE, /* Idle state */ + WL_OTA_SYNC_ACTIVE, /* Waiting for Sync */ + WL_OTA_SYNC_FAIL /* Sync pkt not recieved */ +}; + +/* Various error states dut can get stuck during test */ +enum { + WL_OTA_SKIP_TEST_CAL_FAIL = 1, /* Phy calibration failed */ + WL_OTA_SKIP_TEST_SYNCH_FAIL, /* Sync Packet not recieved */ + WL_OTA_SKIP_TEST_FILE_DWNLD_FAIL, /* Cmd flow file download failed */ + WL_OTA_SKIP_TEST_NO_TEST_FOUND, /* No test found in Flow file */ + WL_OTA_SKIP_TEST_WL_NOT_UP, /* WL UP failed */ + WL_OTA_SKIP_TEST_UNKNOWN_CALL /* Unintentional scheduling on ota test */ +}; + +/* Differentiator for ota_tx and ota_rx */ +enum { + WL_OTA_TEST_TX, /* ota_tx */ + WL_OTA_TEST_RX /* ota_rx */ +}; + +/* Catch 3 modes of operation: 20Mhz, 40Mhz, 20 in 40 Mhz */ +enum { + WL_OTA_TEST_BW_20_IN_40MHZ, /* 20 in 40 operation */ + WL_OTA_TEST_BW_20MHZ, /* 20 Mhz operation */ + WL_OTA_TEST_BW_40MHZ /* full 40Mhz operation */ +}; +typedef struct ota_rate_info { + uint8 rate_cnt; /* Total number of rates */ + uint8 rate_val_mbps[WL_OTA_TEST_MAX_NUM_RATE]; /* array of rates from 1mbps to 130mbps */ + /* for legacy rates : ratein mbps * 2 */ + /* for HT rates : mcs index */ +} ota_rate_info_t; + +typedef struct ota_power_info { + int8 pwr_ctrl_on; /* power control on/off */ + int8 start_pwr; /* starting power/index */ + int8 delta_pwr; /* delta power/index */ + int8 end_pwr; /* end power/index */ +} ota_power_info_t; + +typedef struct ota_packetengine { + uint16 delay; /* Inter-packet delay */ + /* for ota_tx, delay is tx ifs in micro seconds */ + /* for ota_rx, delay is wait time in milliseconds */ + uint16 nframes; /* Number of frames */ + uint16 length; /* Packet length */ +} ota_packetengine_t; + +/* Test info vector */ +typedef struct wl_ota_test_args { + uint8 cur_test; /* test phase */ + uint8 chan; /* channel */ + uint8 bw; /* bandwidth */ + char control_band; /* control band */ + uint8 stf_mode; /* stf mode */ + ota_rate_info_t rt_info; /* Rate info */ + ota_packetengine_t pkteng; /* packeteng info */ + uint8 txant; /* tx antenna */ + uint8 rxant; /* rx antenna */ + ota_power_info_t pwr_info; /* power sweep info */ + uint8 wait_for_sync; /* wait for sync or not */ +} wl_ota_test_args_t; + +typedef struct wl_ota_test_vector { + wl_ota_test_args_t test_arg[WL_OTA_TEST_MAX_NUM_SEQ]; /* Test argument struct */ + uint16 test_cnt; /* Total no of test */ + bool file_dwnld_valid; /* File successfully downloaded */ + uint8 sync_timeout; /* sync packet timeout */ + int8 sync_fail_action; /* sync fail action */ + struct ether_addr sync_mac; /* macaddress for sync pkt */ + struct ether_addr tx_mac; /* macaddress for tx */ + struct ether_addr rx_mac; /* macaddress for rx */ + int8 loop_test; /* dbg feature to loop the test */ +} wl_ota_test_vector_t; + + +/* struct copied back form dongle to host to query the status */ +typedef struct wl_ota_test_status { + int16 cur_test_cnt; /* test phase */ + int8 skip_test_reason; /* skip test reasoin */ + wl_ota_test_args_t test_arg; /* cur test arg details */ + uint16 test_cnt; /* total no of test downloaded */ + bool file_dwnld_valid; /* file successfully downloaded ? */ + uint8 sync_timeout; /* sync timeout */ + int8 sync_fail_action; /* sync fail action */ + struct ether_addr sync_mac; /* macaddress for sync pkt */ + struct ether_addr tx_mac; /* tx mac address */ + struct ether_addr rx_mac; /* rx mac address */ + uint8 test_stage; /* check the test status */ + int8 loop_test; /* Debug feature to puts test enfine in a loop */ + uint8 sync_status; /* sync status */ +} wl_ota_test_status_t; + +/* WL_OTA END */ + /* wl_radar_args_t */ typedef struct { int npulses; /* required number of pulses at n * t_int */ @@ -2258,168 +2418,168 @@ typedef struct { typedef struct txppr { /* start of 20MHz tx power limits */ - uint8 b20_1x1dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b20_1x1ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM transmission */ - uint8 b20_1x1mcs0[WL_NUM_RATES_MCS_1STREAM]; /* SISO MCS 0-7 */ - - uint8 b20_1x2dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b20_1x2cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ - uint8 b20_1x2cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* CDD MCS 0-7 */ - uint8 b20_2x2stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ - uint8 b20_2x2sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* MCS 8-15 */ - - uint8 b20_1x3dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b20_1x3cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ - uint8 b20_1x3cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* 1 Nsts to 3 Tx Chain */ - uint8 b20_2x3stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ - uint8 b20_2x3sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* 2 Nsts to 3 Tx Chain */ - uint8 b20_3x3sdm_mcs16[WL_NUM_RATES_MCS_1STREAM]; /* 3 Nsts to 3 Tx Chain */ - - uint8 b20_1x1vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1 */ - uint8 b20_1x2cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD1 */ - uint8 b20_2x2stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC */ - uint8 b20_2x2sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2 */ - uint8 b20_1x3cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD2 */ - uint8 b20_2x3stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC_SPEXP1 */ - uint8 b20_2x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2_SPEXP1 */ - uint8 b20_3x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS3 */ + int8 b20_1x1dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b20_1x1ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM transmission */ + int8 b20_1x1mcs0[WL_NUM_RATES_MCS_1STREAM]; /* SISO MCS 0-7 */ + + int8 b20_1x2dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b20_1x2cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ + int8 b20_1x2cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* CDD MCS 0-7 */ + int8 b20_2x2stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ + int8 b20_2x2sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* MCS 8-15 */ + + int8 b20_1x3dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b20_1x3cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ + int8 b20_1x3cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* 1 Nsts to 3 Tx Chain */ + int8 b20_2x3stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ + int8 b20_2x3sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* 2 Nsts to 3 Tx Chain */ + int8 b20_3x3sdm_mcs16[WL_NUM_RATES_MCS_1STREAM]; /* 3 Nsts to 3 Tx Chain */ + + int8 b20_1x1vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1 */ + int8 b20_1x2cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD1 */ + int8 b20_2x2stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC */ + int8 b20_2x2sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2 */ + int8 b20_1x3cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD2 */ + int8 b20_2x3stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC_SPEXP1 */ + int8 b20_2x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2_SPEXP1 */ + int8 b20_3x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS3 */ /* start of 40MHz tx power limits */ - uint8 b40_dummy1x1dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b40_1x1ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM transmission */ - uint8 b40_1x1mcs0[WL_NUM_RATES_MCS_1STREAM]; /* SISO MCS 0-7 */ - - uint8 b40_dummy1x2dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b40_1x2cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ - uint8 b40_1x2cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* CDD MCS 0-7 */ - uint8 b40_2x2stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ - uint8 b40_2x2sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* MCS 8-15 */ - - uint8 b40_dummy1x3dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b40_1x3cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ - uint8 b40_1x3cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* 1 Nsts to 3 Tx Chain */ - uint8 b40_2x3stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ - uint8 b40_2x3sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* 2 Nsts to 3 Tx Chain */ - uint8 b40_3x3sdm_mcs16[WL_NUM_RATES_MCS_1STREAM]; /* 3 Nsts to 3 Tx Chain */ - - uint8 b40_1x1vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1 */ - uint8 b40_1x2cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD1 */ - uint8 b40_2x2stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC */ - uint8 b40_2x2sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2 */ - uint8 b40_1x3cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD2 */ - uint8 b40_2x3stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC_SPEXP1 */ - uint8 b40_2x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2_SPEXP1 */ - uint8 b40_3x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS3 */ + int8 b40_dummy1x1dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b40_1x1ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM transmission */ + int8 b40_1x1mcs0[WL_NUM_RATES_MCS_1STREAM]; /* SISO MCS 0-7 */ + + int8 b40_dummy1x2dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b40_1x2cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ + int8 b40_1x2cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* CDD MCS 0-7 */ + int8 b40_2x2stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ + int8 b40_2x2sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* MCS 8-15 */ + + int8 b40_dummy1x3dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b40_1x3cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ + int8 b40_1x3cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* 1 Nsts to 3 Tx Chain */ + int8 b40_2x3stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ + int8 b40_2x3sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* 2 Nsts to 3 Tx Chain */ + int8 b40_3x3sdm_mcs16[WL_NUM_RATES_MCS_1STREAM]; /* 3 Nsts to 3 Tx Chain */ + + int8 b40_1x1vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1 */ + int8 b40_1x2cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD1 */ + int8 b40_2x2stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC */ + int8 b40_2x2sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2 */ + int8 b40_1x3cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD2 */ + int8 b40_2x3stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC_SPEXP1 */ + int8 b40_2x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2_SPEXP1 */ + int8 b40_3x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS3 */ /* start of 20in40MHz tx power limits */ - uint8 b20in40_1x1dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b20in40_1x1ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM transmission */ - uint8 b20in40_1x1mcs0[WL_NUM_RATES_MCS_1STREAM]; /* SISO MCS 0-7 */ - - uint8 b20in40_1x2dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b20in40_1x2cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ - uint8 b20in40_1x2cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* CDD MCS 0-7 */ - uint8 b20in40_2x2stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ - uint8 b20in40_2x2sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* MCS 8-15 */ - - uint8 b20in40_1x3dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b20in40_1x3cdd_ofdm[WL_NUM_RATES_OFDM]; /* 20 in 40 MHz Legacy OFDM CDD */ - uint8 b20in40_1x3cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* 1 Nsts to 3 Tx Chain */ - uint8 b20in40_2x3stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ - uint8 b20in40_2x3sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* 2 Nsts to 3 Tx Chain */ - uint8 b20in40_3x3sdm_mcs16[WL_NUM_RATES_MCS_1STREAM]; /* 3 Nsts to 3 Tx Chain */ - - uint8 b20in40_1x1vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1 */ - uint8 b20in40_1x2cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD1 */ - uint8 b20in40_2x2stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC */ - uint8 b20in40_2x2sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2 */ - uint8 b20in40_1x3cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD2 */ - uint8 b20in40_2x3stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC_SPEXP1 */ - uint8 b20in40_2x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2_SPEXP1 */ - uint8 b20in40_3x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS3 */ + int8 b20in40_1x1dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b20in40_1x1ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM transmission */ + int8 b20in40_1x1mcs0[WL_NUM_RATES_MCS_1STREAM]; /* SISO MCS 0-7 */ + + int8 b20in40_1x2dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b20in40_1x2cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ + int8 b20in40_1x2cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* CDD MCS 0-7 */ + int8 b20in40_2x2stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ + int8 b20in40_2x2sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* MCS 8-15 */ + + int8 b20in40_1x3dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b20in40_1x3cdd_ofdm[WL_NUM_RATES_OFDM]; /* 20 in 40 MHz Legacy OFDM CDD */ + int8 b20in40_1x3cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* 1 Nsts to 3 Tx Chain */ + int8 b20in40_2x3stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ + int8 b20in40_2x3sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* 2 Nsts to 3 Tx Chain */ + int8 b20in40_3x3sdm_mcs16[WL_NUM_RATES_MCS_1STREAM]; /* 3 Nsts to 3 Tx Chain */ + + int8 b20in40_1x1vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1 */ + int8 b20in40_1x2cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD1 */ + int8 b20in40_2x2stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC */ + int8 b20in40_2x2sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2 */ + int8 b20in40_1x3cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD2 */ + int8 b20in40_2x3stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC_SPEXP1 */ + int8 b20in40_2x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2_SPEXP1 */ + int8 b20in40_3x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS3 */ /* start of 80MHz tx power limits */ - uint8 b80_dummy1x1dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b80_1x1ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM transmission */ - uint8 b80_1x1mcs0[WL_NUM_RATES_MCS_1STREAM]; /* SISO MCS 0-7 */ - - uint8 b80_dummy1x2dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b80_1x2cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ - uint8 b80_1x2cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* CDD MCS 0-7 */ - uint8 b80_2x2stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ - uint8 b80_2x2sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* MCS 8-15 */ - - uint8 b80_dummy1x3dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b80_1x3cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ - uint8 b80_1x3cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* 1 Nsts to 3 Tx Chain */ - uint8 b80_2x3stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ - uint8 b80_2x3sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* 2 Nsts to 3 Tx Chain */ - uint8 b80_3x3sdm_mcs16[WL_NUM_RATES_MCS_1STREAM]; /* 3 Nsts to 3 Tx Chain */ - - uint8 b80_1x1vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1 */ - uint8 b80_1x2cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD1 */ - uint8 b80_2x2stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC */ - uint8 b80_2x2sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2 */ - uint8 b80_1x3cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD2 */ - uint8 b80_2x3stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC_SPEXP1 */ - uint8 b80_2x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2_SPEXP1 */ - uint8 b80_3x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS3 */ + int8 b80_dummy1x1dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b80_1x1ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM transmission */ + int8 b80_1x1mcs0[WL_NUM_RATES_MCS_1STREAM]; /* SISO MCS 0-7 */ + + int8 b80_dummy1x2dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b80_1x2cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ + int8 b80_1x2cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* CDD MCS 0-7 */ + int8 b80_2x2stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ + int8 b80_2x2sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* MCS 8-15 */ + + int8 b80_dummy1x3dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b80_1x3cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ + int8 b80_1x3cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* 1 Nsts to 3 Tx Chain */ + int8 b80_2x3stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ + int8 b80_2x3sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* 2 Nsts to 3 Tx Chain */ + int8 b80_3x3sdm_mcs16[WL_NUM_RATES_MCS_1STREAM]; /* 3 Nsts to 3 Tx Chain */ + + int8 b80_1x1vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1 */ + int8 b80_1x2cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD1 */ + int8 b80_2x2stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC */ + int8 b80_2x2sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2 */ + int8 b80_1x3cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD2 */ + int8 b80_2x3stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC_SPEXP1 */ + int8 b80_2x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2_SPEXP1 */ + int8 b80_3x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS3 */ /* start of 20in80MHz tx power limits */ - uint8 b20in80_1x1dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b20in80_1x1ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM transmission */ - uint8 b20in80_1x1mcs0[WL_NUM_RATES_MCS_1STREAM]; /* SISO MCS 0-7 */ - - uint8 b20in80_1x2dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b20in80_1x2cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ - uint8 b20in80_1x2cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* CDD MCS 0-7 */ - uint8 b20in80_2x2stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ - uint8 b20in80_2x2sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* MCS 8-15 */ - - uint8 b20in80_1x3dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b20in80_1x3cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ - uint8 b20in80_1x3cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* 1 Nsts to 3 Tx Chain */ - uint8 b20in80_2x3stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ - uint8 b20in80_2x3sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* 2 Nsts to 3 Tx Chain */ - uint8 b20in80_3x3sdm_mcs16[WL_NUM_RATES_MCS_1STREAM]; /* 3 Nsts to 3 Tx Chain */ - - uint8 b20in80_1x1vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1 */ - uint8 b20in80_1x2cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD1 */ - uint8 b20in80_2x2stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC */ - uint8 b20in80_2x2sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2 */ - uint8 b20in80_1x3cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD2 */ - uint8 b20in80_2x3stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC_SPEXP1 */ - uint8 b20in80_2x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2_SPEXP1 */ - uint8 b20in80_3x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS3 */ + int8 b20in80_1x1dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b20in80_1x1ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM transmission */ + int8 b20in80_1x1mcs0[WL_NUM_RATES_MCS_1STREAM]; /* SISO MCS 0-7 */ + + int8 b20in80_1x2dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b20in80_1x2cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ + int8 b20in80_1x2cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* CDD MCS 0-7 */ + int8 b20in80_2x2stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ + int8 b20in80_2x2sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* MCS 8-15 */ + + int8 b20in80_1x3dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b20in80_1x3cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ + int8 b20in80_1x3cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* 1 Nsts to 3 Tx Chain */ + int8 b20in80_2x3stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ + int8 b20in80_2x3sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* 2 Nsts to 3 Tx Chain */ + int8 b20in80_3x3sdm_mcs16[WL_NUM_RATES_MCS_1STREAM]; /* 3 Nsts to 3 Tx Chain */ + + int8 b20in80_1x1vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1 */ + int8 b20in80_1x2cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD1 */ + int8 b20in80_2x2stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC */ + int8 b20in80_2x2sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2 */ + int8 b20in80_1x3cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD2 */ + int8 b20in80_2x3stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC_SPEXP1 */ + int8 b20in80_2x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2_SPEXP1 */ + int8 b20in80_3x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS3 */ /* start of 40in80MHz tx power limits */ - uint8 b40in80_dummy1x1dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b40in80_1x1ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM transmission */ - uint8 b40in80_1x1mcs0[WL_NUM_RATES_MCS_1STREAM]; /* SISO MCS 0-7 */ - - uint8 b40in80_dummy1x2dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b40in80_1x2cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ - uint8 b40in80_1x2cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* CDD MCS 0-7 */ - uint8 b40in80_2x2stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ - uint8 b40in80_2x2sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* MCS 8-15 */ - - uint8 b40in80_dummy1x3dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ - uint8 b40in80_1x3cdd_ofdm[WL_NUM_RATES_OFDM]; /* MHz Legacy OFDM CDD */ - uint8 b40in80_1x3cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* 1 Nsts to 3 Tx Chain */ - uint8 b40in80_2x3stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ - uint8 b40in80_2x3sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* 2 Nsts to 3 Tx Chain */ - uint8 b40in80_3x3sdm_mcs16[WL_NUM_RATES_MCS_1STREAM]; /* 3 Nsts to 3 Tx Chain */ - - uint8 b40in80_1x1vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1 */ - uint8 b40in80_1x2cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD1 */ - uint8 b40in80_2x2stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC */ - uint8 b40in80_2x2sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2 */ - uint8 b40in80_1x3cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD2 */ - uint8 b40in80_2x3stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC_SPEXP1 */ - uint8 b40in80_2x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2_SPEXP1 */ - uint8 b40in80_3x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS3 */ - - uint8 mcs32; /* C_CHECK - THIS NEEDS TO BE REMOVED THROUGHOUT THE CODE */ + int8 b40in80_dummy1x1dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b40in80_1x1ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM transmission */ + int8 b40in80_1x1mcs0[WL_NUM_RATES_MCS_1STREAM]; /* SISO MCS 0-7 */ + + int8 b40in80_dummy1x2dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b40in80_1x2cdd_ofdm[WL_NUM_RATES_OFDM]; /* Legacy OFDM CDD transmission */ + int8 b40in80_1x2cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* CDD MCS 0-7 */ + int8 b40in80_2x2stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ + int8 b40in80_2x2sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* MCS 8-15 */ + + int8 b40in80_dummy1x3dsss[WL_NUM_RATES_CCK]; /* Legacy CCK/DSSS */ + int8 b40in80_1x3cdd_ofdm[WL_NUM_RATES_OFDM]; /* MHz Legacy OFDM CDD */ + int8 b40in80_1x3cdd_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* 1 Nsts to 3 Tx Chain */ + int8 b40in80_2x3stbc_mcs0[WL_NUM_RATES_MCS_1STREAM]; /* STBC MCS 0-7 */ + int8 b40in80_2x3sdm_mcs8[WL_NUM_RATES_MCS_1STREAM]; /* 2 Nsts to 3 Tx Chain */ + int8 b40in80_3x3sdm_mcs16[WL_NUM_RATES_MCS_1STREAM]; /* 3 Nsts to 3 Tx Chain */ + + int8 b40in80_1x1vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1 */ + int8 b40in80_1x2cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD1 */ + int8 b40in80_2x2stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC */ + int8 b40in80_2x2sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2 */ + int8 b40in80_1x3cdd_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_CDD2 */ + int8 b40in80_2x3stbc_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS1_STBC_SPEXP1 */ + int8 b40in80_2x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS2_SPEXP1 */ + int8 b40in80_3x3sdm_vht[WL_NUM_RATES_EXTRA_VHT]; /* VHT8_9SS3 */ + + int8 mcs32; /* C_CHECK - THIS NEEDS TO BE REMOVED THROUGHOUT THE CODE */ } txppr_t; /* 20MHz */ @@ -2601,45 +2761,35 @@ typedef struct txppr { #define WL_TX_POWER_MCS20_SISO_FIRST_SSN WL_TX_POWER_MCS20_SISO_FIRST #define WL_TX_POWER_MCS40_SISO_FIRST_SSN WL_TX_POWER_MCS40_SISO_FIRST -/* tx_power_t.flags bits */ -#define WL_TX_POWER_F_ENABLED 1 -#define WL_TX_POWER_F_HW 2 -#define WL_TX_POWER_F_MIMO 4 -#define WL_TX_POWER_F_SISO 8 -#define WL_TX_POWER_F_HT 0x10 - typedef struct { uint16 ver; /* version of this struct */ uint16 len; /* length in bytes of this structure */ uint32 flags; chanspec_t chanspec; /* txpwr report for this channel */ chanspec_t local_chanspec; /* channel on which we are associated */ - uint8 ppr[WL_TX_POWER_RATES]; /* Latest target power */ + uint32 buflen; /* ppr buffer length */ + uint8 pprbuf[1]; /* Latest target power buffer buffer */ } wl_txppr_t; #define WL_TXPPR_VERSION 0 #define WL_TXPPR_LENGTH (sizeof(wl_txppr_t)) -#define TX_POWER_T_VERSION 43 +#define TX_POWER_T_VERSION 44 /* Defines used with channel_bandwidth for curpower */ #define WL_BW_20MHZ 0 #define WL_BW_40MHZ 1 #define WL_BW_80MHZ 2 +#define WL_BW_160MHZ 3 /* tx_power_t.flags bits */ -#ifdef PPR_API -#define WL_TX_POWER2_F_ENABLED 1 -#define WL_TX_POWER2_F_HW 2 -#define WL_TX_POWER2_F_MIMO 4 -#define WL_TX_POWER2_F_SISO 8 -#define WL_TX_POWER2_F_HT 0x10 -#else +/* use for defined PPR_API */ #define WL_TX_POWER_F_ENABLED 1 #define WL_TX_POWER_F_HW 2 #define WL_TX_POWER_F_MIMO 4 #define WL_TX_POWER_F_SISO 8 #define WL_TX_POWER_F_HT 0x10 -#endif +#define WL_TX_POWER_F_VHT 0x20 + typedef struct { uint32 flags; chanspec_t chanspec; /* txpwr report for this channel */ @@ -2649,9 +2799,7 @@ typedef struct { int8 antgain[2]; /* Ant gain for each band - from SROM */ uint8 rf_cores; /* count of RF Cores being reported */ uint8 est_Pout[4]; /* Latest tx power out estimate per RF chain */ - uint8 est_Pout_act[4]; /* Latest tx power out estimate per RF chain - * without adjustment - */ + uint8 est_Pout_act[4]; /* Latest tx power out estimate per RF chain w/o adjustment */ uint8 est_Pout_cck; /* Latest CCK tx power out estimate */ uint8 tx_power_max[4]; /* Maximum target power among all rates */ uint tx_power_max_rate_ind[4]; /* Index of the rate with the max target power */ @@ -2665,11 +2813,10 @@ typedef struct { int8 channel_bandwidth; /* 20, 40 or 80 MHz bandwidth? */ uint8 version; /* Version of the data format wlu <--> driver */ uint8 display_core; /* Displayed curpower core */ -#ifdef PPR_API -} tx_power_new_t; -#else + int8 target_offsets[4]; /* Target power offsets for current rate per core */ + uint32 last_tx_ratespec; /* Ratespec for last transmition */ + int8 SARLIMIT[MAX_STREAMS_SUPPORTED]; } tx_power_t; -#endif typedef struct tx_inst_power { uint8 txpwr_est_Pout[2]; /* Latest estimate for 2.4 and 5 Ghz */ @@ -2813,6 +2960,11 @@ typedef struct wl_txchain_pwr_offsets { #define WL_TBTT_VAL 0x00010000 #define WL_NIC_VAL 0x00020000 #define WL_PWRSEL_VAL 0x00040000 +#define WL_TRF_MGMT_VAL 0x00080000 +#define WL_L2FILTER_VAL 0x00100000 +#define WL_TSO_VAL 0x00200000 +#define WL_MQ_VAL 0x00400000 + /* use top-bit for WL_TIME_STAMP_VAL because this is a modifier * rather than a message-type of its own */ @@ -2845,7 +2997,9 @@ typedef struct wl_txchain_pwr_offsets { #define WL_LED_ASSOC_WITH_SEC 20 /* when connected with security */ /* keep on for 300 sec */ #define WL_LED_START_OFF 21 /* off upon boot, could be turned on later */ -#define WL_LED_NUMBEHAVIOR 22 +#define WL_LED_W6 22 /* off upon boot, could be turned on later */ +#define WL_LED_WI7 23 /* off upon boot, could be turned on later */ +#define WL_LED_NUMBEHAVIOR 24 /* led behavior numeric value format */ #define WL_LED_BEH_MASK 0x7f /* behavior mask */ @@ -2903,7 +3057,7 @@ typedef struct wl_txchain_pwr_offsets { * * 4. BAND RSSI - 2 octets * offset 0: band types - * offset 1: +ve RSSI boost balue in dB + * offset 1: +ve RSSI boost value in dB */ /* join preference types */ @@ -3167,6 +3321,12 @@ typedef struct { uint32 pstatxbcmc; /* count of bcmc frames transmitted on all psta */ uint32 cso_passthrough; /* hw cso required but passthrough */ + uint32 chained; /* number of frames chained */ + uint32 chainedsz1; /* number of chain size 1 frames */ + uint32 unchained; /* number of frames not chained */ + uint32 maxchainsz; /* max chain size so far */ + uint32 currchainsz; /* current chain size */ + uint32 cso_normal; /* hw cso hdr for normal process */ } wl_cnt_t; #ifndef LINUX_POSTMOGRIFY_REMOVAL @@ -3607,13 +3767,14 @@ struct tslist { #ifdef WLTDLS /* different ops for manual end point */ -#define TDLS_MANUAL_EP_CREATE 1 /* create manual dpt endpoint */ -#define TDLS_MANUAL_EP_MODIFY 2 /* modify manual dpt endpoint */ -#define TDLS_MANUAL_EP_DELETE 3 /* delete manual dpt endpoint */ +#define TDLS_MANUAL_EP_CREATE 1 /* create manual dpt endpoint */ +#define TDLS_MANUAL_EP_MODIFY 2 /* modify manual dpt endpoint */ +#define TDLS_MANUAL_EP_DELETE 3 /* delete manual dpt endpoint */ #define TDLS_MANUAL_EP_PM 4 /* put dpt endpoint in PM mode */ #define TDLS_MANUAL_EP_WAKE 5 /* wake up dpt endpoint from PM */ #define TDLS_MANUAL_EP_DISCOVERY 6 /* discover if endpoint is TDLS capable */ #define TDLS_MANUAL_EP_CHSW 7 /* channel switch */ +#define TDLS_MANUAL_EP_WFD_TPQ 8 /* WiFi-Display Tunneled Probe reQuest */ /* structure for tdls iovars */ typedef struct tdls_iovar { @@ -3624,14 +3785,16 @@ typedef struct tdls_iovar { } tdls_iovar_t; /* modes */ -#define TDLS_WFD_IE_TX 0 -#define TDLS_WFD_IE_RX 1 -#define TDLS_WFD_IE_SIZE 255 +#define TDLS_WFD_IE_TX 0 +#define TDLS_WFD_IE_RX 1 +#define TDLS_WFD_PROBE_IE_TX 2 +#define TDLS_WFD_PROBE_IE_RX 3 +#define TDLS_WFD_IE_SIZE 512 /* structure for tdls wfd ie */ typedef struct tdls_wfd_ie_iovar { struct ether_addr ea; /* Station address */ uint8 mode; - uint8 length; + uint16 length; uint8 data[TDLS_WFD_IE_SIZE]; } tdls_wfd_ie_iovar_t; #endif /* WLTDLS */ @@ -3701,11 +3864,11 @@ typedef struct wme_max_bandwidth { /* Software feature flag defines used by wlfeatureflag */ #ifdef WLAFTERBURNER -#define WL_SWFL_ABBFL 0x0001 /* Allow Afterburner on systems w/o hardware BFL */ -#define WL_SWFL_ABENCORE 0x0002 /* Allow AB on non-4318E chips */ +#define WL_SWFL_ABBFL 0x0001 /* Allow Afterburner on systems w/o hardware BFL */ +#define WL_SWFL_ABENCORE 0x0002 /* Allow AB on non-4318E chips */ #endif /* WLAFTERBURNER */ #define WL_SWFL_NOHWRADIO 0x0004 -#define WL_SWFL_FLOWCONTROL 0x0008 /* Enable backpressure to OS stack */ +#define WL_SWFL_FLOWCONTROL 0x0008 /* Enable backpressure to OS stack */ #define WL_SWFL_WLBSSSORT 0x0010 /* Per-port supports sorting of BSS */ #define WL_LIFETIME_MAX 0xFFFF /* Max value in ms */ @@ -3773,8 +3936,8 @@ enum { #define ENABLE_NET_OFFLOAD_BIT 10 #define SORT_CRITERIA_MASK 0x0001 -#define AUTO_NET_SWITCH_MASK 0x0002 -#define ENABLE_BKGRD_SCAN_MASK 0x0004 +#define AUTO_NET_SWITCH_MASK 0x0002 +#define ENABLE_BKGRD_SCAN_MASK 0x0004 #define IMMEDIATE_SCAN_MASK 0x0008 #define AUTO_CONNECT_MASK 0x0010 @@ -3784,7 +3947,7 @@ enum { #define SUPPRESS_SSID_MASK 0x0200 #define ENABLE_NET_OFFLOAD_MASK 0x0400 -#define PFN_VERSION 2 +#define PFN_VERSION 2 #define PFN_SCANRESULT_VERSION 1 #define MAX_PFN_LIST_COUNT 16 @@ -3794,7 +3957,7 @@ enum { #define DEFAULT_BESTN 2 #define DEFAULT_MSCAN 0 #define DEFAULT_REPEAT 10 -#define DEFAULT_EXP 2 +#define DEFAULT_EXP 2 /* PFN network info structure */ typedef struct wl_pfn_subnet_info { @@ -3822,54 +3985,56 @@ typedef struct wl_pfn_param { int32 version; /* PNO parameters version */ int32 scan_freq; /* Scan frequency */ int32 lost_network_timeout; /* Timeout in sec. to declare - * discovered network as lost - */ + * discovered network as lost + */ int16 flags; /* Bit field to control features - * of PFN such as sort criteria auto - * enable switch and background scan - */ + * of PFN such as sort criteria auto + * enable switch and background scan + */ int16 rssi_margin; /* Margin to avoid jitter for choosing a - * PFN based on RSSI sort criteria - */ - uint8 bestn; /* number of best networks in each scan */ - uint8 mscan; /* number of scans recorded */ - uint8 repeat; /* Minimum number of scan intervals - *before scan frequency changes in adaptive scan - */ - uint8 exp; /* Exponent of 2 for maximum scan interval */ - int32 slow_freq; /* slow scan period */ + * PFN based on RSSI sort criteria + */ + uint8 bestn; /* number of best networks in each scan */ + uint8 mscan; /* number of scans recorded */ + uint8 repeat; /* Minimum number of scan intervals + *before scan frequency changes in adaptive scan + */ + uint8 exp; /* Exponent of 2 for maximum scan interval */ + int32 slow_freq; /* slow scan period */ } wl_pfn_param_t; typedef struct wl_pfn_bssid { - struct ether_addr macaddr; + struct ether_addr macaddr; /* Bit4: suppress_lost, Bit3: suppress_found */ - uint16 flags; + uint16 flags; } wl_pfn_bssid_t; #define WL_PFN_SUPPRESSFOUND_MASK 0x08 #define WL_PFN_SUPPRESSLOST_MASK 0x10 +#define WL_PFN_RSSI_MASK 0xff00 +#define WL_PFN_RSSI_SHIFT 8 typedef struct wl_pfn_cfg { - uint32 reporttype; - int32 channel_num; - uint16 channel_list[WL_NUMCHANNELS]; + uint32 reporttype; + int32 channel_num; + uint16 channel_list[WL_NUMCHANNELS]; } wl_pfn_cfg_t; -#define WL_PFN_REPORT_ALLNET 0 -#define WL_PFN_REPORT_SSIDNET 1 -#define WL_PFN_REPORT_BSSIDNET 2 +#define WL_PFN_REPORT_ALLNET 0 +#define WL_PFN_REPORT_SSIDNET 1 +#define WL_PFN_REPORT_BSSIDNET 2 typedef struct wl_pfn { - wlc_ssid_t ssid; /* ssid name and its length */ - int32 flags; /* bit2: hidden */ - int32 infra; /* BSS Vs IBSS */ - int32 auth; /* Open Vs Closed */ - int32 wpa_auth; /* WPA type */ - int32 wsec; /* wsec value */ + wlc_ssid_t ssid; /* ssid name and its length */ + int32 flags; /* bit2: hidden */ + int32 infra; /* BSS Vs IBSS */ + int32 auth; /* Open Vs Closed */ + int32 wpa_auth; /* WPA type */ + int32 wsec; /* wsec value */ } wl_pfn_t; -#define WL_PFN_HIDDEN_BIT 2 +#define WL_PFN_HIDDEN_BIT 2 #define PNO_SCAN_MAX_FW 508*1000 /* max time scan time in msec */ #define PNO_SCAN_MAX_FW_SEC PNO_SCAN_MAX_FW/1000 /* max time scan time in SEC */ -#define PNO_SCAN_MIN_FW_SEC 10 /* min time scan time in SEC */ -#define WL_PFN_HIDDEN_MASK 0x4 +#define PNO_SCAN_MIN_FW_SEC 10 /* min time scan time in SEC */ +#define WL_PFN_HIDDEN_MASK 0x4 #endif /* LINUX_POSTMOGRIFY_REMOVAL */ @@ -3925,7 +4090,7 @@ struct toe_ol_stats_t { #define ARP_ERRTEST_REPLY_HOST 0x2 #define ARP_MULTIHOMING_MAX 8 /* Maximum local host IP addresses */ -#define ND_MULTIHOMING_MAX 8 /* Maximum local host IP addresses */ +#define ND_MULTIHOMING_MAX 10 /* Maximum local host IP addresses */ /* Arp offload statistic counts */ struct arp_ol_stats_t { @@ -4065,6 +4230,8 @@ typedef struct wl_seq_cmd_ioctl { #define WL_PKTENG_SYNCHRONOUS 0x100 /* synchronous flag */ +#define WL_PKTENG_MAXPKTSZ 16384 /* max pktsz limit for pkteng */ + typedef struct wl_pkteng { uint32 flags; uint32 delay; /* Inter-packet delay */ @@ -4107,14 +4274,14 @@ typedef struct wl_pkteng_stats { #define MAGIC_PKT_MINLEN 102 /* Magic pkt min length is 6 * 0xFF + 16 * ETHER_ADDR_LEN */ #define WOWL_PATTEN_TYPE_ARP (1 << 0) /* ARP offload Pattern */ -#define WOWL_PATTEN_TYPE_NA (1 << 1) /* NA offload Pattern */ +#define WOWL_PATTEN_TYPE_NA (1 << 1) /* NA offload Pattern */ typedef struct { uint32 masksize; /* Size of the mask in #of bytes */ uint32 offset; /* Offset to start looking for the packet in # of bytes */ - uint32 patternoffset; /* Offset of start of pattern in the structure */ + uint32 patternoffset; /* Offset of start of pattern in the structure */ uint32 patternsize; /* Size of the pattern itself in #of bytes */ - uint32 id; /* id */ + uint32 id; /* id */ uint32 reasonsize; /* Size of the wakeup reason code */ uint32 flags; /* Flags to tell the pattern type and other properties */ /* Mask follows the structure above */ @@ -4248,6 +4415,37 @@ typedef struct { uint32 queue_capacity; /* the maximum capacity of the queue */ } pktq_log_counters_v01_t; +typedef struct { + uint32 requested; /* packets requested to be stored */ + uint32 stored; /* packets stored */ + uint32 saved; /* packets saved, + because a lowest priority queue has given away one packet + */ + uint32 selfsaved; /* packets saved, + because an older packet from the same queue has been dropped + */ + uint32 full_dropped; /* packets dropped, + because pktq is full with higher precedence packets + */ + uint32 dropped; /* packets dropped because pktq per that precedence is full */ + uint32 sacrificed; /* packets dropped, + in order to save one from a queue of a highest priority + */ + uint32 busy; /* packets droped because of hardware/transmission error */ + uint32 retry; /* packets re-sent because they were not received */ + uint32 ps_retry; /* packets retried again prior to moving power save mode */ + uint32 retry_drop; /* packets finally dropped after retry limit */ + uint32 max_avail; /* the high-water mark of the queue capacity for packets - + goes to zero as queue fills + */ + uint32 max_used; /* the high-water mark of the queue utilisation for packets - + increases with use ('inverse' of max_avail) + */ + uint32 queue_capacity; /* the maximum capacity of the queue */ + uint32 rtsfail; /* count of rts attempts that failed to receive cts */ + uint32 acked; /* count of packets sent (acked) successfully */ +} pktq_log_counters_v02_t; + #define sacrified sacrificed typedef struct { @@ -4256,12 +4454,21 @@ typedef struct { char headings[1]; } pktq_log_format_v01_t; +typedef struct { + uint8 num_prec[WL_IOV_MAC_PARAM_LEN]; + pktq_log_counters_v02_t counters[WL_IOV_MAC_PARAM_LEN][WL_IOV_PKTQ_LOG_PRECS]; + uint32 throughput[WL_IOV_MAC_PARAM_LEN][WL_IOV_PKTQ_LOG_PRECS]; + uint32 time_delta; + char headings[1]; +} pktq_log_format_v02_t; + typedef struct { uint32 version; wl_iov_mac_params_t params; union { pktq_log_format_v01_t v01; + pktq_log_format_v02_t v02; } pktq_log; } wl_iov_pktq_log_t; @@ -4419,6 +4626,21 @@ typedef struct { #define VNDR_IE_IWAPID_FLAG 0x40 /* vendor IE in IW advertisement protocol ID field */ #define VNDR_IE_CUSTOM_FLAG 0x100 /* allow custom IE id */ +#if defined(WLP2P) +/* P2P Action Frames flags (spec ordered) */ +#define VNDR_IE_GONREQ_FLAG 0x001000 +#define VNDR_IE_GONRSP_FLAG 0x002000 +#define VNDR_IE_GONCFM_FLAG 0x004000 +#define VNDR_IE_INVREQ_FLAG 0x008000 +#define VNDR_IE_INVRSP_FLAG 0x010000 +#define VNDR_IE_DISREQ_FLAG 0x020000 +#define VNDR_IE_DISRSP_FLAG 0x040000 +#define VNDR_IE_PRDREQ_FLAG 0x080000 +#define VNDR_IE_PRDRSP_FLAG 0x100000 + +#define VNDR_IE_P2PAF_SHIFT 12 +#endif /* WLP2P */ + #define VNDR_IE_INFO_HDR_LEN (sizeof(uint32)) typedef BWL_PRE_PACKED_STRUCT struct { @@ -4493,6 +4715,35 @@ typedef BWL_PRE_PACKED_STRUCT struct { } BWL_POST_PACKED_STRUCT txfailinfo_t; #endif /* WLMEDIA_TXFAILEVENT */ +typedef BWL_PRE_PACKED_STRUCT struct { + uint32 flags; + chanspec_t chanspec; /* txpwr report for this channel */ + chanspec_t local_chanspec; /* channel on which we are associated */ + uint8 local_max; /* local max according to the AP */ + uint8 local_constraint; /* local constraint according to the AP */ + int8 antgain[2]; /* Ant gain for each band - from SROM */ + uint8 rf_cores; /* count of RF Cores being reported */ + uint8 est_Pout[4]; /* Latest tx power out estimate per RF chain */ + uint8 est_Pout_act[4]; /* Latest tx power out estimate per RF chain w/o adjustment */ + uint8 est_Pout_cck; /* Latest CCK tx power out estimate */ + uint8 tx_power_max[4]; /* Maximum target power among all rates */ + uint tx_power_max_rate_ind[4]; /* Index of the rate with the max target power */ + int8 clm_limits[WL_NUMRATES]; /* regulatory limits - 20, 40 or 80MHz */ + int8 clm_limits_subchan1[WL_NUMRATES]; /* regulatory limits - 20in40 or 40in80 */ + int8 clm_limits_subchan2[WL_NUMRATES]; /* regulatory limits - 20in80MHz */ + int8 sar; /* SAR limit for display by wl executable */ + int8 channel_bandwidth; /* 20, 40 or 80 MHz bandwidth? */ + uint8 version; /* Version of the data format wlu <--> driver */ + uint8 display_core; /* Displayed curpower core */ + int8 target_offsets[4]; /* Target power offsets for current rate per core */ + uint32 last_tx_ratespec; /* Ratespec for last transmition */ + uint user_target; /* user limit */ + uint32 board_limit_len; /* length of board limit buffer */ + uint32 target_len; /* length of target power buffer */ + int8 SARLIMIT[MAX_STREAMS_SUPPORTED]; + uint8 pprdata[1]; /* ppr serialization buffer */ +} BWL_POST_PACKED_STRUCT tx_pwr_rpt_t; + #endif /* LINUX_POSTMOGRIFY_REMOVAL */ /* no strict structure packing */ @@ -4545,10 +4796,12 @@ struct wapi_sta_msg_t /* define for apcs reason code */ #define APCS_INIT 0 -#define APCS_IOCTL 1 -#define APCS_CHANIM 2 +#define APCS_IOCTL 1 +#define APCS_CHANIM 2 #define APCS_CSTIMER 3 #define APCS_BTA 4 +#define APCS_TXDLY 5 +#define APCS_NONACSD 6 /* number of ACS record entries */ #define CHANIM_ACS_RECORD 10 @@ -4820,7 +5073,9 @@ typedef struct wl_nic_cnx { uint8 SSID_len; uint8 SSID[32]; struct ether_addr abssid; - uint8 join_period; + uint16 beacon_interval; + uint16 sync_threshold; + uint16 beacon_wait_time; } wl_nic_cnx_t; /* opcode */ @@ -4834,16 +5089,23 @@ typedef struct wl_nic_cnx { typedef struct wl_nic_cfg { uint8 version; uint8 beacon_mode; - uint16 beacon_interval; uint8 diluted_beacon_period; - uint8 repeat_EQC; + uint8 beacon_probability; + uint8 num_awake_window_params; + struct { + uint8 channel_number; + uint8 awake_window_length; + uint8 repeat_EQC; + } awake_window_params[3]; uint8 scan_length; uint8 scan_interval; uint8 scan_probability; - uint8 awake_window_length; - int8 TSF_correction; uint8 ASID; uint8 channel_usage_mode; + uint8 CWmin_af; + uint8 NIC_priority; + uint8 NIC_data_ind; + uint8 allowed_wakeup_delay; } wl_nic_cfg_t; /* version */ @@ -4865,7 +5127,6 @@ typedef struct wl_nic_frm { } wl_nic_frm_t; /* type */ -#define WL_NIC_FRM_MYNET 1 #define WL_NIC_FRM_ACTION 2 /* i/f query */ @@ -4878,8 +5139,17 @@ typedef struct wl_nic_ifq { /* nic_dm iovar */ typedef struct wl_nic_dm { uint8 enab; + uint8 rsvd; + /* the following fields are valid when enabling... */ chanspec_t chspec; + uint8 DATA_priority; + uint8 NIC_priority; } wl_nic_dm_t; + +/* immediate scan request */ +typedef struct wl_nic_isq { + uint8 scan_length; +} wl_nic_isq_t; #endif /* WLNIC */ /* RFAWARE def */ @@ -5024,6 +5294,13 @@ enum { SPATIAL_MODE_MAX_IDX }; +#define WLC_TXCORE_MAX 4 /* max number of txcore supports */ +#define WLC_SUBBAND_MAX 4 /* max number of sub-band supports */ +typedef struct { + uint8 band2g[WLC_TXCORE_MAX]; + uint8 band5g[WLC_SUBBAND_MAX][WLC_TXCORE_MAX]; +} sar_limit_t; + /* IOVAR "mempool" parameter. Used to retrieve a list of memory pool statistics. */ typedef struct wl_mempool_stats { int num; /* Number of memory pools */ @@ -5059,15 +5336,23 @@ typedef struct { #define TRF_MGMT_MAX_PRIORITIES 3 #define TRF_MGMT_FLAG_ADD_DSCP 0x0001 /* Add DSCP to IP TOS field */ -#define TRF_MGMT_FLAG_DISABLE_SHAPING 0x0002 /* Only support traffic clasification */ -#define TRF_MGMT_FLAG_DISABLE_PRIORITY_TAGGING 0x0004 /* Don't override packet's priority */ +#define TRF_MGMT_FLAG_DISABLE_SHAPING 0x0002 /* Don't shape traffic */ +#define TRF_MGMT_FLAG_MANAGE_LOCAL_TRAFFIC 0x0008 /* Manage traffic over our local subnet */ +#define TRF_MGMT_FLAG_FILTER_ON_MACADDR 0x0010 /* filter on MAC address */ +#define TRF_MGMT_FLAG_NO_RX 0x0020 /* do not apply fiters to rx packets */ + +#define TRF_FILTER_MAC_ADDR 0x0001 /* L2 filter use dst mac address for filtering */ +#define TRF_FILTER_IP_ADDR 0x0002 /* L3 filter use ip ddress for filtering */ +#define TRF_FILTER_L4 0x0004 /* L4 filter use tcp/udp for filtering */ +#define TRF_FILTER_FAVORED 0x0010 /* Tag the packet FAVORED */ /* Traffic management priority classes */ typedef enum trf_mgmt_priority_class { - trf_mgmt_priority_low = 0, /* Maps to 802.1p BO */ - trf_mgmt_priority_medium = 1, /* Maps to 802.1p BE */ - trf_mgmt_priority_high = 2, /* Maps to 802.1p VI */ - trf_mgmt_priority_invalid = (trf_mgmt_priority_high + 1) + trf_mgmt_priority_low = 0, /* Maps to 802.1p BK */ + trf_mgmt_priority_medium = 1, /* Maps to 802.1p BE */ + trf_mgmt_priority_high = 2, /* Maps to 802.1p VI */ + trf_mgmt_priority_nochange = 3, /* do not update the priority */ + trf_mgmt_priority_invalid = (trf_mgmt_priority_nochange + 1) } trf_mgmt_priority_class_t; /* Traffic management configuration parameters */ @@ -5149,5 +5434,91 @@ typedef struct powersel_params { uint8 pwr_sel_exp_time; /* Time lapse for expiry of database */ } powersel_params_t; +/* tx pkt delay statistics */ +#define SCB_RETRY_SHORT_DEF 7 /* Default Short retry Limit */ +#define WLPKTDLY_HIST_NBINS 16 /* number of bins used in the Delay histogram */ + +/* structure to store per-AC delay statistics */ +typedef struct scb_delay_stats { + uint32 txmpdu_lost; /* number of MPDUs lost */ + uint32 txmpdu_cnt[SCB_RETRY_SHORT_DEF]; /* retry times histogram */ + uint32 delay_sum[SCB_RETRY_SHORT_DEF]; /* cumulative packet latency */ + uint32 delay_min; /* minimum packet latency observed */ + uint32 delay_max; /* maximum packet latency observed */ + uint32 delay_avg; /* packet latency average */ + uint32 delay_hist[WLPKTDLY_HIST_NBINS]; /* delay histogram */ +} scb_delay_stats_t; + +/* structure for txdelay event */ +typedef struct txdelay_event { + uint8 status; + int rssi; + chanim_stats_t chanim_stats; + scb_delay_stats_t delay_stats[AC_COUNT]; +} txdelay_event_t; + +/* structure for txdelay parameters */ +typedef struct txdelay_params { + uint16 ratio; /* Avg Txdelay Delta */ + uint8 cnt; /* Sample cnt */ + uint8 period; /* Sample period */ + uint8 tune; /* Debug */ +} txdelay_params_t; + #endif /* LINUX_POSTMOGRIFY_REMOVAL */ + +/* fbt_cap: FBT assoc / reassoc modes. */ +#define WLC_FBT_CAP_DRV_4WAY_AND_REASSOC 1 /* Driver 4-way handshake & reassoc (WLFBT). */ + +typedef struct bcnreq { + uint8 bcn_mode; + int dur; + int channel; + struct ether_addr da; + uint16 random_int; + wlc_ssid_t ssid; + uint16 reps; +} bcnreq_t; + +typedef struct rrmreq { + struct ether_addr da; + uint8 reg; + uint8 chan; + uint16 random_int; + uint16 dur; + uint16 reps; +} rrmreq_t; + +typedef struct framereq { + struct ether_addr da; + uint8 reg; + uint8 chan; + uint16 random_int; + uint16 dur; + struct ether_addr ta; + uint16 reps; +} framereq_t; + +typedef struct statreq { + struct ether_addr da; + struct ether_addr peer; + uint16 random_int; + uint16 dur; + uint8 group_id; + uint16 reps; +} statreq_t; + +#ifdef EVENT_LOG_COMPILE +typedef struct wlc_event_log_set_s { + uint8 set; /* Set number */ + uint32 size; /* Size to make/expand */ +} wlc_event_log_set_t; + +typedef struct wlc_event_log_tag_s { + uint16 tag; + uint8 set; + uint8 flags; +} wlc_event_log_tag_t; +#endif /* EVENT_LOG_COMPILE */ + #endif /* _wlioctl_h_ */ |