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path: root/drivers/staging/xgifb/vb_init.c
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Diffstat (limited to 'drivers/staging/xgifb/vb_init.c')
-rw-r--r--drivers/staging/xgifb/vb_init.c258
1 files changed, 130 insertions, 128 deletions
diff --git a/drivers/staging/xgifb/vb_init.c b/drivers/staging/xgifb/vb_init.c
index 33c6876..9e890a1 100644
--- a/drivers/staging/xgifb/vb_init.c
+++ b/drivers/staging/xgifb/vb_init.c
@@ -1,8 +1,8 @@
-#include "vgatypes.h"
-
-#include <linux/version.h>
#include <linux/types.h>
#include <linux/delay.h> /* udelay */
+#include <linux/pci.h>
+
+#include "vgatypes.h"
#include "XGIfb.h"
#include "vb_def.h"
@@ -15,15 +15,13 @@
#include <linux/io.h>
-static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
-
-static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
+static const unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
{ 2, 13, 9, 64, 0x45},
{ 2, 12, 9, 32, 0x35},
{ 2, 12, 8, 16, 0x31},
{ 2, 11, 8, 8, 0x21} };
-static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
+static const unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
{ 2, 14, 11, 128, 0x5D},
{ 2, 14, 10, 64, 0x59},
{ 2, 13, 11, 64, 0x4D},
@@ -37,8 +35,6 @@ static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
{ 2, 12, 9, 8, 0x35},
{ 2, 12, 8, 4, 0x31} };
-static int XGINew_RAMType;
-
static unsigned char
XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
struct vb_device_info *pVBInfo)
@@ -112,14 +108,18 @@ static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
}
udelay(60);
- xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
+ xgifb_reg_set(P3c4,
+ 0x18,
+ pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
xgifb_reg_set(P3c4, 0x19, 0x01);
xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
mdelay(1);
xgifb_reg_set(P3c4, 0x1B, 0x03);
udelay(500);
- xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
+ xgifb_reg_set(P3c4,
+ 0x18,
+ pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
xgifb_reg_set(P3c4, 0x19, 0x00);
xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
@@ -132,23 +132,23 @@ static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
xgifb_reg_set(pVBInfo->P3c4,
0x28,
- pVBInfo->MCLKData[XGINew_RAMType].SR28);
+ pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
xgifb_reg_set(pVBInfo->P3c4,
0x29,
- pVBInfo->MCLKData[XGINew_RAMType].SR29);
+ pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
xgifb_reg_set(pVBInfo->P3c4,
0x2A,
- pVBInfo->MCLKData[XGINew_RAMType].SR2A);
+ pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
xgifb_reg_set(pVBInfo->P3c4,
0x2E,
- pVBInfo->ECLKData[XGINew_RAMType].SR2E);
+ pVBInfo->ECLKData[pVBInfo->ram_type].SR2E);
xgifb_reg_set(pVBInfo->P3c4,
0x2F,
- pVBInfo->ECLKData[XGINew_RAMType].SR2F);
+ pVBInfo->ECLKData[pVBInfo->ram_type].SR2F);
xgifb_reg_set(pVBInfo->P3c4,
0x30,
- pVBInfo->ECLKData[XGINew_RAMType].SR30);
+ pVBInfo->ECLKData[pVBInfo->ram_type].SR30);
/* [Vicent] 2004/07/07,
* When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
@@ -156,12 +156,12 @@ static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
* Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
* Set SR32 D[1:0] = 10b */
if (HwDeviceExtension->jChipType == XG42) {
- if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C) &&
- (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01) &&
- (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C) &&
- (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01)) ||
- ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22) &&
- (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
+ if ((pVBInfo->MCLKData[pVBInfo->ram_type].SR28 == 0x1C) &&
+ (pVBInfo->MCLKData[pVBInfo->ram_type].SR29 == 0x01) &&
+ (((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x1C) &&
+ (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01)) ||
+ ((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x22) &&
+ (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01))))
xgifb_reg_set(pVBInfo->P3c4,
0x32,
((unsigned char) xgifb_reg_get(
@@ -174,8 +174,7 @@ static void XGINew_DDRII_Bootup_XG27(
unsigned long P3c4, struct vb_device_info *pVBInfo)
{
unsigned long P3d4 = P3c4 + 0x10;
- XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
- pVBInfo);
+ pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
/* Set Double Frequency */
@@ -250,8 +249,7 @@ static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
{
unsigned long P3d4 = P3c4 + 0x10;
- XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
- pVBInfo);
+ pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
@@ -307,7 +305,9 @@ static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
xgifb_reg_set(P3c4, 0x16, 0x00);
xgifb_reg_set(P3c4, 0x16, 0x80);
udelay(60);
- xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
+ xgifb_reg_set(P3c4,
+ 0x18,
+ pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
/* xgifb_reg_set(P3c4, 0x18, 0x31); */
xgifb_reg_set(P3c4, 0x19, 0x01);
xgifb_reg_set(P3c4, 0x16, 0x03);
@@ -316,7 +316,9 @@ static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
xgifb_reg_set(P3c4, 0x1B, 0x03);
udelay(500);
/* xgifb_reg_set(P3c4, 0x18, 0x31); */
- xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
+ xgifb_reg_set(P3c4,
+ 0x18,
+ pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
xgifb_reg_set(P3c4, 0x19, 0x00);
xgifb_reg_set(P3c4, 0x16, 0x03);
xgifb_reg_set(P3c4, 0x16, 0x83);
@@ -333,13 +335,13 @@ static void XGINew_DDR1x_DefaultRegister(
XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
xgifb_reg_set(P3d4,
0x82,
- pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
+ pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
xgifb_reg_set(P3d4,
0x85,
- pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
+ pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
xgifb_reg_set(P3d4,
0x86,
- pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
+ pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
xgifb_reg_set(P3d4, 0x98, 0x01);
xgifb_reg_set(P3d4, 0x9A, 0x02);
@@ -354,15 +356,15 @@ static void XGINew_DDR1x_DefaultRegister(
/* CR82 */
xgifb_reg_set(P3d4,
0x82,
- pVBInfo->CR40[11][XGINew_RAMType]);
+ pVBInfo->CR40[11][pVBInfo->ram_type]);
/* CR85 */
xgifb_reg_set(P3d4,
0x85,
- pVBInfo->CR40[12][XGINew_RAMType]);
+ pVBInfo->CR40[12][pVBInfo->ram_type]);
/* CR86 */
xgifb_reg_set(P3d4,
0x86,
- pVBInfo->CR40[13][XGINew_RAMType]);
+ pVBInfo->CR40[13][pVBInfo->ram_type]);
break;
default:
xgifb_reg_set(P3d4, 0x82, 0x88);
@@ -373,7 +375,7 @@ static void XGINew_DDR1x_DefaultRegister(
xgifb_reg_get(P3d4, 0x86);
xgifb_reg_set(P3d4,
0x86,
- pVBInfo->CR40[13][XGINew_RAMType]);
+ pVBInfo->CR40[13][pVBInfo->ram_type]);
xgifb_reg_set(P3d4, 0x82, 0x77);
xgifb_reg_set(P3d4, 0x85, 0x00);
@@ -386,11 +388,11 @@ static void XGINew_DDR1x_DefaultRegister(
/* CR85 */
xgifb_reg_set(P3d4,
0x85,
- pVBInfo->CR40[12][XGINew_RAMType]);
+ pVBInfo->CR40[12][pVBInfo->ram_type]);
/* CR82 */
xgifb_reg_set(P3d4,
0x82,
- pVBInfo->CR40[11][XGINew_RAMType]);
+ pVBInfo->CR40[11][pVBInfo->ram_type]);
break;
}
@@ -415,16 +417,18 @@ static void XGINew_DDR2_DefaultRegister(
xgifb_reg_set(P3d4, 0x86, 0x88);
xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
/* CR86 */
- xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
+ xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
xgifb_reg_set(P3d4, 0x82, 0x77);
xgifb_reg_set(P3d4, 0x85, 0x00);
xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
xgifb_reg_set(P3d4, 0x85, 0x88);
xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
- xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
+ xgifb_reg_set(P3d4,
+ 0x85,
+ pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
if (HwDeviceExtension->jChipType == XG27)
/* CR82 */
- xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]);
+ xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
else
xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
@@ -444,15 +448,15 @@ static void XGINew_SetDRAMDefaultRegister340(
unsigned long P3d4 = Port, P3c4 = Port - 0x10;
- xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][XGINew_RAMType]);
- xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][XGINew_RAMType]);
- xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][XGINew_RAMType]);
- xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][XGINew_RAMType]);
+ xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
+ xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
+ xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
+ xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
temp2 = 0;
for (i = 0; i < 4; i++) {
/* CR6B DQS fine tune delay */
- temp = pVBInfo->CR6B[XGINew_RAMType][i];
+ temp = pVBInfo->CR6B[pVBInfo->ram_type][i];
for (j = 0; j < 4; j++) {
temp1 = ((temp >> (2 * j)) & 0x03) << 2;
temp2 |= temp1;
@@ -467,7 +471,7 @@ static void XGINew_SetDRAMDefaultRegister340(
temp2 = 0;
for (i = 0; i < 4; i++) {
/* CR6E DQM fine tune delay */
- temp = pVBInfo->CR6E[XGINew_RAMType][i];
+ temp = pVBInfo->CR6E[pVBInfo->ram_type][i];
for (j = 0; j < 4; j++) {
temp1 = ((temp >> (2 * j)) & 0x03) << 2;
temp2 |= temp1;
@@ -486,7 +490,7 @@ static void XGINew_SetDRAMDefaultRegister340(
temp2 = 0;
for (i = 0; i < 8; i++) {
/* CR6F DQ fine tune delay */
- temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i];
+ temp = pVBInfo->CR6F[pVBInfo->ram_type][8 * k + i];
for (j = 0; j < 4; j++) {
temp1 = (temp >> (2 * j)) & 0x03;
temp2 |= temp1;
@@ -500,12 +504,16 @@ static void XGINew_SetDRAMDefaultRegister340(
temp3 += 0x01;
}
- xgifb_reg_set(P3d4, 0x80, pVBInfo->CR40[9][XGINew_RAMType]); /* CR80 */
- xgifb_reg_set(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */
+ xgifb_reg_set(P3d4,
+ 0x80,
+ pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
+ xgifb_reg_set(P3d4,
+ 0x81,
+ pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
temp2 = 0x80;
/* CR89 terminator type select */
- temp = pVBInfo->CR89[XGINew_RAMType][0];
+ temp = pVBInfo->CR89[pVBInfo->ram_type][0];
for (j = 0; j < 4; j++) {
temp1 = (temp >> (2 * j)) & 0x03;
temp2 |= temp1;
@@ -515,45 +523,49 @@ static void XGINew_SetDRAMDefaultRegister340(
temp2 += 0x10;
}
- temp = pVBInfo->CR89[XGINew_RAMType][1];
+ temp = pVBInfo->CR89[pVBInfo->ram_type][1];
temp1 = temp & 0x03;
temp2 |= temp1;
xgifb_reg_set(P3d4, 0x89, temp2);
- temp = pVBInfo->CR40[3][XGINew_RAMType];
+ temp = pVBInfo->CR40[3][pVBInfo->ram_type];
temp1 = temp & 0x0F;
temp2 = (temp >> 4) & 0x07;
temp3 = temp & 0x80;
xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
- xgifb_reg_set(P3d4, 0x41, pVBInfo->CR40[0][XGINew_RAMType]); /* CR41 */
+ xgifb_reg_set(P3d4,
+ 0x41,
+ pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
if (HwDeviceExtension->jChipType == XG27)
xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
for (j = 0; j <= 6; j++) /* CR90 - CR96 */
xgifb_reg_set(P3d4, (0x90 + j),
- pVBInfo->CR40[14 + j][XGINew_RAMType]);
+ pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
xgifb_reg_set(P3d4, (0xC3 + j),
- pVBInfo->CR40[21 + j][XGINew_RAMType]);
+ pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
for (j = 0; j < 2; j++) /* CR8A - CR8B */
xgifb_reg_set(P3d4, (0x8A + j),
- pVBInfo->CR40[1 + j][XGINew_RAMType]);
+ pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
if ((HwDeviceExtension->jChipType == XG41) ||
(HwDeviceExtension->jChipType == XG42))
xgifb_reg_set(P3d4, 0x8C, 0x87);
- xgifb_reg_set(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */
+ xgifb_reg_set(P3d4,
+ 0x59,
+ pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
- if (XGINew_RAMType) {
+ if (pVBInfo->ram_type) {
/* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
if (HwDeviceExtension->jChipType == XG27)
@@ -571,11 +583,13 @@ static void XGINew_SetDRAMDefaultRegister340(
xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
}
- xgifb_reg_set(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
+ xgifb_reg_set(P3c4,
+ 0x1B,
+ pVBInfo->SR15[3][pVBInfo->ram_type]); /* SR1B */
}
static void XGINew_SetDRAMSizingType(int index,
- unsigned short DRAMTYPE_TABLE[][5],
+ const unsigned short DRAMTYPE_TABLE[][5],
struct vb_device_info *pVBInfo)
{
unsigned short data;
@@ -587,14 +601,14 @@ static void XGINew_SetDRAMSizingType(int index,
}
static unsigned short XGINew_SetDRAMSizeReg(int index,
- unsigned short DRAMTYPE_TABLE[][5],
+ const unsigned short DRAMTYPE_TABLE[][5],
struct vb_device_info *pVBInfo)
{
unsigned short data = 0, memsize = 0;
int RankSize;
unsigned char ChannelNo;
- RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 32;
+ RankSize = DRAMTYPE_TABLE[index][3] * pVBInfo->ram_bus / 32;
data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
data &= 0x80;
@@ -603,10 +617,10 @@ static unsigned short XGINew_SetDRAMSizeReg(int index,
data = 0;
- if (XGINew_ChannelAB == 3)
+ if (pVBInfo->ram_channel == 3)
ChannelNo = 4;
else
- ChannelNo = XGINew_ChannelAB;
+ ChannelNo = pVBInfo->ram_channel;
if (ChannelNo * RankSize <= 256) {
while ((RankSize >>= 1) > 0)
@@ -620,8 +634,8 @@ static unsigned short XGINew_SetDRAMSizeReg(int index,
(xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
(data & 0xF0));
- /* data |= XGINew_ChannelAB << 2; */
- /* data |= (XGINew_DataBusWidth / 64) << 1; */
+ /* data |= pVBInfo->ram_channel << 2; */
+ /* data |= (pVBInfo->ram_bus / 64) << 1; */
/* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
/* should delay */
@@ -631,14 +645,14 @@ static unsigned short XGINew_SetDRAMSizeReg(int index,
}
static unsigned short XGINew_SetDRAMSize20Reg(int index,
- unsigned short DRAMTYPE_TABLE[][5],
+ const unsigned short DRAMTYPE_TABLE[][5],
struct vb_device_info *pVBInfo)
{
unsigned short data = 0, memsize = 0;
int RankSize;
unsigned char ChannelNo;
- RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 8;
+ RankSize = DRAMTYPE_TABLE[index][3] * pVBInfo->ram_bus / 8;
data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
data &= 0x80;
@@ -647,10 +661,10 @@ static unsigned short XGINew_SetDRAMSize20Reg(int index,
data = 0;
- if (XGINew_ChannelAB == 3)
+ if (pVBInfo->ram_channel == 3)
ChannelNo = 4;
else
- ChannelNo = XGINew_ChannelAB;
+ ChannelNo = pVBInfo->ram_channel;
if (ChannelNo * RankSize <= 256) {
while ((RankSize >>= 1) > 0)
@@ -665,8 +679,8 @@ static unsigned short XGINew_SetDRAMSize20Reg(int index,
(data & 0xF0));
udelay(15);
- /* data |= XGINew_ChannelAB << 2; */
- /* data |= (XGINew_DataBusWidth / 64) << 1; */
+ /* data |= pVBInfo->ram_channel << 2; */
+ /* data |= (pVBInfo->ram_bus / 64) << 1; */
/* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
/* should delay */
@@ -680,12 +694,13 @@ static int XGINew_ReadWriteRest(unsigned short StopAddr,
{
int i;
unsigned long Position = 0;
+ void __iomem *fbaddr = pVBInfo->FBAddr;
- *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
+ writel(Position, fbaddr + Position);
for (i = StartAddr; i <= StopAddr; i++) {
Position = 1 << i;
- *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
+ writel(Position, fbaddr + Position);
}
udelay(500); /* [Vicent] 2004/04/16.
@@ -693,13 +708,12 @@ static int XGINew_ReadWriteRest(unsigned short StopAddr,
Position = 0;
- if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
+ if (readl(fbaddr + Position) != Position)
return 0;
for (i = StartAddr; i <= StopAddr; i++) {
Position = 1 << i;
- if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) !=
- Position)
+ if (readl(fbaddr + Position) != Position)
return 0;
}
return 1;
@@ -730,14 +744,14 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
case XG21:
data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
data = data & 0x01;
- XGINew_ChannelAB = 1; /* XG20 "JUST" one channel */
+ pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
if (data == 0) { /* Single_32_16 */
if ((HwDeviceExtension->ulVideoMemorySize - 1)
> 0x1000000) {
- XGINew_DataBusWidth = 32; /* 32 bits */
+ pVBInfo->ram_bus = 32; /* 32 bits */
/* 22bit + 2 rank + 32bit */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
@@ -766,7 +780,7 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
if ((HwDeviceExtension->ulVideoMemorySize - 1) >
0x800000) {
- XGINew_DataBusWidth = 16; /* 16 bits */
+ pVBInfo->ram_bus = 16; /* 16 bits */
/* 22bit + 2 rank + 16bit */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
@@ -784,7 +798,7 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
} else { /* Dual_16_8 */
if ((HwDeviceExtension->ulVideoMemorySize - 1) >
0x800000) {
- XGINew_DataBusWidth = 16; /* 16 bits */
+ pVBInfo->ram_bus = 16; /* 16 bits */
/* (0x31:12x8x2) 22bit + 2 rank */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
/* 0x41:16Mx16 bit*/
@@ -815,7 +829,7 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
if ((HwDeviceExtension->ulVideoMemorySize - 1) >
0x400000) {
- XGINew_DataBusWidth = 8; /* 8 bits */
+ pVBInfo->ram_bus = 8; /* 8 bits */
/* (0x31:12x8x2) 22bit + 2 rank */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
/* 0x30:8Mx8 bit*/
@@ -834,21 +848,21 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
break;
case XG27:
- XGINew_DataBusWidth = 16; /* 16 bits */
- XGINew_ChannelAB = 1; /* Single channel */
+ pVBInfo->ram_bus = 16; /* 16 bits */
+ pVBInfo->ram_channel = 1; /* Single channel */
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
break;
case XG41:
if (XGINew_CheckFrequence(pVBInfo) == 1) {
- XGINew_DataBusWidth = 32; /* 32 bits */
- XGINew_ChannelAB = 3; /* Quad Channel */
+ pVBInfo->ram_bus = 32; /* 32 bits */
+ pVBInfo->ram_channel = 3; /* Quad Channel */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
return;
- XGINew_ChannelAB = 2; /* Dual channels */
+ pVBInfo->ram_channel = 2; /* Dual channels */
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
@@ -859,7 +873,7 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
return;
- XGINew_ChannelAB = 3;
+ pVBInfo->ram_channel = 3;
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
@@ -873,15 +887,15 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
else
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x39);
} else { /* DDR */
- XGINew_DataBusWidth = 64; /* 64 bits */
- XGINew_ChannelAB = 2; /* Dual channels */
+ pVBInfo->ram_bus = 64; /* 64 bits */
+ pVBInfo->ram_channel = 2; /* Dual channels */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
return;
- XGINew_ChannelAB = 1; /* Single channels */
+ pVBInfo->ram_channel = 1; /* Single channels */
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
@@ -892,14 +906,14 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
return;
- XGINew_ChannelAB = 2; /* Dual channels */
+ pVBInfo->ram_channel = 2; /* Dual channels */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
return;
- XGINew_ChannelAB = 1; /* Single channels */
+ pVBInfo->ram_channel = 1; /* Single channels */
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
@@ -919,8 +933,8 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
It's Different from Other XG40 Series.
*/
if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
- XGINew_DataBusWidth = 32; /* 32 bits */
- XGINew_ChannelAB = 2; /* 2 Channel */
+ pVBInfo->ram_bus = 32; /* 32 bits */
+ pVBInfo->ram_channel = 2; /* 2 Channel */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
@@ -932,7 +946,7 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
return;
- XGINew_ChannelAB = 1; /* Single Channel */
+ pVBInfo->ram_channel = 1; /* Single Channel */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
@@ -943,8 +957,8 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
}
} else { /* DDR */
- XGINew_DataBusWidth = 64; /* 64 bits */
- XGINew_ChannelAB = 1; /* 1 channels */
+ pVBInfo->ram_bus = 64; /* 64 bits */
+ pVBInfo->ram_channel = 1; /* 1 channels */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
@@ -961,15 +975,15 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
default: /* XG40 */
if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
- XGINew_DataBusWidth = 32; /* 32 bits */
- XGINew_ChannelAB = 3;
+ pVBInfo->ram_bus = 32; /* 32 bits */
+ pVBInfo->ram_channel = 3;
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
return;
- XGINew_ChannelAB = 2; /* 2 channels */
+ pVBInfo->ram_channel = 2; /* 2 channels */
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
@@ -979,14 +993,14 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
- XGINew_ChannelAB = 3; /* 4 channels */
+ pVBInfo->ram_channel = 3; /* 4 channels */
} else {
- XGINew_ChannelAB = 2; /* 2 channels */
+ pVBInfo->ram_channel = 2; /* 2 channels */
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
}
} else { /* DDR */
- XGINew_DataBusWidth = 64; /* 64 bits */
- XGINew_ChannelAB = 2; /* 2 channels */
+ pVBInfo->ram_bus = 64; /* 64 bits */
+ pVBInfo->ram_channel = 2; /* 2 channels */
xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
@@ -1022,7 +1036,7 @@ static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
if (memsize == 0)
continue;
- addr = memsize + (XGINew_ChannelAB - 2) + 20;
+ addr = memsize + (pVBInfo->ram_channel - 2) + 20;
if ((HwDeviceExtension->ulVideoMemorySize - 1) <
(unsigned long) (1 << addr))
continue;
@@ -1042,7 +1056,7 @@ static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
if (memsize == 0)
continue;
- addr = memsize + (XGINew_ChannelAB - 2) + 20;
+ addr = memsize + (pVBInfo->ram_channel - 2) + 20;
if ((HwDeviceExtension->ulVideoMemorySize - 1) <
(unsigned long) (1 << addr))
continue;
@@ -1429,8 +1443,10 @@ static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
return temp;
}
-unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
+unsigned char XGIInitNew(struct pci_dev *pdev)
{
+ struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
+ struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
struct vb_device_info VBINF;
struct vb_device_info *pVBInfo = &VBINF;
unsigned char i, temp = 0, temp1;
@@ -1439,8 +1455,6 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
/* unsigned long j, k; */
- unsigned long Temp;
-
pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
@@ -1552,8 +1566,7 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
/* 3.SetMemoryClock
- XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension,
- pVBInfo);
+ pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
*/
printk("11");
@@ -1580,6 +1593,8 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
printk("12");
if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
+ u32 Temp;
+
/* Set AGP Rate */
/*
temp1 = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
@@ -1646,10 +1661,7 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
/* if (ChipsetID == 0x25308086) */
/* xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
- HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension,
- 0x50,
- 0,
- &Temp); /* Get */
+ pci_read_config_dword(pdev, 0x50, &Temp);
Temp >>= 20;
Temp &= 0xF;
@@ -1733,15 +1745,6 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
printk("183");
/* XGINew_DetectMonitor(HwDeviceExtension); */
- pVBInfo->IF_DEF_CH7007 = 0;
- if ((HwDeviceExtension->jChipType == XG21) &&
- (pVBInfo->IF_DEF_CH7007)) {
- printk("184");
- /* sense CRT2 */
- XGI_GetSenseStatus(HwDeviceExtension, pVBInfo);
- printk("185");
-
- }
if (HwDeviceExtension->jChipType == XG21) {
printk("186");
@@ -1764,8 +1767,7 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
}
printk("19");
- XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
- pVBInfo);
+ pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
pVBInfo->P3d4,
generated by cgit v1.1 at 2024-04-20 13:03:40 +0000