aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* drm/i915/lvds: Add AOpen i915GMm-HFS to the list of false-positive LVDSKnut Petersen2011-01-141-0/+8
| | | | | | Signed-off-by: Knut Petersen <knut_petersen@t-online.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
* agp/intel: Fix device names of i845 and 845GOswald Buddenhagen2011-01-142-3/+3
| | | | | | | | They got mixed up when the switch was converted to a table in 2007. Signed-off-by: Oswald Buddenhagen <ossi@kde.org> [ickle: minor changes for 2.6.37+] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Disable GPU semaphores on SandyBridge mobileChris Wilson2011-01-141-1/+2
| | | | | | | | | | | Hopefully, this is a temporary measure whilst the root cause is understood. At the moment, we experience a hard hang whilst looping urbanterror that has been identified as a result of the use of semaphores, but so far only on SNB mobile. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32752 Tested-by: mengmeng.meng@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/execbuffer: Clear domains before beginning reloc processingChris Wilson2011-01-131-4/+3
| | | | | | | | | | | | After reordering the sequence of relocating objects, commit 6fe4f1404, we can no longer rely on seeing all reloc targets prior to performing the relocation. As a result we were ignoring the need to flush objects from the render cache and invalidate the sampler caches, resulting in rendering glitches. So we need to clear the relocation domains earlier. Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Tested-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/execbuffer: Reorder relocations to match new object orderChris Wilson2011-01-131-6/+9
| | | | | | | | | | | | On the fault path, commit 6fe4f140 introduction a regression whereby it changed the sequence of the objects but continued to use the original ordering of relocation entries. The result was that incorrect GTT offsets were being fed into the execbuffer causing lots of misrendering and potential hangs. Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Tested-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Fix error handler to capture the first batch after the seqnoChris Wilson2011-01-131-1/+1
| | | | | | | | | | Whilst we had no older batches on the active list, everything was fine. However, if the GPU is free running and the requests are only being reaped by the periodic retirer, than the current seqno may not be at the start of the list. In this case we need to select the first batch after the last seqno written by the gpu and not inclusive of the seqno. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Add a module option to override the use of SSCChris Wilson2011-01-134-17/+21
| | | | | | | | | | | In order to workaround the issue with LVDS not working on the Lenovo U160 apparently due to using the wrong SSC frequency, add an option to disable SSC. Suggested-by: Lukács, Árpád <lukacs.arpad@gmail.com> Bugzillla: https://bugs.freedesktop.org/show_bug.cgi?id=32748 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
* drm/i915/panel: The backlight is enabled if the current value is non-zeroIndan Zupancic2011-01-121-1/+1
| | | | | | | | | | ... and not if the maximum is non-zero. This fixes the typo introduced in 47356eb6728501452 and preserves the backlight value from boot. [ickle: My thanks also to Indan Zupancic for diagnosing the original regression and suggesting the appropriate fix.] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org # after 47356eb6728501452
* drm/i915/debugfs: Correct format after changing type of err object 'size'Chris Wilson2011-01-121-1/+1
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* Merge branch 'drm-fixes' of ↵Linus Torvalds2011-01-1223-637/+1082
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (39 commits) i915/gtt: fix ordering causing DMAR errors on object teardown. i915/gtt: fix ordering issues with status setup and DMAR drm/i915/execbuffer: Reorder binding of objects to favour restrictions drm/i915: If we hit OOM when allocating GTT pages, clear the aperture drm/i915/evict: Ensure we completely cleanup on failure drm/i915/execbuffer: Correctly clear the current object list upon EFAULT drm/i915/debugfs: Show all objects in the gtt drm/i915: Record AGP memory type upon error drm/i915: Periodically flush the active lists and requests drm/i915/gtt: Unmap the PCI pages after unbinding them from the GTT drm/i915: Record the error batchbuffer on each ring drm/i915: Include TLB miss overhead for computing WM drm/i915: Propagate error from flushing the ring drm/i915: detect & report PCH display error interrupts drm/i915: cleanup rc6 code drm/i915: fix rc6 enabling around suspend/resume drm/i915: re-enable rc6 support for Ironlake+ drm/i915: Make the ring IMR handling private drm/i915/ringbuffer: Simplify the ring irq refcounting drm/i915/debugfs: Show the per-ring IMR ...
| * i915/gtt: fix ordering causing DMAR errors on object teardown.Dave Airlie2011-01-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | Previous to the last GTT rework we always rewrote the GTT then unmapped the object, somehow this got reversed in the rework in 2.6.37-rc5 timeframe. This fix needs to go to stable in an alternate form since the code changed. This fixes DMAR reports on my Ironlake HP2540p. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * i915/gtt: fix ordering issues with status setup and DMARDave Airlie2011-01-121-2/+2
| | | | | | | | | | | | | | | | This code was setting up the status page before setting the DMAR-is-on-bit, so we were getting DMAR errors on the status page. Reverse the two bits of init code to the correct result. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * Merge branch 'drm-intel-fixes' of ↵Dave Airlie2011-01-1223-633/+1078
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ssh://master.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel * 'drm-intel-fixes' of ssh://master.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel: (37 commits) drm/i915/execbuffer: Reorder binding of objects to favour restrictions drm/i915: If we hit OOM when allocating GTT pages, clear the aperture drm/i915/evict: Ensure we completely cleanup on failure drm/i915/execbuffer: Correctly clear the current object list upon EFAULT drm/i915/debugfs: Show all objects in the gtt drm/i915: Record AGP memory type upon error drm/i915: Periodically flush the active lists and requests drm/i915/gtt: Unmap the PCI pages after unbinding them from the GTT drm/i915: Record the error batchbuffer on each ring drm/i915: Include TLB miss overhead for computing WM drm/i915: Propagate error from flushing the ring drm/i915: detect & report PCH display error interrupts drm/i915: cleanup rc6 code drm/i915: fix rc6 enabling around suspend/resume drm/i915: re-enable rc6 support for Ironlake+ drm/i915: Make the ring IMR handling private drm/i915/ringbuffer: Simplify the ring irq refcounting drm/i915/debugfs: Show the per-ring IMR drm/i915: Mask USER interrupts on gen6 (until required) drm/i915: Handle ringbuffer stalls when flushing ...
| | * drm/i915/execbuffer: Reorder binding of objects to favour restrictionsChris Wilson2011-01-112-26/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the mappable portion of the aperture is always a small subset at the start of the GTT, it is allocated preferentially by drm_mm. This is useful in case we ever need to map an object later. However, if you have a large object that can consume the entire mappable region of the GTT this prevents the batchbuffer from fitting and so causing an error. Instead allocate all those that require a mapping up front in order to improve the likelihood of finding sufficient space to bind them. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: If we hit OOM when allocating GTT pages, clear the apertureChris Wilson2011-01-111-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than evicting an object at random, which is unlikely to alleviate the memory pressure sufficient to allow us to continue, zap the entire aperture. That should give the system long enough to recover and reap some pages from the evicted objects, forestalling the allocation error for the new object. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/evict: Ensure we completely cleanup on failureChris Wilson2011-01-111-1/+8
| | | | | | | | | | | | | | | | | | | | | ... and not leave the objects in a inconsistent state. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| | * drm/i915/execbuffer: Correctly clear the current object list upon EFAULTChris Wilson2011-01-111-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before releasing the lock in order to copy the relocation list from user pages, we need to drop all the object references as another thread may usurp and execute another batchbuffer before we reacquire the lock. However, the code was buggy and failed to clear the list... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| | * drm/i915/debugfs: Show all objects in the gttChris Wilson2011-01-111-10/+43
| | | | | | | | | | | | | | | | | | Useful for determining the layout. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Record AGP memory type upon errorChris Wilson2011-01-113-4/+16
| | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Periodically flush the active lists and requestsChris Wilson2011-01-111-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to retire active buffers whilst no client is active, we need to insert our own flush requests onto the ring. This is useful for servers that queue up some rendering and then go to sleep as it allows us to the complete processing of those requests, potentially making that memory available again much earlier. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/gtt: Unmap the PCI pages after unbinding them from the GTTChris Wilson2011-01-111-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dave Airlie spotted that his ILK laptop with DMAR enabled was generating the occasional DMAR warning. "The ordering in the previous code was to rewrite the GTT table before unmapping the pages and that makes sense to me." This is his stable patch ported to d-i-n. Reported-by: Dave Airlie <airlied@redhat.com> Original-patch-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Record the error batchbuffer on each ringChris Wilson2011-01-113-120/+50
| | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Include TLB miss overhead for computing WMChris Wilson2011-01-111-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | The docs recommend that if 8 display lines fit inside the FIFO buffer, then the number of watermark entries should be increased to hide the latency of filling the rest of the FIFO buffer. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Propagate error from flushing the ringChris Wilson2011-01-113-48/+90
| | | | | | | | | | | | | | | | | | ... in order to avoid a BUG() and potential unbounded waits. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: detect & report PCH display error interruptsJesse Barnes2011-01-112-2/+81
| | | | | | | | | | | | | | | | | | | | | | | | FDI and the transcoders can fail for various reasons, so detect those conditions and report on them. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: cleanup rc6 codeJesse Barnes2011-01-114-46/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleanup several aspects of the rc6 code: - misnamed intel_disable_clock_gating function (was only about rc6) - remove commented call to intel_disable_clock_gating - rc6 enabling code belongs in its own function (allows us to move the actual clock gating enable call back into restore_state) - allocate power & render contexts up front, only free on unload (avoids ugly lazy init at rc6 enable time) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: checkpatch cleanup] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: fix rc6 enabling around suspend/resumeJesse Barnes2011-01-112-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling RC6 implies setting a graphics context. Make sure we do that only after the ring has been enabled, otherwise our ring commands will hang. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: re-enable rc6 support for Ironlake+Jesse Barnes2011-01-114-21/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-enable rc6 support on Ironlake for power savings. Adds a debugfs file to check current RC state, adds a missing workaround for Ironlake MI_SET_CONTEXT instructions, and renames MCHBAR_RENDER_STANDBY to RSTDBYCTL to match the docs. Keep RC6 and the power context disabled on pre-ILK. It only seems to hang and doesn't save any power. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Make the ring IMR handling privateChris Wilson2011-01-112-12/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | As the IMR for the USER interrupts are not modified elsewhere, we can separate the spinlock used for these from that of hpd and pipestats. Those two IMR are manipulated under an IRQ and so need heavier locking. Reported-and-tested-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/ringbuffer: Simplify the ring irq refcountingChris Wilson2011-01-112-39/+25
| | | | | | | | | | | | | | | | | | | | | | | | ... and move it under the spinlock to gain the appropriate memory barriers. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32752 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/debugfs: Show the per-ring IMRChris Wilson2011-01-113-14/+24
| | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Mask USER interrupts on gen6 (until required)Chris Wilson2011-01-115-62/+113
| | | | | | | | | | | | | | | | | | | | | Otherwise we may consume 20% of the CPU just handling IRQs whilst rendering. Ouch. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Handle ringbuffer stalls when flushingChris Wilson2011-01-114-43/+65
| | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Enforce write ordering through the GTTChris Wilson2011-01-112-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to ensure that writes through the GTT land before any modification to the MMIO registers and so must impose a mandatory write barrier when flushing the GTT domain. This was revealed by relaxing the write ordering by experimentally mapping the registers and the GATT as write-combining. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Remove impossible testChris Wilson2011-01-111-8/+0
| | | | | | | | | | | | | | | | | | | | | As has_gem is unconditionally set to true, the conditional immediately following that assignment is superfluous. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: avoid reading non-existent PLL reg on Ironlake+Jesse Barnes2011-01-111-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | These functions need to be reworked for Ironlake and above, but until then at least avoid reading non-existent registers. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: combine with a gratuitous tidy] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: add 'reset' parameterChris Wilson2011-01-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When bringing up new hardware, or otherwise experimenting, GPU hangs are a way of life. However, the automatic GPU reset can do more harm than good under these circumstances, as we may wish to capture a full trace for debugging. Based on a patch by Zhenyu Wang. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: fix the wrong latency value while computing wm0Yuanhan Liu2011-01-111-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | On Ironlake, the LP0 latency is hardcoded and in ns unit, while on Sandybridge, it comes from a register and with unit 0.1 us. So, fix the wrong latency value while computing wm0 on Ironlake and Sandybridge. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: support low power watermarks on IronlakeJesse Barnes2011-01-112-130/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch actually makes the watermark code even uglier (if that's possible), but has the advantage of sharing code between SNB and ILK at least. Longer term we should refactor the watermark stuff into its own file and clean it up now that we know how it's supposed to work. Supporting WM2 on my Vaio reduced power consumption by around 0.5W, so this patch is definitely worthwhile (though it also needs lots of test coverage). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: pass the watermark structs arounds] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * agp/intel: Flush the chipset write buffers when changing GTT baseChris Wilson2011-01-112-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flush the chipset write buffers before and after adjusting the GTT base register, just in case. We only modify this value upon initialisation (boot and resume) so there should be no outstanding writes, however there are always those persistent PGTBL_ER that keep getting reported upon resume. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Workaround erratum on i830 for TAIL pointer within last 2 cachelinesChris Wilson2011-01-112-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | On i830 if the tail pointer is set to within 2 cachelines of the end of the buffer, the chip may hang. So instead if the tail were to land in that location, we pad the end of the buffer with NOPs, and start again at the beginning. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Use the mappable sizes determined by GTT for consistency.Chris Wilson2011-01-112-17/+10
| | | | | | | | | | | | | | | | | | There should be no difference, but we can eliminate redundant code. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: support overclocking on Sandy BridgeJesse Barnes2011-01-112-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some configuration, the PCU may allow us to overclock the GPU. Check for this case and adjust the max frequency as appropriate. Also initialize the min/max frequencies to default values as indicated by hardware. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/lvds: Always use 0 to disable the pfit controllerChris Wilson2011-01-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | ... and just any combination of bits & ~PFIT_ENABLE. This way we do not attempt disable to the panel fitter controller uselessly upon intel_lvds_disable(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/panel: Only record the backlight level when it is enabledChris Wilson2011-01-115-8/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By tracking the current status of the backlight we can prevent recording the value of the current backlight when we have disabled it. And so prevent restoring it to 'off' after an unbalanced sequence of intel_lvds_disable/enable. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=22672 Tested-by: Alex Riesen <raa.lkml@gmail.com> Tested-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| | * drm/i915/sdvo: Defer detection of output capabilities until probingChris Wilson2011-01-111-22/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alex Fiestas reported an issue with his HDMI connector being misdetected as DVI unless he had something connected upon boot. By moving the decision as to whether to use HDMI or DVI encoding for the HDMI capable output until we probe the monitor means that we should avoid sending a HDMI signal to a DVI monitor and also correctly detect hardware like Alex's. However, to really determine what connector is soldered onto the wire we need to inspect the VBT sdvo child devices - but can we trust it? Reported-by: Alex Fiestas <alex@eyeos.org> Tested-by: Alex Fiestas <alex@eyeos.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32828 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| | * drm/i915: fix calculation of eDP signal levels on SandybridgeYuanhan Liu2011-01-112-11/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some voltage swing/pre-emphasis level use the same value on eDP Sandybridge, like 400mv_0db and 600mv_0db are with the same value of (0x0 << 22). So, fix them, and point out the value if it isn't a supported voltage swing/pre-emphasis level. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| | * drm/i915/crt: Check for a analog monitor in case of DVI-IDavid Müller2011-01-111-5/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since Linux 2.6.36 the digital output on my system (855GME + DVI-I) is not working any longer. The analog output is always activated regardless of the type of monitor attached. The culprit seems to be intel_crt_detect_ddc(), which returns true as soon as an ACK from the EDID device is received. Obviously this approach does not work with DVI-I where the analog and digital outputs share a common DDC bus. In a similar manner to the shared DDC wire, ala the "Mac Mini Hack", we need an additional check to make sure that there really is an analog device attached to the DDC. Signed-off-by: David Müller <d.mueller@elsoft.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| | * drm/i915: make DP training try a little harderJesse Barnes2011-01-111-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When trying to do channel equalization, we need to make sure we still have clock recovery on all lanes while training. We also need to try clock recovery again if we lose the clock or if channel eq fails 5 times. We'll try clock recovery up to 5 more times before giving up entirely. Gets suspend/resume working on my Vaio again and brings us back into compliance with the DP training sequence spec. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: check eDP encoder correctly when setting modesJesse Barnes2011-01-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We were using a stale pointer in the check which caused us to use CPU attached DP params when we should have been using PCH attached params. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31988 Tested-by: Jan-Hendrik Zab <jan@jhz.name> Tested-by: Christoph Lukas <christoph.lukas@gmx.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
generated by cgit v1.1 at 2024-09-22 19:27:20 +0000