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* update other arm platforms from 3.2.72 and also merge some general arm code ↵Wolfgang Wiedmeyer2015-10-231-49/+118
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* merged more from 3.0.101 that is not related to the platformWolfgang Wiedmeyer2015-10-231-1/+1
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* Merge remote-tracking branch 'kernelorg/linux-3.0.y' into 3_0_64Andrew Dodd2013-02-271-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/Kconfig arch/arm/include/asm/hwcap.h arch/arm/kernel/smp.c arch/arm/plat-samsung/adc.c drivers/gpu/drm/i915/i915_reg.h drivers/gpu/drm/i915/intel_drv.h drivers/mmc/core/sd.c drivers/net/tun.c drivers/net/usb/usbnet.c drivers/regulator/max8997.c drivers/usb/core/hub.c drivers/usb/host/xhci.h drivers/usb/serial/qcserial.c fs/jbd2/transaction.c include/linux/migrate.h kernel/sys.c kernel/time/timekeeping.c lib/genalloc.c mm/memory-failure.c mm/memory_hotplug.c mm/mempolicy.c mm/page_alloc.c mm/vmalloc.c mm/vmscan.c mm/vmstat.c scripts/Kbuild.include Change-Id: I91e2d85c07320c7ccfc04cf98a448e89bed6ade6
| * ARM: 7532/1: decompressor: reset SCTLR.TRE for VMSA ARMv7 coresMatthew Leach2012-10-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit e1e5b7e4251c7538ca08c2c5545b0c2fbd8a6635 upstream. This patch zeroes the SCTLR.TRE bit prior to setting the mapping as cacheable for ARMv7 cores in the decompressor, ensuring that the memory region attributes are obtained from the C and B bits, not from the page tables. Cc: Nicolas Pitre <nico@fluxnic.net> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | samsung update 1codeworkx2012-06-021-1/+42
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* ARM: 6961/1: zImage: Add build-time check for correctly-sized proc_type entriesDave Martin2011-06-211-1/+13
| | | | | | | | | | | | | | | It is easy to mis-maintain the proc_types table such that the entries become wrongly-sized and misaligned when the kernel is built in Thumb-2. This patch adds an assembly-time check which will turn most common size/alignment mistakes in this table into build failures, to avoid having to debug the boot-time kernel hang which would happen if the resulting kernel were actually booted. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6954/1: zImage: fix Thumb2 breakageNicolas Pitre2011-06-091-3/+3
| | | | | | | | | | | Commit af3e4fd37a "ARM: 6859/1: Add writethrough dcache support for ARM926EJS processor" broke Thumb2 compilation by omitting to maintain the wide encoding for the added branch instructions which made the ARM926EJ-S record smaller than expected, breaking the record walk code. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'devel-stable' into for-linusRussell King2011-05-231-11/+19
|\ | | | | | | | | | | Conflicts: arch/arm/Kconfig arch/arm/mach-ns9xxx/include/mach/uncompress.h
| * Merge branch 'zImage_fixes' of git://git.linaro.org/people/nico/linux into ↵Russell King2011-05-071-15/+42
| |\ | | | | | | | | | devel-stable
| | * ARM: zImage: make sure no GOTOFF relocs are used with .bss symbolsNicolas Pitre2011-05-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To be able to relocate the .bss section at run time independently from the rest of the code, we must make sure that no GOTOFF relocations are used with .bss symbols. This usually means that no global variables can be marked static unless they're also const. To enforce this, suffice to fail the build whenever a private symbol is allocated to .bss and list those symbols for convenience. The user_stack and user_stack_end labels in head.S were converted into non exported symbols to remove false positives. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
| | * ARM: zImage: no need to get the decompressed size from the filesystemNicolas Pitre2011-05-071-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit d239b1dc093d the hardcoded 4x estimate for the decompressed kernel size was replaced by the exact Image file size and passed to the linker as a symbol value. Turns out that this is unneeded as the size is already included at the end of the compressed piggy data. For those compressed formats that don't include this data, the build system already takes care of appending it using size_append in scripts/Makefile.lib. So let's use that instead. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
| * | ARM: PJ4: remove the ARMv6 compatible cache method entriesNicolas Pitre2011-05-031-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell PJ4 is ARMv7 capable, so we don't support it in ARMv6 mode anymore. Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Acked-by: Saeed Bishara <saeed.bishara@gmail.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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*---. \ \ Merge branches 'consolidate', 'ep93xx', 'fixes', 'misc', 'mmci', 'remove' ↵Russell King2011-05-231-0/+16
|\ \ \ \ \ | | |_|/ / | |/| | | | | | | | and 'spear' into for-linus
| | * | | ARM: 6859/1: Add writethrough dcache support for ARM926EJS processorMark A. Greer2011-05-121-0/+16
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM kernel supports writethrough data cache via the CONFIG_CPU_DCACHE_WRITETHROUGH option. However, that functionality wasn't implemented in the arch/arm/boot/compressed code. It is now necessary due to a new ARM926EJS processor that has an issue with writeback data cache. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | Merge first four commits of 'zImage_fixes' of ↵Russell King2011-05-071-11/+24
|\ \ \ \ | |/ / / |/| | / | | |/ | |/| git://git.linaro.org/people/nico/linux into fixes
| * | ARM: zImage: the page table memory must be considered before relocationNicolas Pitre2011-05-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For correctness, the initial page table located right before the decompressed kernel should be considered when determining if relocation is required. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com>
| * | ARM: zImage: make sure not to relocate on top of the relocation codeNicolas Pitre2011-05-071-10/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the zImage load address is slightly below the relocation address, there is a risk for the copied data to overwrite the copy loop or cache flush code that the relocation process requires. Always bump the relocation address by the size of that code to avoid this issue. Noticed by Tony Lindgren <tony@atomide.com>. While at it, let's start the copy from the restart symbol which makes the above code size computation possible by the assembler directly (same sections), given that we don't need to preserve the code before that point anyway. And therefore we don't need to carry the _start pointer in r5 anymore. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
| * | ARM: zImage: Fix bad SP address after relocating kernelTony Lindgren2011-05-061-0/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise cache_clean_flush can overwrite some of the relocated area depending on where the kernel image gets loaded. This fixes booting on n900 after commit 6d7d0ae51574943bf571d269da3243257a2d15db (ARM: 6750/1: improvements to compressed/head.S). Thanks to Aaro Koskinen <aaro.koskinen@nokia.com> for debugging the address of the relocated area that gets corrupted, and to Nicolas Pitre <nicolas.pitre@linaro.org> for the other uncompress related fixes. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* | ARM: 6826/1: Merge v6 and v7 DEBUG_LL DCC supportStephen Boyd2011-03-281-9/+1
|/ | | | | | | | | | | | | | | | The inline assembly differences for v6 vs. v7 are purely optimizations. On a v7 processor, an mrc with the pc sets the condition codes to the 28-31 bits of the register being read. It just so happens that the TX/RX full bits the DCC support code is testing for are high enough in the register to be put into the condition codes. On a v6 processor, this "feature" isn't implemented and thus we have to do the usual read, mask, test operations to check for TX/RX full. Thus, we can drop the v7 implementation and just use the v6 implementation for both. Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'v6v7' into develRussell King2011-03-161-1/+1
|\ | | | | | | | | | | | | Conflicts: arch/arm/include/asm/cacheflush.h arch/arm/include/asm/proc-fns.h arch/arm/mm/Kconfig
| * ARM: v6k: introduce CPU_V6K optionRussell King2011-02-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a CPU_V6K configuration option for platforms to select if they have a V6K CPU core. This allows us to identify whether we need to support ARMv6 CPUs without the V6K SMP extensions at build time. Currently CPU_V6K is just an alias for CPU_V6, and all places which reference CPU_V6 are replaced by (CPU_V6 || CPU_V6K). Select CPU_V6K from platforms which are known to be V6K-only. Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6750/1: improvements to compressed/head.SNicolas Pitre2011-02-231-129/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the case of a conflict between the memory used by the compressed kernel with its decompressor code and the memory used for the decompressed kernel, we currently store the later after the former and relocate it afterwards. This would be more efficient to do this the other way around i.e. relocate the compressed data up front instead, resulting in a smaller copy. That also has the advantage of making the code smaller and more straight forward. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6663/1: make Thumb2 kernel entry point more similar to the ARM oneNicolas Pitre2011-02-231-5/+5
|/ | | | | | | | | | Some installers would binary patch the kernel zImage to replace the first few nops with custom instructions. This breaks the Thumb2 kernel as the mode switch is right at the beginning. Let's move it towards the end of the nop sequence instead. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6503/1: Thumb-2: Restore sensible zImage header layout for ↵Dave Martin2010-11-301-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_THUMB2_KERNEL The code which makes up the zImage header intends to leave a 32-byte gap followed by a branch to the real entry point, a magic number, and a word containing the absolute entry point address. This gets messed up with with CONFIG_THUMB2_KERNEL, because the size of the initial padding NOPs changes. Instead, the header can be made fully compatible by restoring it to ARM. In the Thumb-2 case, we can replace the initial NOPs with a sequence which switches to Thumb and jumps to the real entry point. As a consequence, the zImage entry point is now always ARM, so no special magic is needed any more for the uImage rules in the Thumb-2 case. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6502/1: Thumb-2: Fix CONFIG_THUMB2_KERNEL breakage in compressed/head.SDave Martin2010-11-301-2/+4
| | | | | | | | | | | | | | | | | | Some instruction operand combinations are used here which are nor permitted in Thumb-2. In particular, most uses of pc as an operand are disallowed in Thumb-2, and deprecated in ARM from ARMv7 onwards. The modified code introduced by this patch should be compatible with all architecture versions >= v3, with or without CONFIG_THUMB2_KERNEL. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: avoid marking decompressor .stack section as having contentsRussell King2010-11-221-1/+1
| | | | | | | | | The .stack section doesn't contain any contents, and doesn't require initialization either. Rather than marking the output section with 'NOLOAD' but still having it exist in the object files, mark it with %nobits which avoids the assembler marking the section with 'CONTENTS'. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Partially revert "Auto calculate ZRELADDR and provide option for ↵Russell King2010-09-091-1/+1
| | | | | | | | | | | | | exceptions" Partially revert e69edc7, which introduced automatic zreladdr support. The change in the way the manual definition is defined seems to be error and conflict prone. Go back to the original way we were handling this for the time being, while keeping the automatic zreladdr facility. Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6286/1: fix Thumb-2 decompressor broken by "Auto calculate ZRELADDR"Rabin Vincent2010-08-101-3/+2
| | | | | | | | | | | | | | | "ARM: Auto calculate ZRELADDR and provide option for exceptions" broke the Thumb-2 decompressor because it removed an entry in the LC0 table but didn't adjust the offset the Thumb-2 code uses to load the SP from that table. Fix it, and also change the ARM code to use the separate SP-load since ARM instructions that include the SP in the LDM register list are deprecated. Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Auto calculate ZRELADDR and provide option for exceptionsEric Miao2010-07-121-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As long as the zImage is placed within the 128MB range from the start of memory, ZRELADDR (Address where the decompressed kernel will be placed, usually == PHYS_OFFSET + TEXT_OFFSET) can be determined at run-time by masking PC with 0xf80000000. Running through all the Makefile.boot, all those zreladdr-y addresses == 0x[0-f][08]00_0000 + TEXT_OFFSET can be determined at run-time. Option CONFIG_AUTO_ZRELADDR and CONFIG_ZRELADDR are introduced, CONFIG_ZRELADDR _must_ be explicitly specified if: - ((zreladdr-y - TEXT_OFFSET) & ~0xf8000000) != 0, which means masking PC with 0xf8000000 will result in an incorrect address. Currently this is only a problem on u300. - or the assumption of the zImage being loaded by the bootloader within the first 128MB of RAM is incorrect - or when ZBOOT_ROM is used, where the above assumption is usually wrong. [ukleinek: changed mask from 0xf0000000 to 0xf8000000 for mx1 and shark + some review fixes from the mailing list] Original-Idea-and-Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Eric Miao <eric.miao@canonical.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
* ARM: Remove unused PARAMS_PHYS from arch/arm/boot/compressedEric Miao2010-07-071-1/+1
| | | | | | | | | The only reference in arch/arm/boot/compressed to PARAMS_PHYS is params() in head.S, which can be directly converted to the exact address as specified by arch/arm/mach-rpc/Makefile.boot. Signed-off-by: Eric Miao <eric.miao@canonical.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
* ARM: zImage: annotate debug functions about corrupted registersUwe Kleine-König2010-06-171-0/+4
| | | | Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
* ARM: zImage: fix comments for cache_on, cache_off and cache_clean_flushUwe Kleine-König2010-06-171-5/+6
| | | | | | | | | | | This adds missing registers to the list of corrupted registers and removes a wrong comment about r9 on entry While at it the formatting of the comment to cache_off is changed to resemble the other two. Acked-by: Eric Miao <eric.miao@canonical.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
* ARM: zImage: __armv3_mpu_cache_flush: respect should-be-zero specificationUwe Kleine-König2010-06-171-1/+1
| | | | | | | | Probably the register content for cache operations is "don't care" in practice, but as r1 is explicitly zeroed, use that one. Acked-by: Eric Miao <eric.miao@canonical.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
* ARM: zImage: some comments for __armv3_mpu_cache_onUwe Kleine-König2010-06-171-0/+6
| | | | | | | | __armv3_mpu_cache_on seems broken. As there is noone around who knows about these machines just keep the code as is but point out the strange things. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
* ARM: zImage: don't hard code the stack size twiceUwe Kleine-König2010-06-171-1/+2
| | | | | | Acked-by: Eric Miao <eric.miao@canonical.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
* [ARM] pxa: update cpuid pattern for pxa9xx in head.SHaojian Zhuang2010-05-061-8/+2
| | | | | | | | Update CPUID pattern of PXA9xx in head.S and fix the duplicate entries for pxa935. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* ARM: 6031/1: fix Thumb-2 decompressorRabin Vincent2010-04-071-1/+1
| | | | | | | | | | | 98e12b5a6e05413 ("ARM: Fix decompressor's kernel size estimation for ROM=y") broke the Thumb-2 decompressor because it added an entry in the LC0 table but didn't adjust the offset the Thumb-2 code uses to load the SP from that table. Fix it. Cc: stable <stable@kernel.org> Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5990/1: ARM: use __armv5tej_mmu_cache_flush for V5TEJ instead of ↵Sascha Hauer2010-03-151-1/+1
| | | | | | | | | __armv4_mmu_cache_flush This got broken with commit 0e056f20 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'master' into for-linusRussell King2010-03-081-27/+23
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| * ARM: Fix decompressor's kernel size estimation for ROM=yRussell King2010-02-261-27/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2552fc2 changed the way the decompressor decides if it is safe to decompress the kernel directly to its final location. Unfortunately, it took the top of the compressed data as being the stack pointer, which it is for ROM=n cases. However, for ROM=y, the stack pointer is not relevant, and results in the wrong answer. Fix this by explicitly storing the end of the biggybacked data in the decompressor, and use that to calculate the compressed image size. CC: <stable@kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 5910/1: ARM: Add tmp register for addruart and loadspTony Lindgren2010-02-121-10/+10
|/ | | | | | | | | | | | | | Otherwise more complicated uart configuration won't be possible. We can use r1 for tmp register for both head.S and debug.S. NOTE: This patch depends on another patch to add the the tmp register into all debug-macro.S files. That can be done with: $ sed -i -e "s/addruart,rx|addruart, rx/addruart, rx, tmp/" arch/arm/*/include/*/debug-macro.S Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5884/1: arm: Fix DCC console for v7Tony Lindgren2010-01-191-0/+8
| | | | | | | | | | | | | | | | | | | | | | Without this patch arch/arm/compressed/head.S defaults to generic DCC code that does not work for v7. For more information on the v7 DCC, see Cortex-A8 TRM "12.11.1 Debug communications channel". To use it with post 2.6.33-rc1 or later, you need to have: CONFIG_DEBUG_LL=y ONFIG_DEBUG_ICEDCC=y CONFIG_EARLY_PRINTK=y Earlier kernels need commit 93fd03a8c6728b58879f8af20ffd55d9c32a778b backported. Tested on omap3430. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: add base support for Marvell Dove SoCSaeed Bishara2009-11-271-0/+6
| | | | | | | | | | | The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* nommu: Fix compressed/head.S to not perform MMU specific operationsCatalin Marinas2009-07-241-0/+14
| | | | Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* Thumb-2: Implement the unified boot codeCatalin Marinas2009-07-241-68/+99
| | | | | | | This patch adds the ARM/Thumb-2 unified support for the arch/arm/boot/* files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* Thumb-2: Add some .align statements to the .S filesCatalin Marinas2009-07-241-0/+3
| | | | | | | | Since the Thumb-2 instructions can be 16-bit wide, data in the .text sections may not be aligned to a 32-bit word and this leads to unaligned exceptions. This patch does not affect the ARM code generation. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* [ARM] Add old Feroceon support to compressed/head.SJoonyoung Shim2009-06-191-0/+9
| | | | | | | | | This patch supports the cache handling for some old Feroceon cores for which the CPU ID is like 0x41159260. This is a complement to commit ab6d15d50637fc25ee941710b23fed09ceb28db3. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* Add core support for ARMv6/v7 big-endianCatalin Marinas2009-05-301-0/+6
| | | | | | | | | | | | | | | | Starting with ARMv6, the CPUs support the BE-8 variant of big-endian (byte-invariant). This patch adds the core support: - setting of the BE-8 mode via the CPSR.E register for both kernel and user threads - big-endian page table walking - REV used to rotate instructions read from memory during fault processing as they are still little-endian format - Kconfig and Makefile support for BE-8. The --be8 option must be passed to the final linking stage to convert the instructions to little-endian Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* Merge branch 'for-rmk' of git://gitorious.org/linux-gemini/mainline into develRussell King2009-03-261-0/+26
|\ | | | | | | | | | | | | Conflicts: arch/arm/mm/Kconfig Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: Add support for FA526 v2Paulius Zaleckas2009-03-251-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for Faraday FA526 core. This core is used at least by: Cortina Systems Gemini and Centroid family Cavium Networks ECONA family Grain Media GM8120 Pixelplus ImageARM Prolific PL-1029 Faraday IP evaluation boards v2: - move TLB_BTB to separate patch - update copyrights Signed-off-by: Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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