kernel_samsung_smdk4412.git - kernel for Galaxy S3

	Commit message (Collapse)	Author	Age	Files	Lines
*	Dove: Attempt to fix PMU/RTC interrupts	Russell King - ARM Linux	2012-12-10	1	-1/+13
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	commit 5d3df935426271016b895aecaa247101b4bfa35e upstream. Fix the acknowledgement of PMU interrupts on Dove: some Dove hardware has not been sensibly designed so that interrupts can be handled in a race free manner. The PMU is one such instance. The pending (aka 'cause') register is a bunch of RW bits, meaning that these bits can be both cleared and set by software (confirmed on the Armada-510 on the cubox.) Hardware sets the appropriate bit when an interrupt is asserted, and software is required to clear the bits which are to be processed. If we write ~(1 << bit), then we end up asserting every other interrupt except the one we're processing. So, we need to do a read-modify-write cycle to clear the asserted bit. However, any interrupts which occur in the middle of this cycle will also be written back as zero, which will also clear the new interrupts. The upshot of this is: there is _no_ way to safely clear down interrupts in this register (and other similarly behaving interrupt pending registers on this device.) The patch below at least stops us creating new interrupts. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
*	arm: Fold irq_set_chip/irq_set_handler	Thomas Gleixner	2011-03-29	1	-2/+1
\| \| \| \| \| \|	Use irq_set_chip_and_handler() instead. Converted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
*	arm: Cleanup the irq namespace	Thomas Gleixner	2011-03-29	1	-8/+8
\| \| \| \| \| \|	Convert to the new function names. Automated with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
*	arm: dove: Use proper irq accessor functions	Thomas Gleixner	2011-03-29	1	-3/+2
\| \| \| \| \| \|	Remove the obsolete desc_handle_irq() helper. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
*	ARM: Remove dependency of plat-orion GPIO code on mach directory includes.	Lennert Buytenhek	2011-03-03	1	-16/+14
\| \| \| \| \| \| \| \| \| \| \| \|	This patch makes the various mach dirs that use the plat-orion GPIO code pass in GPIO-related platform info (GPIO controller base address, secondary base IRQ number, etc) explicitly, instead of having plat-orion get those values by including a mach dir include file -- the latter mechanism is problematic if you want to support multiple ARM platforms in the same kernel image. Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
*	ARM: dove: irq_data conversion.	Lennert Buytenhek	2011-01-13	1	-9/+9
\| \| \| \| \|	Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca> Acked-by: Nicolas Pitre <nico@fluxnic.net>
*	ARM: add base support for Marvell Dove SoC	Saeed Bishara	2009-11-27	1	-0/+133
	The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>